Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	12409404	1			T1	2867		T2	14174		T4	451
all_values[1]	12409404	1			T1	2867		T2	14174		T4	451
all_values[2]	12409404	1			T1	2867		T2	14174		T4	451

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116400

1

T1

148

T7

6

T5

20

auto[1]

37111812

1

T1

8453

T2

42522

T4

1353

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30930620

1

T1

7579

T2

39387

T4

1299

auto[1]

6297592

1

T1

1022

T2

3135

T4

54

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	45807	1			T1	74		T5	1		T11	177
all_values[0]	auto[0]	auto[1]	322	1			T5	6		T11	4		T89	2
all_values[0]	auto[1]	auto[0]	12331026	1			T1	2783		T2	14131		T4	421
all_values[0]	auto[1]	auto[1]	32249	1			T1	10		T2	43		T4	30
all_values[1]	auto[0]	auto[0]	27540	1			T7	6		T5	1		T11	11
all_values[1]	auto[0]	auto[1]	160	1			T5	3		T11	2		T20	3
all_values[1]	auto[1]	auto[0]	12381431	1			T1	2867		T2	14174		T4	451
all_values[1]	auto[1]	auto[1]	273	1			T5	4		T11	6		T20	3
all_values[2]	auto[0]	auto[0]	25421	1			T5	9		T11	12		T6	2
all_values[2]	auto[0]	auto[1]	17150	1			T1	74		T11	6		T65	2193
all_values[2]	auto[1]	auto[0]	6119395	1			T1	1855		T2	11082		T4	427
all_values[2]	auto[1]	auto[1]	6247438	1			T1	938		T2	3092		T4	24