Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5624486

1

T1

1406

T2

5754

T4

14

auto[1]

2248545

1

T1

1446

T2

8308

T4

24

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2233527

1

T1

1045

T2

6434

T4

22

auto[1]

5639504

1

T1

1807

T2

7628

T4

16

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4756106

1

T1

1103

T2

5899

T4

19

auto[1]

3116925

1

T1

1749

T2

8163

T4

19

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6386316	1			T1	2734		T2	13402		T4	12
fifo_depth[1]	256285	1			T1	60		T2	369		T7	3
fifo_depth[2]	197977	1			T1	38		T2	202		T7	2
fifo_depth[3]	150028	1			T1	16		T2	64		T7	1
fifo_depth[4]	120493	1			T1	4		T2	19		T5	341
fifo_depth[5]	97764	1			T2	5		T5	93		T10	4
fifo_depth[6]	91547	1			T2	1		T5	27		T10	2
fifo_depth[7]	79048	1			T5	8		T11	4		T6	94

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1486715

1

T1

118

T2

660

T4

26

auto[1]

6386316

1

T1

2734

T2

13402

T4

12

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7859659

1

T1

2852

T2

14062

T4

34

auto[1]

13372

1

T4

4

T15

3

T91

182

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

88240

1

T2

71

T4

4

T5

335

auto[0]

auto[0]

auto[0]

auto[1]

82663

1

T2

174

T4

4

T5

365

auto[0]

auto[0]

auto[1]

auto[0]

625814

1

T4

1

T5

282

T11

1676

auto[0]

auto[0]

auto[1]

auto[1]

91577

1

T1

41

T2

44

T4

6

auto[0]

auto[1]

auto[0]

auto[0]

149111

1

T1

28

T2

25

T4

3

auto[0]

auto[1]

auto[0]

auto[1]

163435

1

T1

31

T2

52

T4

4

auto[0]

auto[1]

auto[1]

auto[0]

139820

1

T1

18

T2

155

T5

856

auto[0]

auto[1]

auto[1]

auto[1]

146055

1

T2

139

T4

4

T5

1519

auto[1]

auto[0]

auto[0]

auto[0]

237434

1

T1

4

T2

1302

T4

2

auto[1]

auto[0]

auto[0]

auto[1]

233993

1

T2

2908

T7

18

T5

6392

auto[1]

auto[0]

auto[1]

auto[0]

3151443

1

T1

516

T2

1

T7

17

auto[1]

auto[0]

auto[1]

auto[1]

244942

1

T1

542

T2

1399

T4

2

auto[1]

auto[1]

auto[0]

auto[0]

597353

1

T1

571

T2

1197

T4

3

auto[1]

auto[1]

auto[0]

auto[1]

681298

1

T1

411

T2

705

T4

2

auto[1]

auto[1]

auto[1]

auto[0]

635271

1

T1

269

T2

3003

T4

1

auto[1]

auto[1]

auto[1]

auto[1]

604582

1

T1

421

T2

2887

T4

2

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

323703

1

T1

4

T2

1373

T4

5

auto[0]

auto[0]

auto[0]

auto[1]

314299

1

T2

3082

T4

4

T7

18

auto[0]

auto[0]

auto[1]

auto[0]

3775382

1

T1

516

T2

1

T4

1

auto[0]

auto[0]

auto[1]

auto[1]

333311

1

T1

583

T2

1443

T4

7

auto[0]

auto[1]

auto[0]

auto[0]

745320

1

T1

599

T2

1222

T4

5

auto[0]

auto[1]

auto[0]

auto[1]

843631

1

T1

442

T2

757

T4

6

auto[0]

auto[1]

auto[1]

auto[0]

774658

1

T1

287

T2

3158

T4

1

auto[0]

auto[1]

auto[1]

auto[1]

749355

1

T1

421

T2

3026

T4

5

auto[1]

auto[0]

auto[0]

auto[0]

1971

1

T4

1

T15

2

T91

4

auto[1]

auto[0]

auto[0]

auto[1]

2357

1

T91

57

T92

43

T29

1

auto[1]

auto[0]

auto[1]

auto[0]

1875

1

T15

1

T91

56

T92

424

auto[1]

auto[0]

auto[1]

auto[1]

3208

1

T4

1

T27

2

T92

30

auto[1]

auto[1]

auto[0]

auto[0]

1144

1

T4

1

T27

1

T92

237

auto[1]

auto[1]

auto[0]

auto[1]

1102

1

T27

1

T31

97

T115

3

auto[1]

auto[1]

auto[1]

auto[0]

433

1

T91

30

T93

2

T30

1

auto[1]

auto[1]

auto[1]

auto[1]

1282

1

T4

1

T91

35

T27

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	237434	1			T1	4		T2	1302		T4	2
fifo_depth[0]	auto[0]	auto[0]	auto[1]	233993	1			T2	2908		T7	18		T5	6392
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3151443	1			T1	516		T2	1		T7	17
fifo_depth[0]	auto[0]	auto[1]	auto[1]	244942	1			T1	542		T2	1399		T4	2
fifo_depth[0]	auto[1]	auto[0]	auto[0]	597353	1			T1	571		T2	1197		T4	3
fifo_depth[0]	auto[1]	auto[0]	auto[1]	681298	1			T1	411		T2	705		T4	2
fifo_depth[0]	auto[1]	auto[1]	auto[0]	635271	1			T1	269		T2	3003		T4	1
fifo_depth[0]	auto[1]	auto[1]	auto[1]	604582	1			T1	421		T2	2887		T4	2
fifo_depth[1]	auto[0]	auto[0]	auto[0]	7740	1			T2	35		T5	193		T11	161
fifo_depth[1]	auto[0]	auto[0]	auto[1]	7597	1			T2	103		T5	191		T11	153
fifo_depth[1]	auto[0]	auto[1]	auto[0]	165315	1			T5	138		T11	1116		T13	1014
fifo_depth[1]	auto[0]	auto[1]	auto[1]	8276	1			T1	20		T2	25		T5	259
fifo_depth[1]	auto[1]	auto[0]	auto[0]	16347	1			T1	11		T2	14		T5	900
fifo_depth[1]	auto[1]	auto[0]	auto[1]	18136	1			T1	15		T2	35		T7	3
fifo_depth[1]	auto[1]	auto[1]	auto[0]	16531	1			T1	14		T2	89		T5	454
fifo_depth[1]	auto[1]	auto[1]	auto[1]	16343	1			T2	68		T5	690		T10	1
fifo_depth[2]	auto[0]	auto[0]	auto[0]	6546	1			T2	28		T5	94		T11	64
fifo_depth[2]	auto[0]	auto[0]	auto[1]	6569	1			T2	49		T5	113		T11	84
fifo_depth[2]	auto[0]	auto[1]	auto[0]	117394	1			T5	84		T11	391		T13	278
fifo_depth[2]	auto[0]	auto[1]	auto[1]	7033	1			T1	13		T2	12		T5	139
fifo_depth[2]	auto[1]	auto[0]	auto[0]	14962	1			T1	13		T2	8		T7	1
fifo_depth[2]	auto[1]	auto[0]	auto[1]	16522	1			T1	9		T2	12		T7	1
fifo_depth[2]	auto[1]	auto[1]	auto[0]	14449	1			T1	3		T2	46		T5	236
fifo_depth[2]	auto[1]	auto[1]	auto[1]	14502	1			T2	47		T5	499		T10	2
fifo_depth[3]	auto[0]	auto[0]	auto[0]	5029	1			T2	5		T5	34		T11	29
fifo_depth[3]	auto[0]	auto[0]	auto[1]	4928	1			T2	14		T5	46		T11	30
fifo_depth[3]	auto[0]	auto[1]	auto[0]	84324	1			T5	33		T11	116		T13	102
fifo_depth[3]	auto[0]	auto[1]	auto[1]	5371	1			T1	7		T2	6		T5	40
fifo_depth[3]	auto[1]	auto[0]	auto[0]	12443	1			T1	3		T2	2		T7	1
fifo_depth[3]	auto[1]	auto[0]	auto[1]	13923	1			T1	6		T2	4		T5	134
fifo_depth[3]	auto[1]	auto[1]	auto[0]	12100	1			T2	16		T5	109		T10	3
fifo_depth[3]	auto[1]	auto[1]	auto[1]	11910	1			T2	17		T5	216		T10	2
fifo_depth[4]	auto[0]	auto[0]	auto[0]	5162	1			T2	2		T5	12		T11	10
fifo_depth[4]	auto[0]	auto[0]	auto[1]	4621	1			T2	6		T5	15		T11	33
fifo_depth[4]	auto[0]	auto[1]	auto[0]	57975	1			T5	19		T11	42		T13	32
fifo_depth[4]	auto[0]	auto[1]	auto[1]	5686	1			T1	1		T2	1		T5	17
fifo_depth[4]	auto[1]	auto[0]	auto[0]	11864	1			T1	1		T5	117		T11	11
fifo_depth[4]	auto[1]	auto[0]	auto[1]	13187	1			T1	1		T2	1		T5	44
fifo_depth[4]	auto[1]	auto[1]	auto[0]	11000	1			T1	1		T2	2		T5	37
fifo_depth[4]	auto[1]	auto[1]	auto[1]	10998	1			T2	7		T5	80		T10	2
fifo_depth[5]	auto[0]	auto[0]	auto[0]	4102	1			T2	1		T5	1		T89	22
fifo_depth[5]	auto[0]	auto[0]	auto[1]	3618	1			T2	2		T11	5		T64	2
fifo_depth[5]	auto[0]	auto[1]	auto[0]	44489	1			T5	3		T11	8		T13	6
fifo_depth[5]	auto[0]	auto[1]	auto[1]	4124	1			T5	4		T11	1		T64	4
fifo_depth[5]	auto[1]	auto[0]	auto[0]	10442	1			T5	30		T11	4		T25	135
fifo_depth[5]	auto[1]	auto[0]	auto[1]	11794	1			T5	18		T11	4		T25	101
fifo_depth[5]	auto[1]	auto[1]	auto[0]	9769	1			T2	2		T5	13		T10	2
fifo_depth[5]	auto[1]	auto[1]	auto[1]	9426	1			T5	24		T10	2		T11	6
fifo_depth[6]	auto[0]	auto[0]	auto[0]	4238	1			T64	1		T89	11		T96	8
fifo_depth[6]	auto[0]	auto[0]	auto[1]	3893	1			T11	4		T64	2		T12	2
fifo_depth[6]	auto[0]	auto[1]	auto[0]	38056	1			T5	2		T11	2		T13	1
fifo_depth[6]	auto[0]	auto[1]	auto[1]	4384	1			T5	1		T64	5		T12	3
fifo_depth[6]	auto[1]	auto[0]	auto[0]	10333	1			T2	1		T5	7		T11	1
fifo_depth[6]	auto[1]	auto[0]	auto[1]	11805	1			T5	2		T25	95		T64	1
fifo_depth[6]	auto[1]	auto[1]	auto[0]	9487	1			T5	7		T10	1		T64	2
fifo_depth[6]	auto[1]	auto[1]	auto[1]	9351	1			T5	8		T10	1		T11	3
fifo_depth[7]	auto[0]	auto[0]	auto[0]	3982	1			T5	1		T89	12		T96	4
fifo_depth[7]	auto[0]	auto[0]	auto[1]	3397	1			T11	3		T64	1		T116	12
fifo_depth[7]	auto[0]	auto[1]	auto[0]	29644	1			T5	3		T11	1		T12	2
fifo_depth[7]	auto[0]	auto[1]	auto[1]	3436	1			T64	2		T12	1		T96	1
fifo_depth[7]	auto[1]	auto[0]	auto[0]	9919	1			T5	2		T25	133		T89	14
fifo_depth[7]	auto[1]	auto[0]	auto[1]	10936	1			T5	1		T25	81		T64	1
fifo_depth[7]	auto[1]	auto[1]	auto[0]	8945	1			T64	2		T65	90		T66	1
fifo_depth[7]	auto[1]	auto[1]	auto[1]	8789	1			T5	1		T6	94		T25	426