Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	12409404	1			T1	2867		T2	14174		T4	451
all_pins[1]	12409404	1			T1	2867		T2	14174		T4	451
all_pins[2]	12409404	1			T1	2867		T2	14174		T4	451

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	30947702	1			T1	7653		T2	39386		T4	1296
values[0x1]	6280510	1			T1	948		T2	3136		T4	57
transitions[0x0=>0x1]	6280342	1			T1	948		T2	3136		T4	57
transitions[0x1=>0x0]	6280358	1			T1	948		T2	3136		T4	57

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	12376624	1			T1	2857		T2	14130		T4	418
all_pins[0]	values[0x1]	32780	1			T1	10		T2	44		T4	33
all_pins[0]	transitions[0x0=>0x1]	32687	1			T1	10		T2	44		T4	33
all_pins[0]	transitions[0x1=>0x0]	6247361	1			T1	938		T2	3092		T4	24
all_pins[1]	values[0x0]	12409112	1			T1	2867		T2	14174		T4	451
all_pins[1]	values[0x1]	292	1			T5	4		T11	6		T20	3
all_pins[1]	transitions[0x0=>0x1]	254	1			T5	2		T11	5		T20	3
all_pins[1]	transitions[0x1=>0x0]	32742	1			T1	10		T2	44		T4	33
all_pins[2]	values[0x0]	6161966	1			T1	1929		T2	11082		T4	427
all_pins[2]	values[0x1]	6247438	1			T1	938		T2	3092		T4	24
all_pins[2]	transitions[0x0=>0x1]	6247401	1			T1	938		T2	3092		T4	24
all_pins[2]	transitions[0x1=>0x0]	255	1			T5	4		T11	4		T91	1