Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 771 1 T5 10 T11 28 T20 14
all_values[1] 771 1 T5 10 T11 28 T20 14
all_values[2] 771 1 T5 10 T11 28 T20 14


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1119 1 T5 19 T11 36 T20 17
auto[1] 1194 1 T5 11 T11 48 T20 25


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 843 1 T5 8 T11 38 T20 14
auto[1] 1470 1 T5 22 T11 46 T20 28


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1322 1 T5 15 T11 52 T20 24
auto[1] 991 1 T5 15 T11 32 T20 18


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 148 1 T11 3 T20 5 T106 4
all_values[0] auto[0] auto[0] auto[1] 72 1 T5 4 T11 1 T20 1
all_values[0] auto[0] auto[1] auto[0] 142 1 T5 1 T11 9 T20 2
all_values[0] auto[0] auto[1] auto[1] 79 1 T11 2 T20 1 T31 2
all_values[0] auto[1] auto[0] auto[1] 158 1 T5 2 T11 3 T20 1
all_values[0] auto[1] auto[1] auto[1] 172 1 T5 3 T11 10 T20 4
all_values[1] auto[0] auto[0] auto[0] 123 1 T11 7 T20 2 T106 5
all_values[1] auto[0] auto[0] auto[1] 92 1 T5 2 T11 2 T20 2
all_values[1] auto[0] auto[1] auto[0] 138 1 T5 1 T11 7 T20 3
all_values[1] auto[0] auto[1] auto[1] 93 1 T11 4 T20 1 T106 5
all_values[1] auto[1] auto[0] auto[1] 161 1 T5 5 T11 4 T20 3
all_values[1] auto[1] auto[1] auto[1] 164 1 T5 2 T11 4 T20 3
all_values[2] auto[0] auto[0] auto[0] 151 1 T5 6 T11 6 T20 1
all_values[2] auto[0] auto[0] auto[1] 63 1 T11 4 T20 1 T106 2
all_values[2] auto[0] auto[1] auto[0] 141 1 T11 6 T20 1 T106 7
all_values[2] auto[0] auto[1] auto[1] 80 1 T5 1 T11 1 T20 4
all_values[2] auto[1] auto[0] auto[1] 151 1 T11 6 T20 1 T106 7
all_values[2] auto[1] auto[1] auto[1] 185 1 T5 3 T11 5 T20 6


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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