Group : hmac_env_pkg::hmac_env_cov::cfg_cg
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Group : hmac_env_pkg::hmac_env_cov::cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
60.78 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv



Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 20 4 16 80.00
Crosses 82 36 46 56.10


Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
digest_size 5 2 3 60.00 100 1 1 0
digest_swap 2 0 2 100.00 100 1 1 2
endian_swap 2 0 2 100.00 100 1 1 2
hmac_en 2 0 2 100.00 100 1 1 0
key_length 7 1 6 85.71 100 1 1 0
sha_en 2 1 1 50.00 100 1 1 0


Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cfg_cross 8 0 8 100.00 100 1 1 0
hmac_dis_x_sha_en 4 2 2 50.00 100 1 1 0
key_x_digest_mismatch 35 17 18 51.43 100 1 1 0
key_length_x_digest_size 35 17 18 51.43 100 1 1 0


Summary for Variable digest_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 2 3 60.00


User Defined Bins for digest_size

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
sha2_invalid 0 1 1
sha2_none 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
sha2_512 3943 1 T1 3 T2 13 T4 8
sha2_384 3948 1 T1 4 T2 12 T4 11
sha2_256 22062 1 T1 2 T2 8 T4 7



Summary for Variable digest_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for digest_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 24274 1 T1 5 T2 9 T4 8
auto[1] 5679 1 T1 4 T2 24 T4 18



Summary for Variable endian_swap

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for endian_swap

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 5671 1 T1 6 T2 17 T4 15
auto[1] 24282 1 T1 3 T2 16 T4 11



Summary for Variable hmac_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for hmac_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
enabled 6318 1 T1 5 T2 15 T4 11
disabled 23635 1 T1 4 T2 18 T4 15



Summary for Variable key_length

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 7 1 6 85.71


User Defined Bins for key_length

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
key_invalid 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
key_none 919 1 T1 1 T2 3 T5 16
key_1024 1780 1 T1 1 T2 7 T4 4
key_512 2127 1 T2 2 T4 3 T5 51
key_384 2184 1 T1 4 T2 6 T4 6
key_256 20795 1 T1 1 T2 9 T4 7
key_128 2148 1 T1 2 T2 6 T4 6



Summary for Variable sha_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 1 1 50.00


User Defined Bins for sha_en

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
disabled 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
enabled 29953 1 T1 9 T2 33 T4 26



Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for cfg_cross

Bins
hmac_enendian_swapdigest_swapCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
enabled auto[0] auto[0] 1492 1 T1 2 T2 2 T4 3
enabled auto[0] auto[1] 1467 1 T1 2 T2 2 T4 4
enabled auto[1] auto[0] 1865 1 T1 1 T2 3 T5 47
enabled auto[1] auto[1] 1494 1 T2 8 T4 4 T5 40
disabled auto[0] auto[0] 1379 1 T1 2 T2 4 T4 4
disabled auto[0] auto[1] 1333 1 T2 9 T4 4 T7 2
disabled auto[1] auto[0] 19538 1 T4 1 T7 2 T5 22
disabled auto[1] auto[1] 1385 1 T1 2 T2 5 T4 6



Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 4 2 2 50.00 2
Automatically Generated Cross Bins 3 2 1 33.33 2
User Defined Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for hmac_dis_x_sha_en

Element holes
hmac_ensha_enCOUNTAT LEASTNUMBERSTATUS
* [disabled] -- -- 2


Covered bins
hmac_ensha_enCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
enabled enabled 6318 1 T1 5 T2 15 T4 11


User Defined Cross Bins for hmac_dis_x_sha_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
b0 23635 1 T1 4 T2 18 T4 15



Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 35 17 18 51.43 17
Automatically Generated Cross Bins 34 17 17 50.00 17
User Defined Cross Bins 1 0 1 100.00


Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes
key_lengthdigest_sizeCOUNTAT LEASTNUMBERSTATUS
[key_invalid] * -- -- 5


Uncovered bins
key_lengthdigest_sizeCOUNTAT LEASTNUMBERSTATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128] [sha2_invalid , sha2_none] -- -- 12


Covered bins
key_lengthdigest_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
key_none sha2_512 338 1 T2 1 T5 5 T10 1
key_none sha2_384 279 1 T5 6 T10 1 T11 2
key_none sha2_256 302 1 T1 1 T2 2 T5 5
key_1024 sha2_512 761 1 T2 4 T4 2 T5 16
key_1024 sha2_384 721 1 T1 1 T2 3 T4 1
key_512 sha2_512 709 1 T2 1 T4 1 T5 16
key_512 sha2_384 714 1 T4 2 T5 17 T10 2
key_512 sha2_256 704 1 T2 1 T5 18 T10 1
key_384 sha2_512 713 1 T1 1 T2 1 T4 2
key_384 sha2_384 749 1 T1 2 T2 5 T4 2
key_384 sha2_256 722 1 T1 1 T4 2 T7 1
key_256 sha2_512 707 1 T1 1 T2 3 T4 2
key_256 sha2_384 763 1 T2 3 T4 2 T7 1
key_256 sha2_256 19325 1 T2 3 T4 3 T7 1
key_128 sha2_512 715 1 T1 1 T2 3 T4 1
key_128 sha2_384 722 1 T1 1 T2 1 T4 4
key_128 sha2_256 711 1 T2 2 T4 1 T5 13


User Defined Cross Bins for key_x_digest_mismatch

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
b0 298 1 T4 1 T7 2 T5 5



Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 35 17 18 51.43 17


Automatically Generated Cross Bins for key_length_x_digest_size

Element holes
key_lengthdigest_sizeCOUNTAT LEASTNUMBERSTATUS
[key_invalid] * -- -- 5


Uncovered bins
key_lengthdigest_sizeCOUNTAT LEASTNUMBERSTATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128] [sha2_invalid , sha2_none] -- -- 12


Covered bins
key_lengthdigest_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
key_none sha2_512 338 1 T2 1 T5 5 T10 1
key_none sha2_384 279 1 T5 6 T10 1 T11 2
key_none sha2_256 302 1 T1 1 T2 2 T5 5
key_1024 sha2_512 761 1 T2 4 T4 2 T5 16
key_1024 sha2_384 721 1 T1 1 T2 3 T4 1
key_1024 sha2_256 298 1 T4 1 T7 2 T5 5
key_512 sha2_512 709 1 T2 1 T4 1 T5 16
key_512 sha2_384 714 1 T4 2 T5 17 T10 2
key_512 sha2_256 704 1 T2 1 T5 18 T10 1
key_384 sha2_512 713 1 T1 1 T2 1 T4 2
key_384 sha2_384 749 1 T1 2 T2 5 T4 2
key_384 sha2_256 722 1 T1 1 T4 2 T7 1
key_256 sha2_512 707 1 T1 1 T2 3 T4 2
key_256 sha2_384 763 1 T2 3 T4 2 T7 1
key_256 sha2_256 19325 1 T2 3 T4 3 T7 1
key_128 sha2_512 715 1 T1 1 T2 3 T4 1
key_128 sha2_384 722 1 T1 1 T2 1 T4 4
key_128 sha2_256 711 1 T2 2 T4 1 T5 13

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