Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
88.50 94.84 92.25 100.00 71.79 89.38 99.49 71.75


Total test records in report: 723
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T537 /workspace/coverage/default/30.hmac_long_msg.3982144724 Jun 11 02:16:08 PM PDT 24 Jun 11 02:16:43 PM PDT 24 6580001242 ps
T538 /workspace/coverage/default/2.hmac_error.3230126942 Jun 11 02:15:22 PM PDT 24 Jun 11 02:17:33 PM PDT 24 18516400287 ps
T539 /workspace/coverage/default/26.hmac_wipe_secret.1883804772 Jun 11 02:16:12 PM PDT 24 Jun 11 02:16:21 PM PDT 24 163838176 ps
T540 /workspace/coverage/default/49.hmac_datapath_stress.2345808679 Jun 11 02:17:18 PM PDT 24 Jun 11 02:40:28 PM PDT 24 4660673214 ps
T541 /workspace/coverage/default/48.hmac_alert_test.1902363737 Jun 11 02:17:19 PM PDT 24 Jun 11 02:17:20 PM PDT 24 65174394 ps
T542 /workspace/coverage/default/4.hmac_back_pressure.2342918068 Jun 11 02:15:36 PM PDT 24 Jun 11 02:16:06 PM PDT 24 1368050820 ps
T543 /workspace/coverage/default/33.hmac_long_msg.2731311544 Jun 11 02:16:18 PM PDT 24 Jun 11 02:17:49 PM PDT 24 78466702122 ps
T544 /workspace/coverage/default/24.hmac_alert_test.4138391132 Jun 11 02:15:56 PM PDT 24 Jun 11 02:15:59 PM PDT 24 12195418 ps
T545 /workspace/coverage/default/45.hmac_long_msg.4057825255 Jun 11 02:17:02 PM PDT 24 Jun 11 02:18:10 PM PDT 24 4580682368 ps
T546 /workspace/coverage/default/35.hmac_error.3121265872 Jun 11 02:16:38 PM PDT 24 Jun 11 02:16:54 PM PDT 24 577966793 ps
T547 /workspace/coverage/default/41.hmac_alert_test.1201433496 Jun 11 02:16:48 PM PDT 24 Jun 11 02:16:49 PM PDT 24 48473214 ps
T548 /workspace/coverage/default/25.hmac_datapath_stress.3893294695 Jun 11 02:16:14 PM PDT 24 Jun 11 02:19:21 PM PDT 24 988024731 ps
T549 /workspace/coverage/default/2.hmac_test_sha_vectors.1181446434 Jun 11 02:15:26 PM PDT 24 Jun 11 02:22:12 PM PDT 24 30337232129 ps
T550 /workspace/coverage/default/38.hmac_error.698482291 Jun 11 02:16:38 PM PDT 24 Jun 11 02:17:26 PM PDT 24 3408613487 ps
T551 /workspace/coverage/default/28.hmac_burst_wr.87118712 Jun 11 02:16:10 PM PDT 24 Jun 11 02:17:09 PM PDT 24 3740302879 ps
T552 /workspace/coverage/default/42.hmac_test_hmac_vectors.1702653942 Jun 11 02:16:51 PM PDT 24 Jun 11 02:16:53 PM PDT 24 106305207 ps
T553 /workspace/coverage/default/15.hmac_long_msg.811670302 Jun 11 02:15:59 PM PDT 24 Jun 11 02:17:30 PM PDT 24 19668812755 ps
T554 /workspace/coverage/default/30.hmac_smoke.2784205325 Jun 11 02:16:14 PM PDT 24 Jun 11 02:16:21 PM PDT 24 330345452 ps
T555 /workspace/coverage/default/42.hmac_burst_wr.25543929 Jun 11 02:16:49 PM PDT 24 Jun 11 02:17:46 PM PDT 24 7239163261 ps
T556 /workspace/coverage/default/34.hmac_long_msg.3855589294 Jun 11 02:16:21 PM PDT 24 Jun 11 02:16:41 PM PDT 24 1134949609 ps
T557 /workspace/coverage/default/3.hmac_wipe_secret.445802044 Jun 11 02:15:35 PM PDT 24 Jun 11 02:16:43 PM PDT 24 3503565151 ps
T558 /workspace/coverage/default/19.hmac_error.3557275704 Jun 11 02:15:59 PM PDT 24 Jun 11 02:19:27 PM PDT 24 133318309459 ps
T559 /workspace/coverage/default/32.hmac_test_sha_vectors.2035531875 Jun 11 02:16:19 PM PDT 24 Jun 11 02:24:12 PM PDT 24 53593850659 ps
T560 /workspace/coverage/default/32.hmac_datapath_stress.604454265 Jun 11 02:16:14 PM PDT 24 Jun 11 02:18:21 PM PDT 24 866921979 ps
T561 /workspace/coverage/default/23.hmac_smoke.2316876591 Jun 11 02:16:05 PM PDT 24 Jun 11 02:16:07 PM PDT 24 594009608 ps
T562 /workspace/coverage/default/16.hmac_burst_wr.4094190098 Jun 11 02:15:54 PM PDT 24 Jun 11 02:16:16 PM PDT 24 781934379 ps
T563 /workspace/coverage/default/21.hmac_test_hmac_vectors.653592354 Jun 11 02:15:59 PM PDT 24 Jun 11 02:16:03 PM PDT 24 91256448 ps
T564 /workspace/coverage/default/35.hmac_burst_wr.1707313969 Jun 11 02:16:35 PM PDT 24 Jun 11 02:16:55 PM PDT 24 1417104568 ps
T565 /workspace/coverage/default/48.hmac_error.1270694845 Jun 11 02:17:11 PM PDT 24 Jun 11 02:17:56 PM PDT 24 16895172912 ps
T566 /workspace/coverage/default/40.hmac_test_hmac_vectors.636948854 Jun 11 02:16:48 PM PDT 24 Jun 11 02:16:50 PM PDT 24 159776638 ps
T567 /workspace/coverage/default/24.hmac_back_pressure.3165066433 Jun 11 02:15:56 PM PDT 24 Jun 11 02:16:24 PM PDT 24 3047805550 ps
T62 /workspace/coverage/default/47.hmac_stress_all.1067016298 Jun 11 02:17:09 PM PDT 24 Jun 11 02:24:04 PM PDT 24 19573396465 ps
T568 /workspace/coverage/default/13.hmac_datapath_stress.613714699 Jun 11 02:15:45 PM PDT 24 Jun 11 02:32:48 PM PDT 24 3545524330 ps
T569 /workspace/coverage/default/22.hmac_datapath_stress.2827398055 Jun 11 02:15:55 PM PDT 24 Jun 11 02:28:18 PM PDT 24 3007853935 ps
T570 /workspace/coverage/default/36.hmac_back_pressure.2990694547 Jun 11 02:16:31 PM PDT 24 Jun 11 02:17:08 PM PDT 24 2950034648 ps
T571 /workspace/coverage/default/26.hmac_datapath_stress.4195038521 Jun 11 02:16:11 PM PDT 24 Jun 11 02:33:06 PM PDT 24 7427911304 ps
T572 /workspace/coverage/default/37.hmac_alert_test.2147875127 Jun 11 02:16:39 PM PDT 24 Jun 11 02:16:41 PM PDT 24 44540591 ps
T573 /workspace/coverage/default/9.hmac_error.3988332809 Jun 11 02:15:46 PM PDT 24 Jun 11 02:17:58 PM PDT 24 34881574480 ps
T574 /workspace/coverage/default/26.hmac_smoke.2978960525 Jun 11 02:16:17 PM PDT 24 Jun 11 02:16:25 PM PDT 24 1105425633 ps
T575 /workspace/coverage/default/49.hmac_wipe_secret.2987613428 Jun 11 02:17:19 PM PDT 24 Jun 11 02:18:05 PM PDT 24 2507182480 ps
T576 /workspace/coverage/default/26.hmac_test_hmac_vectors.1005247668 Jun 11 02:16:07 PM PDT 24 Jun 11 02:16:09 PM PDT 24 32446918 ps
T577 /workspace/coverage/default/18.hmac_datapath_stress.2207602714 Jun 11 02:15:58 PM PDT 24 Jun 11 02:24:52 PM PDT 24 4137460962 ps
T578 /workspace/coverage/default/46.hmac_test_sha_vectors.1732946320 Jun 11 02:17:11 PM PDT 24 Jun 11 02:25:07 PM PDT 24 130822452390 ps
T579 /workspace/coverage/default/31.hmac_smoke.486142090 Jun 11 02:16:20 PM PDT 24 Jun 11 02:16:30 PM PDT 24 2496220599 ps
T580 /workspace/coverage/default/5.hmac_wipe_secret.209739448 Jun 11 02:15:31 PM PDT 24 Jun 11 02:15:52 PM PDT 24 2257311130 ps
T101 /workspace/coverage/default/29.hmac_datapath_stress.3588337115 Jun 11 02:16:08 PM PDT 24 Jun 11 02:26:57 PM PDT 24 2643536851 ps
T581 /workspace/coverage/default/23.hmac_long_msg.4030692249 Jun 11 02:15:59 PM PDT 24 Jun 11 02:16:12 PM PDT 24 205770179 ps
T582 /workspace/coverage/default/15.hmac_stress_all.3676310094 Jun 11 02:15:55 PM PDT 24 Jun 11 02:18:49 PM PDT 24 12369633826 ps
T583 /workspace/coverage/default/40.hmac_long_msg.619801067 Jun 11 02:16:48 PM PDT 24 Jun 11 02:17:26 PM PDT 24 1452444683 ps
T584 /workspace/coverage/default/28.hmac_error.1653292356 Jun 11 02:16:10 PM PDT 24 Jun 11 02:16:45 PM PDT 24 3696824768 ps
T585 /workspace/coverage/default/24.hmac_datapath_stress.798974616 Jun 11 02:16:00 PM PDT 24 Jun 11 02:19:48 PM PDT 24 5337739837 ps
T586 /workspace/coverage/default/45.hmac_stress_all.664826854 Jun 11 02:17:02 PM PDT 24 Jun 11 02:50:15 PM PDT 24 244465199458 ps
T587 /workspace/coverage/default/22.hmac_wipe_secret.771572364 Jun 11 02:16:02 PM PDT 24 Jun 11 02:17:30 PM PDT 24 1940673022 ps
T588 /workspace/coverage/default/28.hmac_long_msg.3906914780 Jun 11 02:16:05 PM PDT 24 Jun 11 02:17:08 PM PDT 24 966157347 ps
T589 /workspace/coverage/default/29.hmac_smoke.2609642678 Jun 11 02:16:16 PM PDT 24 Jun 11 02:16:29 PM PDT 24 1932836470 ps
T590 /workspace/coverage/default/11.hmac_datapath_stress.3288147575 Jun 11 02:15:46 PM PDT 24 Jun 11 02:26:24 PM PDT 24 2836881598 ps
T591 /workspace/coverage/default/24.hmac_test_hmac_vectors.668452854 Jun 11 02:16:01 PM PDT 24 Jun 11 02:16:05 PM PDT 24 79354065 ps
T592 /workspace/coverage/default/5.hmac_test_hmac_vectors.2972889570 Jun 11 02:15:36 PM PDT 24 Jun 11 02:15:39 PM PDT 24 31961078 ps
T39 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.393116163 Jun 11 01:48:29 PM PDT 24 Jun 11 01:48:31 PM PDT 24 31035918 ps
T40 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3075008758 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:25 PM PDT 24 517216103 ps
T41 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1545624886 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:27 PM PDT 24 68251641 ps
T42 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3362667841 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:32 PM PDT 24 6526954616 ps
T593 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2181186442 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:27 PM PDT 24 699683941 ps
T43 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2458990887 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:30 PM PDT 24 129659075 ps
T34 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1243727091 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:21 PM PDT 24 292949211 ps
T594 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1931132947 Jun 11 01:48:27 PM PDT 24 Jun 11 01:48:31 PM PDT 24 47243531 ps
T44 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1562224706 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:31 PM PDT 24 290987719 ps
T35 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3954885524 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:17 PM PDT 24 368348403 ps
T45 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2140291039 Jun 11 01:48:27 PM PDT 24 Jun 11 01:48:31 PM PDT 24 193278672 ps
T46 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2325748991 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:28 PM PDT 24 49830256 ps
T36 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2635420195 Jun 11 01:48:33 PM PDT 24 Jun 11 01:48:37 PM PDT 24 636065114 ps
T63 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3524592408 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:27 PM PDT 24 235531009 ps
T84 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3021362594 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:38 PM PDT 24 211491036 ps
T595 /workspace/coverage/cover_reg_top/29.hmac_intr_test.1517420832 Jun 11 01:48:54 PM PDT 24 Jun 11 01:48:57 PM PDT 24 18494237 ps
T76 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.416842279 Jun 11 01:48:15 PM PDT 24 Jun 11 01:48:26 PM PDT 24 153977263 ps
T77 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2656995215 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:26 PM PDT 24 21234952 ps
T596 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2531588667 Jun 11 01:48:15 PM PDT 24 Jun 11 01:48:19 PM PDT 24 53077569 ps
T597 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2419321989 Jun 11 01:48:40 PM PDT 24 Jun 11 01:48:42 PM PDT 24 15975232 ps
T598 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2910707839 Jun 11 01:48:27 PM PDT 24 Jun 11 01:48:31 PM PDT 24 330092192 ps
T78 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1850787911 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:20 PM PDT 24 308693727 ps
T599 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2662514216 Jun 11 01:48:13 PM PDT 24 Jun 11 01:48:18 PM PDT 24 321341810 ps
T600 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.646284978 Jun 11 01:48:14 PM PDT 24 Jun 11 01:48:19 PM PDT 24 76660085 ps
T601 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3454664341 Jun 11 01:48:30 PM PDT 24 Jun 11 01:48:33 PM PDT 24 81737710 ps
T602 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.694726660 Jun 11 01:48:22 PM PDT 24 Jun 11 01:48:25 PM PDT 24 245122477 ps
T603 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2224818910 Jun 11 01:48:42 PM PDT 24 Jun 11 01:48:44 PM PDT 24 15428842 ps
T604 /workspace/coverage/cover_reg_top/3.hmac_intr_test.1076264365 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:15 PM PDT 24 49608820 ps
T605 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1301086697 Jun 11 01:48:14 PM PDT 24 Jun 11 01:48:18 PM PDT 24 129411907 ps
T606 /workspace/coverage/cover_reg_top/49.hmac_intr_test.2294314013 Jun 11 01:48:49 PM PDT 24 Jun 11 01:48:50 PM PDT 24 13462075 ps
T607 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2254142047 Jun 11 01:48:28 PM PDT 24 Jun 11 01:48:31 PM PDT 24 223143670 ps
T608 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2327038298 Jun 11 01:48:31 PM PDT 24 Jun 11 01:48:32 PM PDT 24 49060457 ps
T609 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3864076244 Jun 11 01:48:15 PM PDT 24 Jun 11 01:48:20 PM PDT 24 417001106 ps
T610 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1224793287 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:30 PM PDT 24 34398530 ps
T611 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3738716695 Jun 11 01:48:41 PM PDT 24 Jun 11 01:48:43 PM PDT 24 16583062 ps
T612 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3221618951 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:29 PM PDT 24 30728266 ps
T79 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4060576653 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:25 PM PDT 24 16387406 ps
T613 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1031920463 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:25 PM PDT 24 22677384 ps
T107 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1992408278 Jun 11 01:48:15 PM PDT 24 Jun 11 01:48:19 PM PDT 24 58194097 ps
T614 /workspace/coverage/cover_reg_top/46.hmac_intr_test.1976312843 Jun 11 01:48:52 PM PDT 24 Jun 11 01:48:53 PM PDT 24 16515216 ps
T615 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2096671215 Jun 11 01:48:31 PM PDT 24 Jun 11 01:48:34 PM PDT 24 36459589 ps
T616 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2808654095 Jun 11 01:48:39 PM PDT 24 Jun 11 01:48:40 PM PDT 24 16687770 ps
T617 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.662467762 Jun 11 01:48:30 PM PDT 24 Jun 11 01:48:33 PM PDT 24 98129080 ps
T618 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4123906835 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:28 PM PDT 24 45168289 ps
T108 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.474195260 Jun 11 01:48:10 PM PDT 24 Jun 11 01:48:16 PM PDT 24 609266826 ps
T619 /workspace/coverage/cover_reg_top/16.hmac_intr_test.1984986069 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:26 PM PDT 24 14695609 ps
T620 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3788133024 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:28 PM PDT 24 342839524 ps
T621 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2558007478 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:32 PM PDT 24 146279566 ps
T113 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1348502797 Jun 11 01:48:15 PM PDT 24 Jun 11 01:48:23 PM PDT 24 452988731 ps
T622 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.313742133 Jun 11 01:48:15 PM PDT 24 Jun 11 01:50:55 PM PDT 24 57879410221 ps
T80 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4063561503 Jun 11 01:48:10 PM PDT 24 Jun 11 01:48:14 PM PDT 24 30081755 ps
T623 /workspace/coverage/cover_reg_top/1.hmac_intr_test.469818981 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:17 PM PDT 24 72949081 ps
T624 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1614276357 Jun 11 01:48:44 PM PDT 24 Jun 11 01:48:46 PM PDT 24 14652973 ps
T625 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3440963714 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:31 PM PDT 24 249215190 ps
T626 /workspace/coverage/cover_reg_top/27.hmac_intr_test.1940892240 Jun 11 01:48:45 PM PDT 24 Jun 11 01:48:47 PM PDT 24 18058752 ps
T627 /workspace/coverage/cover_reg_top/25.hmac_intr_test.993677906 Jun 11 01:48:50 PM PDT 24 Jun 11 01:48:52 PM PDT 24 13030999 ps
T628 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2176333184 Jun 11 01:48:42 PM PDT 24 Jun 11 01:48:44 PM PDT 24 144904609 ps
T629 /workspace/coverage/cover_reg_top/30.hmac_intr_test.3212581625 Jun 11 01:48:41 PM PDT 24 Jun 11 01:48:43 PM PDT 24 16941088 ps
T630 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.272018241 Jun 11 01:48:13 PM PDT 24 Jun 11 01:48:20 PM PDT 24 237917081 ps
T631 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3652821379 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:25 PM PDT 24 15834919 ps
T632 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3319167254 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:19 PM PDT 24 234308595 ps
T633 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4032875415 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:28 PM PDT 24 14300220 ps
T109 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2576614597 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:32 PM PDT 24 879413433 ps
T634 /workspace/coverage/cover_reg_top/22.hmac_intr_test.1357449400 Jun 11 01:48:40 PM PDT 24 Jun 11 01:48:42 PM PDT 24 39261874 ps
T635 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4210294672 Jun 11 01:48:30 PM PDT 24 Jun 11 01:48:33 PM PDT 24 421747576 ps
T81 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1662338661 Jun 11 01:48:14 PM PDT 24 Jun 11 01:48:23 PM PDT 24 1095439389 ps
T636 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2935419483 Jun 11 01:48:38 PM PDT 24 Jun 11 01:48:42 PM PDT 24 61587551 ps
T637 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.151328963 Jun 11 01:48:22 PM PDT 24 Jun 11 01:48:25 PM PDT 24 61755851 ps
T638 /workspace/coverage/cover_reg_top/17.hmac_intr_test.2431178953 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:26 PM PDT 24 22920716 ps
T111 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3939489580 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:30 PM PDT 24 136502359 ps
T639 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3293009483 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:27 PM PDT 24 64036110 ps
T640 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1826054362 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:17 PM PDT 24 57022665 ps
T641 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2919162064 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:27 PM PDT 24 87491386 ps
T642 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2270611154 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:27 PM PDT 24 61886238 ps
T643 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1078590312 Jun 11 01:48:42 PM PDT 24 Jun 11 01:48:46 PM PDT 24 776400746 ps
T644 /workspace/coverage/cover_reg_top/21.hmac_intr_test.148570433 Jun 11 01:48:42 PM PDT 24 Jun 11 01:48:45 PM PDT 24 40410379 ps
T112 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3986323525 Jun 11 01:48:41 PM PDT 24 Jun 11 01:48:47 PM PDT 24 1202562979 ps
T645 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.720481499 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:17 PM PDT 24 65881746 ps
T646 /workspace/coverage/cover_reg_top/33.hmac_intr_test.1276564527 Jun 11 01:48:44 PM PDT 24 Jun 11 01:48:46 PM PDT 24 62624287 ps
T647 /workspace/coverage/cover_reg_top/28.hmac_intr_test.3146440045 Jun 11 01:48:39 PM PDT 24 Jun 11 01:48:41 PM PDT 24 96082985 ps
T648 /workspace/coverage/cover_reg_top/7.hmac_intr_test.992227481 Jun 11 01:48:27 PM PDT 24 Jun 11 01:48:30 PM PDT 24 28375662 ps
T649 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1404653539 Jun 11 01:48:43 PM PDT 24 Jun 11 01:48:46 PM PDT 24 127169324 ps
T82 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1650940031 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:29 PM PDT 24 16575130 ps
T650 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1903777079 Jun 11 01:48:15 PM PDT 24 Jun 11 01:48:18 PM PDT 24 23289465 ps
T651 /workspace/coverage/cover_reg_top/42.hmac_intr_test.3374508333 Jun 11 01:48:40 PM PDT 24 Jun 11 01:48:43 PM PDT 24 43727766 ps
T114 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1429790014 Jun 11 01:48:21 PM PDT 24 Jun 11 01:48:25 PM PDT 24 154620955 ps
T652 /workspace/coverage/cover_reg_top/0.hmac_intr_test.2476042294 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:17 PM PDT 24 16690075 ps
T653 /workspace/coverage/cover_reg_top/44.hmac_intr_test.397610219 Jun 11 01:48:39 PM PDT 24 Jun 11 01:48:41 PM PDT 24 31117645 ps
T654 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.346685266 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:26 PM PDT 24 247844293 ps
T655 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2215485394 Jun 11 01:48:22 PM PDT 24 Jun 11 01:48:24 PM PDT 24 28454082 ps
T656 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1761505700 Jun 11 01:48:27 PM PDT 24 Jun 11 01:48:31 PM PDT 24 93995260 ps
T657 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3986824506 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:29 PM PDT 24 287063837 ps
T658 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3082060418 Jun 11 01:48:27 PM PDT 24 Jun 11 01:48:31 PM PDT 24 385671784 ps
T83 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3169790717 Jun 11 01:48:10 PM PDT 24 Jun 11 01:48:32 PM PDT 24 1766561306 ps
T659 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3134046205 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:26 PM PDT 24 110456782 ps
T660 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3700403709 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:28 PM PDT 24 314679027 ps
T661 /workspace/coverage/cover_reg_top/6.hmac_intr_test.740070619 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:25 PM PDT 24 62003801 ps
T662 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3542660103 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:25 PM PDT 24 40804564 ps
T663 /workspace/coverage/cover_reg_top/40.hmac_intr_test.4136023611 Jun 11 01:48:40 PM PDT 24 Jun 11 01:48:42 PM PDT 24 10397179 ps
T664 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1309558046 Jun 11 01:48:51 PM PDT 24 Jun 11 01:48:53 PM PDT 24 12915974 ps
T665 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1531065031 Jun 11 01:48:28 PM PDT 24 Jun 11 01:48:34 PM PDT 24 461813688 ps
T85 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2183072664 Jun 11 01:48:14 PM PDT 24 Jun 11 01:48:18 PM PDT 24 30606721 ps
T666 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1047896620 Jun 11 01:48:22 PM PDT 24 Jun 11 01:48:27 PM PDT 24 136538491 ps
T86 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.747032852 Jun 11 01:48:15 PM PDT 24 Jun 11 01:48:18 PM PDT 24 29666323 ps
T667 /workspace/coverage/cover_reg_top/41.hmac_intr_test.1962801239 Jun 11 01:48:42 PM PDT 24 Jun 11 01:48:44 PM PDT 24 39859046 ps
T668 /workspace/coverage/cover_reg_top/38.hmac_intr_test.492504991 Jun 11 01:48:42 PM PDT 24 Jun 11 01:48:44 PM PDT 24 25140244 ps
T669 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.419431600 Jun 11 01:48:13 PM PDT 24 Jun 11 01:48:19 PM PDT 24 155459943 ps
T670 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3121329336 Jun 11 01:48:41 PM PDT 24 Jun 11 01:48:43 PM PDT 24 14187324 ps
T671 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1292552415 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:18 PM PDT 24 116039295 ps
T672 /workspace/coverage/cover_reg_top/32.hmac_intr_test.1257333052 Jun 11 01:48:41 PM PDT 24 Jun 11 01:48:43 PM PDT 24 31762544 ps
T673 /workspace/coverage/cover_reg_top/39.hmac_intr_test.514039997 Jun 11 01:48:38 PM PDT 24 Jun 11 01:48:40 PM PDT 24 13306354 ps
T674 /workspace/coverage/cover_reg_top/15.hmac_intr_test.4175868956 Jun 11 01:48:30 PM PDT 24 Jun 11 01:48:31 PM PDT 24 13494382 ps
T675 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1410588505 Jun 11 01:48:09 PM PDT 24 Jun 11 01:48:15 PM PDT 24 185468274 ps
T676 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.935918373 Jun 11 01:48:10 PM PDT 24 Jun 11 01:48:14 PM PDT 24 31174957 ps
T677 /workspace/coverage/cover_reg_top/12.hmac_intr_test.783113122 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:29 PM PDT 24 12238057 ps
T678 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.960355123 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:17 PM PDT 24 24849782 ps
T679 /workspace/coverage/cover_reg_top/23.hmac_intr_test.4079635883 Jun 11 01:48:41 PM PDT 24 Jun 11 01:48:43 PM PDT 24 52067077 ps
T680 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4225914421 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:27 PM PDT 24 197950779 ps
T38 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3865884230 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:31 PM PDT 24 141820142 ps
T681 /workspace/coverage/cover_reg_top/31.hmac_intr_test.336000677 Jun 11 01:48:45 PM PDT 24 Jun 11 01:48:47 PM PDT 24 34190935 ps
T682 /workspace/coverage/cover_reg_top/26.hmac_intr_test.909204716 Jun 11 01:48:39 PM PDT 24 Jun 11 01:48:41 PM PDT 24 19936445 ps
T683 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3585295073 Jun 11 01:48:27 PM PDT 24 Jun 11 01:48:30 PM PDT 24 17424617 ps
T684 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1952910011 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:29 PM PDT 24 84364472 ps
T110 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2690673452 Jun 11 01:48:29 PM PDT 24 Jun 11 01:48:33 PM PDT 24 343963853 ps
T685 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.925186055 Jun 11 01:48:52 PM PDT 24 Jun 11 01:48:54 PM PDT 24 34477959 ps
T686 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2094445101 Jun 11 01:48:12 PM PDT 24 Jun 11 01:48:16 PM PDT 24 126297421 ps
T687 /workspace/coverage/cover_reg_top/19.hmac_intr_test.4044644194 Jun 11 01:48:46 PM PDT 24 Jun 11 01:48:47 PM PDT 24 15585549 ps
T688 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1514011142 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:28 PM PDT 24 88146923 ps
T689 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3158785288 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:31 PM PDT 24 96699868 ps
T690 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2705044265 Jun 11 01:48:22 PM PDT 24 Jun 11 01:48:25 PM PDT 24 155249491 ps
T691 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3785656630 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:27 PM PDT 24 44088723 ps
T692 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.745648585 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:28 PM PDT 24 131952496 ps
T693 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2504196204 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:28 PM PDT 24 175968830 ps
T694 /workspace/coverage/cover_reg_top/36.hmac_intr_test.301006302 Jun 11 01:48:37 PM PDT 24 Jun 11 01:48:39 PM PDT 24 12896808 ps
T695 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1494909433 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:28 PM PDT 24 290159466 ps
T696 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1228489444 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:32 PM PDT 24 197215039 ps
T697 /workspace/coverage/cover_reg_top/24.hmac_intr_test.2505930019 Jun 11 01:48:43 PM PDT 24 Jun 11 01:48:45 PM PDT 24 42662274 ps
T698 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2362516848 Jun 11 01:48:09 PM PDT 24 Jun 11 01:48:13 PM PDT 24 133797241 ps
T699 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1090000666 Jun 11 01:48:28 PM PDT 24 Jun 11 01:48:32 PM PDT 24 80017134 ps
T700 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2894488976 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:27 PM PDT 24 29420962 ps
T701 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.355337105 Jun 11 01:48:14 PM PDT 24 Jun 11 01:48:19 PM PDT 24 36992032 ps
T702 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2444392300 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:16 PM PDT 24 73290044 ps
T703 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.515195647 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:29 PM PDT 24 358200112 ps
T704 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2435555117 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:31 PM PDT 24 74373133 ps
T705 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3749025331 Jun 11 01:48:24 PM PDT 24 Jun 11 01:48:28 PM PDT 24 334547346 ps
T706 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.763798686 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:32 PM PDT 24 158500817 ps
T87 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.148564423 Jun 11 01:48:15 PM PDT 24 Jun 11 01:48:27 PM PDT 24 217348533 ps
T707 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4171506291 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:32 PM PDT 24 223805490 ps
T708 /workspace/coverage/cover_reg_top/4.hmac_intr_test.2529729003 Jun 11 01:48:15 PM PDT 24 Jun 11 01:48:19 PM PDT 24 17969289 ps
T709 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1221458156 Jun 11 01:48:15 PM PDT 24 Jun 11 01:48:23 PM PDT 24 111083315 ps
T710 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3181893000 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:29 PM PDT 24 57477318 ps
T711 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2699059070 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:25 PM PDT 24 29298447 ps
T712 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3639968291 Jun 11 01:48:14 PM PDT 24 Jun 11 01:48:18 PM PDT 24 21751196 ps
T713 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2753731219 Jun 11 01:48:24 PM PDT 24 Jun 11 02:06:50 PM PDT 24 159853647117 ps
T714 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3811380935 Jun 11 01:48:25 PM PDT 24 Jun 11 01:54:59 PM PDT 24 315321592982 ps
T715 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.391703491 Jun 11 01:48:13 PM PDT 24 Jun 11 01:59:26 PM PDT 24 68388654508 ps
T716 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.908403415 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:18 PM PDT 24 204435154 ps
T717 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3556463017 Jun 11 01:48:11 PM PDT 24 Jun 11 01:48:15 PM PDT 24 82304555 ps
T718 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3226936284 Jun 11 01:48:25 PM PDT 24 Jun 11 01:48:28 PM PDT 24 41594194 ps
T719 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1466941742 Jun 11 01:48:30 PM PDT 24 Jun 11 01:48:34 PM PDT 24 273490166 ps
T88 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3316180371 Jun 11 01:48:26 PM PDT 24 Jun 11 01:48:31 PM PDT 24 136769914 ps
T720 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3919563033 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:26 PM PDT 24 538719428 ps
T721 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1945894028 Jun 11 01:48:13 PM PDT 24 Jun 11 01:48:18 PM PDT 24 49565451 ps
T722 /workspace/coverage/cover_reg_top/8.hmac_intr_test.2179757917 Jun 11 01:48:23 PM PDT 24 Jun 11 01:48:25 PM PDT 24 22190438 ps
T723 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1738529836 Jun 11 01:48:27 PM PDT 24 Jun 11 01:48:30 PM PDT 24 81040770 ps

Test location /workspace/coverage/default/4.hmac_stress_all.413586429
Short name T5
Test name
Test status
Simulation time 95770986230 ps
CPU time 4171.16 seconds
Started Jun 11 02:15:32 PM PDT 24
Finished Jun 11 03:25:05 PM PDT 24
Peak memory 901760 kb
Host smart-0c1a72c3-9c49-4cf1-b33f-a9bcf88ca735
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413586429 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.413586429
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/176.hmac_stress_all_with_rand_reset.3672978852
Short name T9
Test name
Test status
Simulation time 24758735860 ps
CPU time 1539.75 seconds
Started Jun 11 02:17:52 PM PDT 24
Finished Jun 11 02:43:33 PM PDT 24
Peak memory 494804 kb
Host smart-34ddd510-8b00-46ec-91f7-733652395fd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672978852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 176.hmac_stress_all_with_rand_reset.3672978852
Directory /workspace/176.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.3013921203
Short name T18
Test name
Test status
Simulation time 68045611 ps
CPU time 0.81 seconds
Started Jun 11 02:15:24 PM PDT 24
Finished Jun 11 02:15:26 PM PDT 24
Peak memory 218816 kb
Host smart-9b6019de-da4f-40d7-a7bf-e2368bb849c1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013921203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.3013921203
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/49.hmac_stress_all.107908114
Short name T31
Test name
Test status
Simulation time 39088732095 ps
CPU time 1724.62 seconds
Started Jun 11 02:17:18 PM PDT 24
Finished Jun 11 02:46:04 PM PDT 24
Peak memory 767988 kb
Host smart-4117bdd7-531d-456d-a4d3-4399c7f7cc9d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107908114 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.107908114
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.2635420195
Short name T36
Test name
Test status
Simulation time 636065114 ps
CPU time 3.22 seconds
Started Jun 11 01:48:33 PM PDT 24
Finished Jun 11 01:48:37 PM PDT 24
Peak memory 199360 kb
Host smart-8f16a5f6-d348-4f33-b03b-d66ebfbef96a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635420195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.2635420195
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/142.hmac_stress_all_with_rand_reset.3974678718
Short name T8
Test name
Test status
Simulation time 436972109225 ps
CPU time 6442.83 seconds
Started Jun 11 02:17:54 PM PDT 24
Finished Jun 11 04:05:19 PM PDT 24
Peak memory 789160 kb
Host smart-842edf45-bc40-41e9-8c65-364092b5a9e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3974678718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 142.hmac_stress_all_with_rand_reset.3974678718
Directory /workspace/142.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2014065815
Short name T91
Test name
Test status
Simulation time 635310695 ps
CPU time 31.11 seconds
Started Jun 11 02:16:09 PM PDT 24
Finished Jun 11 02:16:42 PM PDT 24
Peak memory 200372 kb
Host smart-33a3e229-14f2-4783-9a2a-3760698e54c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014065815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2014065815
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2690673452
Short name T110
Test name
Test status
Simulation time 343963853 ps
CPU time 2.95 seconds
Started Jun 11 01:48:29 PM PDT 24
Finished Jun 11 01:48:33 PM PDT 24
Peak memory 199352 kb
Host smart-c962db70-7dcc-46f9-96e0-43c2ba0ad8f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690673452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2690673452
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/3.hmac_long_msg.2248490300
Short name T95
Test name
Test status
Simulation time 3842183891 ps
CPU time 75.51 seconds
Started Jun 11 02:15:35 PM PDT 24
Finished Jun 11 02:16:52 PM PDT 24
Peak memory 200488 kb
Host smart-d88b10c2-0a63-45fa-ad2a-d6f545007c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248490300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.2248490300
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.3362667841
Short name T42
Test name
Test status
Simulation time 6526954616 ps
CPU time 17.4 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:32 PM PDT 24
Peak memory 199384 kb
Host smart-81702fad-1404-4a12-aeb7-0a2027ed79c2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362667841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.3362667841
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/default/13.hmac_alert_test.4279577125
Short name T175
Test name
Test status
Simulation time 27624946 ps
CPU time 0.58 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:15:49 PM PDT 24
Peak memory 196412 kb
Host smart-5c6f812a-781f-453d-ac8b-f1467dac789d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279577125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.4279577125
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2367335379
Short name T65
Test name
Test status
Simulation time 5221237618 ps
CPU time 249.51 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:19:56 PM PDT 24
Peak memory 479900 kb
Host smart-c978f15b-1a32-4108-8df0-99a12ef0e1be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2367335379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2367335379
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.3865884230
Short name T38
Test name
Test status
Simulation time 141820142 ps
CPU time 3.92 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 199248 kb
Host smart-23dd640c-08fe-4768-a6c2-94a616ce968c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865884230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.3865884230
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/23.hmac_stress_all.3468013673
Short name T103
Test name
Test status
Simulation time 185539174460 ps
CPU time 1772.49 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:45:31 PM PDT 24
Peak memory 208668 kb
Host smart-dbb08e9b-aeff-4a14-81ac-c12b4ec346d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468013673 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.3468013673
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3588337115
Short name T101
Test name
Test status
Simulation time 2643536851 ps
CPU time 647.48 seconds
Started Jun 11 02:16:08 PM PDT 24
Finished Jun 11 02:26:57 PM PDT 24
Peak memory 710696 kb
Host smart-cf5bb2c2-0f24-41fe-bc08-2b6e64b7de83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3588337115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3588337115
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1120955323
Short name T24
Test name
Test status
Simulation time 100256631 ps
CPU time 1.06 seconds
Started Jun 11 02:15:19 PM PDT 24
Finished Jun 11 02:15:23 PM PDT 24
Peak memory 219920 kb
Host smart-e52a4f3e-5e8f-468f-8465-e8731e4fbd85
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120955323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1120955323
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_stress_all.3790784075
Short name T97
Test name
Test status
Simulation time 206372240841 ps
CPU time 1667.81 seconds
Started Jun 11 02:15:22 PM PDT 24
Finished Jun 11 02:43:12 PM PDT 24
Peak memory 747652 kb
Host smart-0cb36f5d-5448-4d5e-9923-0c69eb76343d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790784075 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.3790784075
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.4160763710
Short name T99
Test name
Test status
Simulation time 695216659 ps
CPU time 25.61 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:16:13 PM PDT 24
Peak memory 200524 kb
Host smart-81defa74-0dca-4a80-a1eb-db9148017e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160763710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.4160763710
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3872293677
Short name T59
Test name
Test status
Simulation time 139209627923 ps
CPU time 3565.6 seconds
Started Jun 11 02:17:01 PM PDT 24
Finished Jun 11 03:16:28 PM PDT 24
Peak memory 797744 kb
Host smart-169a73ae-d306-4eaa-9cf0-6fb52e9add71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872293677 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3872293677
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1850787911
Short name T78
Test name
Test status
Simulation time 308693727 ps
CPU time 6.08 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:20 PM PDT 24
Peak memory 199348 kb
Host smart-6df7e739-d1f2-4cea-bfd3-2d1af51020b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850787911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1850787911
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3169790717
Short name T83
Test name
Test status
Simulation time 1766561306 ps
CPU time 17.92 seconds
Started Jun 11 01:48:10 PM PDT 24
Finished Jun 11 01:48:32 PM PDT 24
Peak memory 199292 kb
Host smart-87b284fc-9ea9-4a1f-91d3-cdfe085790e1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169790717 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3169790717
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.935918373
Short name T676
Test name
Test status
Simulation time 31174957 ps
CPU time 0.9 seconds
Started Jun 11 01:48:10 PM PDT 24
Finished Jun 11 01:48:14 PM PDT 24
Peak memory 198624 kb
Host smart-32cbadd0-b55d-4bd0-948f-f0c037984d3f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935918373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.935918373
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.1826054362
Short name T640
Test name
Test status
Simulation time 57022665 ps
CPU time 1.63 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:17 PM PDT 24
Peak memory 199524 kb
Host smart-286968ba-2667-4f41-9d8e-f4ccfa33bb84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826054362 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.1826054362
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.2362516848
Short name T698
Test name
Test status
Simulation time 133797241 ps
CPU time 0.96 seconds
Started Jun 11 01:48:09 PM PDT 24
Finished Jun 11 01:48:13 PM PDT 24
Peak memory 199116 kb
Host smart-3e960b06-793d-422b-9ed0-690b69f56457
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362516848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.2362516848
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.2476042294
Short name T652
Test name
Test status
Simulation time 16690075 ps
CPU time 0.62 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:17 PM PDT 24
Peak memory 194288 kb
Host smart-2daef2d6-f39c-4706-a74a-3b6de81bd30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476042294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.2476042294
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.419431600
Short name T669
Test name
Test status
Simulation time 155459943 ps
CPU time 2.54 seconds
Started Jun 11 01:48:13 PM PDT 24
Finished Jun 11 01:48:19 PM PDT 24
Peak memory 199396 kb
Host smart-1a566f55-aa7c-4a3c-afe3-42e5d7cea385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419431600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.419431600
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1410588505
Short name T675
Test name
Test status
Simulation time 185468274 ps
CPU time 3.8 seconds
Started Jun 11 01:48:09 PM PDT 24
Finished Jun 11 01:48:15 PM PDT 24
Peak memory 199464 kb
Host smart-b6d5e71c-def3-421e-b0cd-bf33ede4b9f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410588505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1410588505
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.474195260
Short name T108
Test name
Test status
Simulation time 609266826 ps
CPU time 3.01 seconds
Started Jun 11 01:48:10 PM PDT 24
Finished Jun 11 01:48:16 PM PDT 24
Peak memory 199352 kb
Host smart-3e8ec84e-c362-450d-ad44-0bfed95b2bef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474195260 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.474195260
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.908403415
Short name T716
Test name
Test status
Simulation time 204435154 ps
CPU time 3.06 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 198932 kb
Host smart-b69a882b-3608-4500-89e5-e0a88bb7aed0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908403415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.908403415
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.148564423
Short name T87
Test name
Test status
Simulation time 217348533 ps
CPU time 9.83 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 199256 kb
Host smart-982fd66e-ac5b-4dc1-a0ac-9a80669e45c3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148564423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.148564423
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.747032852
Short name T86
Test name
Test status
Simulation time 29666323 ps
CPU time 0.84 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 198204 kb
Host smart-5da2f4d7-75bc-4ff1-8a14-d5315cd98a06
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747032852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.747032852
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.646284978
Short name T600
Test name
Test status
Simulation time 76660085 ps
CPU time 1.82 seconds
Started Jun 11 01:48:14 PM PDT 24
Finished Jun 11 01:48:19 PM PDT 24
Peak memory 199400 kb
Host smart-9663f093-14c6-4c72-88ab-2b5830ceb117
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646284978 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.646284978
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1945894028
Short name T721
Test name
Test status
Simulation time 49565451 ps
CPU time 0.83 seconds
Started Jun 11 01:48:13 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 198652 kb
Host smart-3cf2e720-4004-477a-824a-73c0a01b261f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945894028 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1945894028
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.469818981
Short name T623
Test name
Test status
Simulation time 72949081 ps
CPU time 0.59 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:17 PM PDT 24
Peak memory 194260 kb
Host smart-05783906-db97-43a2-a42b-e871b00abd20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469818981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.469818981
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.3556463017
Short name T717
Test name
Test status
Simulation time 82304555 ps
CPU time 1.12 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:15 PM PDT 24
Peak memory 199296 kb
Host smart-889309df-1cdb-49e4-a842-c12f478618e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556463017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.3556463017
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.720481499
Short name T645
Test name
Test status
Simulation time 65881746 ps
CPU time 3.33 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:17 PM PDT 24
Peak memory 199428 kb
Host smart-ccd013ca-1fd2-4217-87e8-6596548b1727
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720481499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.720481499
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.1243727091
Short name T34
Test name
Test status
Simulation time 292949211 ps
CPU time 4.17 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:21 PM PDT 24
Peak memory 199396 kb
Host smart-850f4d1b-6561-478e-83c9-ba1cd2d5a7f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243727091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.1243727091
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.3811380935
Short name T714
Test name
Test status
Simulation time 315321592982 ps
CPU time 391.46 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:54:59 PM PDT 24
Peak memory 215832 kb
Host smart-2a11abe9-b71b-4f4d-9e8a-7223c17568f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811380935 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.3811380935
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.2270611154
Short name T642
Test name
Test status
Simulation time 61886238 ps
CPU time 0.95 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 198668 kb
Host smart-3a17970b-7baa-4bcb-9a31-13bbd04b8882
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270611154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.2270611154
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3785656630
Short name T691
Test name
Test status
Simulation time 44088723 ps
CPU time 0.58 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 194276 kb
Host smart-623a8287-3a77-49b7-8d1e-583c1304e112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785656630 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3785656630
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.4123906835
Short name T618
Test name
Test status
Simulation time 45168289 ps
CPU time 2.06 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 199356 kb
Host smart-d14010f3-a7ea-477f-80ff-ed77f550b17b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123906835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.4123906835
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.2140291039
Short name T45
Test name
Test status
Simulation time 193278672 ps
CPU time 2.74 seconds
Started Jun 11 01:48:27 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 199384 kb
Host smart-6ba35a84-a271-4f77-a34c-f1397cb1a57d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140291039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.2140291039
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.1494909433
Short name T695
Test name
Test status
Simulation time 290159466 ps
CPU time 4.49 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 199432 kb
Host smart-9a5b2934-35e9-4453-b277-ab5e8644bf9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494909433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.1494909433
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.1031920463
Short name T613
Test name
Test status
Simulation time 22677384 ps
CPU time 1.24 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 199256 kb
Host smart-a934e158-3832-48f1-917e-a92c2b42f9fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031920463 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.1031920463
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.3542660103
Short name T662
Test name
Test status
Simulation time 40804564 ps
CPU time 0.76 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 197068 kb
Host smart-3b61c811-aeb4-42ff-a7c8-d72f354da941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542660103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.3542660103
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2894488976
Short name T700
Test name
Test status
Simulation time 29420962 ps
CPU time 0.62 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 194204 kb
Host smart-69809252-a821-4ad8-80b9-af7b37688112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894488976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2894488976
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.1761505700
Short name T656
Test name
Test status
Simulation time 93995260 ps
CPU time 1.72 seconds
Started Jun 11 01:48:27 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 199328 kb
Host smart-6b203b0b-aab0-4a54-aaac-45df343b83dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761505700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.1761505700
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.1047896620
Short name T666
Test name
Test status
Simulation time 136538491 ps
CPU time 2.95 seconds
Started Jun 11 01:48:22 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 199464 kb
Host smart-29a9f42f-63f5-485f-ab93-eb584ee1c13a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047896620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.1047896620
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2504196204
Short name T693
Test name
Test status
Simulation time 175968830 ps
CPU time 3.1 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 199400 kb
Host smart-dba5c9cb-65a2-4c1f-ae04-ad9bb66dc11d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504196204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2504196204
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2910707839
Short name T598
Test name
Test status
Simulation time 330092192 ps
CPU time 2.41 seconds
Started Jun 11 01:48:27 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 199452 kb
Host smart-8c76f831-4b60-468f-b42c-7ae25d74e96f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910707839 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2910707839
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2699059070
Short name T711
Test name
Test status
Simulation time 29298447 ps
CPU time 0.92 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 199148 kb
Host smart-706ff271-cbc1-43da-b4fd-7ab264a32e88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699059070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2699059070
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.783113122
Short name T677
Test name
Test status
Simulation time 12238057 ps
CPU time 0.62 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:29 PM PDT 24
Peak memory 194212 kb
Host smart-0028a842-3053-4494-beed-fecea4379d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783113122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.783113122
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3788133024
Short name T620
Test name
Test status
Simulation time 342839524 ps
CPU time 1.86 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 199408 kb
Host smart-8ee6fc17-379c-453e-93ab-500cc975aa09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788133024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3788133024
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2325748991
Short name T46
Test name
Test status
Simulation time 49830256 ps
CPU time 2.72 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 199380 kb
Host smart-82f33942-bd5c-4233-b95e-7523aece82c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325748991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2325748991
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.763798686
Short name T706
Test name
Test status
Simulation time 158500817 ps
CPU time 3.3 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:32 PM PDT 24
Peak memory 199412 kb
Host smart-1d436ade-ae38-4f74-ab0a-a8120681d0ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763798686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.763798686
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.694726660
Short name T602
Test name
Test status
Simulation time 245122477 ps
CPU time 1.82 seconds
Started Jun 11 01:48:22 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 199520 kb
Host smart-bb7d85ea-9c6f-423e-bed5-c9887b8dc494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694726660 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.694726660
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.3134046205
Short name T659
Test name
Test status
Simulation time 110456782 ps
CPU time 0.66 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:26 PM PDT 24
Peak memory 197112 kb
Host smart-b1757948-686a-4704-b42b-e96dde5bf14f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134046205 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.3134046205
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3226936284
Short name T718
Test name
Test status
Simulation time 41594194 ps
CPU time 0.65 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 194196 kb
Host smart-c03da14b-15b1-4889-8a85-52deda85152c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226936284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3226936284
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.745648585
Short name T692
Test name
Test status
Simulation time 131952496 ps
CPU time 1.68 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 199376 kb
Host smart-c315576d-1178-4b9c-955f-1b5ed71b504c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745648585 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.745648585
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.3700403709
Short name T660
Test name
Test status
Simulation time 314679027 ps
CPU time 1.9 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 199444 kb
Host smart-1f31a8b7-573c-4720-a918-9c8f7cb2d418
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700403709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.3700403709
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.515195647
Short name T703
Test name
Test status
Simulation time 358200112 ps
CPU time 2.17 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:29 PM PDT 24
Peak memory 199448 kb
Host smart-e534548b-b09c-4e65-984f-33bb4ff449cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515195647 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.515195647
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.3585295073
Short name T683
Test name
Test status
Simulation time 17424617 ps
CPU time 0.69 seconds
Started Jun 11 01:48:27 PM PDT 24
Finished Jun 11 01:48:30 PM PDT 24
Peak memory 197096 kb
Host smart-772bdc33-d8ea-4889-9d1d-c87a8cf6339f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585295073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.3585295073
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3652821379
Short name T631
Test name
Test status
Simulation time 15834919 ps
CPU time 0.63 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 194180 kb
Host smart-f7e5b1e5-d415-48cc-af57-a7ac6b9ea751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652821379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3652821379
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1931132947
Short name T594
Test name
Test status
Simulation time 47243531 ps
CPU time 2.21 seconds
Started Jun 11 01:48:27 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 199364 kb
Host smart-cf66b0af-fca5-44ef-8ae8-47f61c312405
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931132947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1931132947
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1224793287
Short name T610
Test name
Test status
Simulation time 34398530 ps
CPU time 1.75 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:30 PM PDT 24
Peak memory 199432 kb
Host smart-f67c7231-68ff-4ae0-b531-57c110a81f41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224793287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1224793287
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.1531065031
Short name T665
Test name
Test status
Simulation time 461813688 ps
CPU time 4.58 seconds
Started Jun 11 01:48:28 PM PDT 24
Finished Jun 11 01:48:34 PM PDT 24
Peak memory 199432 kb
Host smart-f3af3e56-2419-4cfb-b02a-0ec8685b5e96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531065031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.1531065031
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2458990887
Short name T43
Test name
Test status
Simulation time 129659075 ps
CPU time 1.25 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:30 PM PDT 24
Peak memory 199272 kb
Host smart-21bd0e57-c4b1-427e-b225-deb68071d48e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458990887 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2458990887
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.1650940031
Short name T82
Test name
Test status
Simulation time 16575130 ps
CPU time 0.94 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:29 PM PDT 24
Peak memory 199120 kb
Host smart-869a0be3-4a14-4496-a502-e628d369ac5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650940031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.1650940031
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.4175868956
Short name T674
Test name
Test status
Simulation time 13494382 ps
CPU time 0.57 seconds
Started Jun 11 01:48:30 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 194252 kb
Host smart-9a4919f4-31bd-41b7-854f-14db64123ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175868956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.4175868956
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2254142047
Short name T607
Test name
Test status
Simulation time 223143670 ps
CPU time 1.22 seconds
Started Jun 11 01:48:28 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 197920 kb
Host smart-ea9d7b16-026d-4dd4-9765-60bc773186e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254142047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2254142047
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.1090000666
Short name T699
Test name
Test status
Simulation time 80017134 ps
CPU time 2.16 seconds
Started Jun 11 01:48:28 PM PDT 24
Finished Jun 11 01:48:32 PM PDT 24
Peak memory 199480 kb
Host smart-2a212535-ab00-4f70-9a72-8ec94639f5e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090000666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.1090000666
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.3082060418
Short name T658
Test name
Test status
Simulation time 385671784 ps
CPU time 1.96 seconds
Started Jun 11 01:48:27 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 199408 kb
Host smart-776692ce-4cfa-45a0-82fc-549c6617865b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082060418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.3082060418
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.2435555117
Short name T704
Test name
Test status
Simulation time 74373133 ps
CPU time 2.62 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 207692 kb
Host smart-7249b4b7-723e-4ff2-aa70-6b6a337ad2ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435555117 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.2435555117
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.393116163
Short name T39
Test name
Test status
Simulation time 31035918 ps
CPU time 1.01 seconds
Started Jun 11 01:48:29 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 198816 kb
Host smart-839c9c5c-21d9-42f8-9142-bc119c2b19d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393116163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.393116163
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.1984986069
Short name T619
Test name
Test status
Simulation time 14695609 ps
CPU time 0.59 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:26 PM PDT 24
Peak memory 194152 kb
Host smart-c46e107e-89ab-4b4d-85be-f882dcf75338
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984986069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.1984986069
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.4210294672
Short name T635
Test name
Test status
Simulation time 421747576 ps
CPU time 2.23 seconds
Started Jun 11 01:48:30 PM PDT 24
Finished Jun 11 01:48:33 PM PDT 24
Peak memory 199352 kb
Host smart-eb8b1448-45e7-43c1-9d46-4cd8c53c9cde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210294672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.4210294672
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3293009483
Short name T639
Test name
Test status
Simulation time 64036110 ps
CPU time 1.64 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 199440 kb
Host smart-05e23d80-ad7e-4c58-932b-a9967adb21c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293009483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3293009483
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3454664341
Short name T601
Test name
Test status
Simulation time 81737710 ps
CPU time 2.37 seconds
Started Jun 11 01:48:30 PM PDT 24
Finished Jun 11 01:48:33 PM PDT 24
Peak memory 199452 kb
Host smart-e97e51fd-2c46-49d6-9ccf-2665ae7a18b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454664341 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3454664341
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3181893000
Short name T710
Test name
Test status
Simulation time 57477318 ps
CPU time 0.9 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:29 PM PDT 24
Peak memory 198788 kb
Host smart-aa4d38d8-cd57-42af-90de-e8362ee7b039
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181893000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3181893000
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.2431178953
Short name T638
Test name
Test status
Simulation time 22920716 ps
CPU time 0.62 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:26 PM PDT 24
Peak memory 194180 kb
Host smart-66e17cf3-0e9d-4e6a-87cb-147c5cf506cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431178953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.2431178953
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3749025331
Short name T705
Test name
Test status
Simulation time 334547346 ps
CPU time 2.51 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 199416 kb
Host smart-800e4ac4-1778-4643-a37e-e3ef26557d31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749025331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3749025331
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2558007478
Short name T621
Test name
Test status
Simulation time 146279566 ps
CPU time 4.12 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:32 PM PDT 24
Peak memory 199448 kb
Host smart-8e6c49dc-7046-40b1-94b2-12db6d624b19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558007478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2558007478
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.2919162064
Short name T641
Test name
Test status
Simulation time 87491386 ps
CPU time 1.79 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 199384 kb
Host smart-c6116ea9-03c9-4bc7-904d-881af1e9ac5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919162064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.2919162064
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.1562224706
Short name T44
Test name
Test status
Simulation time 290987719 ps
CPU time 2.54 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 199460 kb
Host smart-2f0008a8-0200-4b58-a1dd-2fbe6812ad85
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562224706 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.1562224706
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.1514011142
Short name T688
Test name
Test status
Simulation time 88146923 ps
CPU time 0.78 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 198164 kb
Host smart-4ad2907d-49c3-43ad-b4d4-ea2ae135ee3b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514011142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.1514011142
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2327038298
Short name T608
Test name
Test status
Simulation time 49060457 ps
CPU time 0.6 seconds
Started Jun 11 01:48:31 PM PDT 24
Finished Jun 11 01:48:32 PM PDT 24
Peak memory 194252 kb
Host smart-94a5fc6b-7513-4531-9f6c-37972c7e0430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327038298 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2327038298
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.1466941742
Short name T719
Test name
Test status
Simulation time 273490166 ps
CPU time 2.41 seconds
Started Jun 11 01:48:30 PM PDT 24
Finished Jun 11 01:48:34 PM PDT 24
Peak memory 199292 kb
Host smart-243d26ab-b4c8-4c11-aedb-c9edad7e5108
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466941742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.1466941742
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2096671215
Short name T615
Test name
Test status
Simulation time 36459589 ps
CPU time 1.8 seconds
Started Jun 11 01:48:31 PM PDT 24
Finished Jun 11 01:48:34 PM PDT 24
Peak memory 199456 kb
Host smart-78414541-6224-4c22-865c-9bafe75dd56c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096671215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2096671215
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.662467762
Short name T617
Test name
Test status
Simulation time 98129080 ps
CPU time 1.73 seconds
Started Jun 11 01:48:30 PM PDT 24
Finished Jun 11 01:48:33 PM PDT 24
Peak memory 199276 kb
Host smart-ee630503-c1ef-4704-ba77-0027a57bb548
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662467762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.662467762
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.1404653539
Short name T649
Test name
Test status
Simulation time 127169324 ps
CPU time 1.12 seconds
Started Jun 11 01:48:43 PM PDT 24
Finished Jun 11 01:48:46 PM PDT 24
Peak memory 199284 kb
Host smart-55f4b4c9-d57a-49d6-abd3-a1c1daad2778
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404653539 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.1404653539
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.925186055
Short name T685
Test name
Test status
Simulation time 34477959 ps
CPU time 0.73 seconds
Started Jun 11 01:48:52 PM PDT 24
Finished Jun 11 01:48:54 PM PDT 24
Peak memory 197376 kb
Host smart-5deb8180-b7fc-4c43-80d5-c6e583ab8981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925186055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.925186055
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.4044644194
Short name T687
Test name
Test status
Simulation time 15585549 ps
CPU time 0.61 seconds
Started Jun 11 01:48:46 PM PDT 24
Finished Jun 11 01:48:47 PM PDT 24
Peak memory 194224 kb
Host smart-65b433f7-f678-4985-a647-046d169d00c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044644194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.4044644194
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.1078590312
Short name T643
Test name
Test status
Simulation time 776400746 ps
CPU time 2.46 seconds
Started Jun 11 01:48:42 PM PDT 24
Finished Jun 11 01:48:46 PM PDT 24
Peak memory 199404 kb
Host smart-a02834d3-aa94-4358-a4d6-52f9835c65d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078590312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.1078590312
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2935419483
Short name T636
Test name
Test status
Simulation time 61587551 ps
CPU time 3.25 seconds
Started Jun 11 01:48:38 PM PDT 24
Finished Jun 11 01:48:42 PM PDT 24
Peak memory 199456 kb
Host smart-c9dedc13-7ecf-4f83-a0e7-660f5d86df0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935419483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2935419483
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.3986323525
Short name T112
Test name
Test status
Simulation time 1202562979 ps
CPU time 4.58 seconds
Started Jun 11 01:48:41 PM PDT 24
Finished Jun 11 01:48:47 PM PDT 24
Peak memory 199468 kb
Host smart-1764cc3c-4822-42ab-a81d-2648eb29752e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986323525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.3986323525
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1662338661
Short name T81
Test name
Test status
Simulation time 1095439389 ps
CPU time 5.99 seconds
Started Jun 11 01:48:14 PM PDT 24
Finished Jun 11 01:48:23 PM PDT 24
Peak memory 199352 kb
Host smart-3cc7ff57-edd9-48bc-9640-8301e4cf0149
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662338661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1662338661
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.4063561503
Short name T80
Test name
Test status
Simulation time 30081755 ps
CPU time 0.88 seconds
Started Jun 11 01:48:10 PM PDT 24
Finished Jun 11 01:48:14 PM PDT 24
Peak memory 198804 kb
Host smart-6b75ad08-aa81-44c4-a57d-3e68c24f1c59
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063561503 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.4063561503
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.313742133
Short name T622
Test name
Test status
Simulation time 57879410221 ps
CPU time 156.1 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:50:55 PM PDT 24
Peak memory 215160 kb
Host smart-4e2bebab-290e-499a-b3b0-4963ed36af99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313742133 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.313742133
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2094445101
Short name T686
Test name
Test status
Simulation time 126297421 ps
CPU time 0.93 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:16 PM PDT 24
Peak memory 198900 kb
Host smart-4fda4682-3596-41ca-b655-ef32017f5580
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094445101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2094445101
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2531588667
Short name T596
Test name
Test status
Simulation time 53077569 ps
CPU time 0.61 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:48:19 PM PDT 24
Peak memory 194180 kb
Host smart-1e22897a-34ef-4fef-8661-2cd9f7e425ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531588667 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2531588667
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.3864076244
Short name T609
Test name
Test status
Simulation time 417001106 ps
CPU time 1.61 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:48:20 PM PDT 24
Peak memory 199396 kb
Host smart-db788899-19bf-41c9-aec9-3a7aab13acf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864076244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.3864076244
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2444392300
Short name T702
Test name
Test status
Simulation time 73290044 ps
CPU time 1.51 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:16 PM PDT 24
Peak memory 199468 kb
Host smart-ddf4bacb-8713-48fd-84dd-b0cff1a7b5b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444392300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2444392300
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3954885524
Short name T35
Test name
Test status
Simulation time 368348403 ps
CPU time 1.89 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:17 PM PDT 24
Peak memory 199440 kb
Host smart-66fb771f-74a4-46d1-b67f-6fbd1080b031
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954885524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3954885524
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2224818910
Short name T603
Test name
Test status
Simulation time 15428842 ps
CPU time 0.65 seconds
Started Jun 11 01:48:42 PM PDT 24
Finished Jun 11 01:48:44 PM PDT 24
Peak memory 194272 kb
Host smart-dd75ea2e-4010-4a01-b6dc-baec46b958de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224818910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2224818910
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.148570433
Short name T644
Test name
Test status
Simulation time 40410379 ps
CPU time 0.56 seconds
Started Jun 11 01:48:42 PM PDT 24
Finished Jun 11 01:48:45 PM PDT 24
Peak memory 194168 kb
Host smart-0879d1ef-5eb7-49ad-8f87-20993b829a05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148570433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.148570433
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.1357449400
Short name T634
Test name
Test status
Simulation time 39261874 ps
CPU time 0.64 seconds
Started Jun 11 01:48:40 PM PDT 24
Finished Jun 11 01:48:42 PM PDT 24
Peak memory 194328 kb
Host smart-792d7f97-e1d0-459f-90b2-a337af63a436
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357449400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.1357449400
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.4079635883
Short name T679
Test name
Test status
Simulation time 52067077 ps
CPU time 0.62 seconds
Started Jun 11 01:48:41 PM PDT 24
Finished Jun 11 01:48:43 PM PDT 24
Peak memory 194184 kb
Host smart-b563f345-88b4-4d47-90cd-9156eabbd89b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079635883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.4079635883
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.2505930019
Short name T697
Test name
Test status
Simulation time 42662274 ps
CPU time 0.6 seconds
Started Jun 11 01:48:43 PM PDT 24
Finished Jun 11 01:48:45 PM PDT 24
Peak memory 194260 kb
Host smart-fbeb30a4-473a-4c32-af0d-b296177b44da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505930019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.2505930019
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.993677906
Short name T627
Test name
Test status
Simulation time 13030999 ps
CPU time 0.59 seconds
Started Jun 11 01:48:50 PM PDT 24
Finished Jun 11 01:48:52 PM PDT 24
Peak memory 194252 kb
Host smart-8ddd4ee1-74b6-4538-be9a-db9429dd29e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993677906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.993677906
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.909204716
Short name T682
Test name
Test status
Simulation time 19936445 ps
CPU time 0.6 seconds
Started Jun 11 01:48:39 PM PDT 24
Finished Jun 11 01:48:41 PM PDT 24
Peak memory 194292 kb
Host smart-42bf2c0c-1377-483a-a3bd-ec1e3e2fe30e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909204716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.909204716
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1940892240
Short name T626
Test name
Test status
Simulation time 18058752 ps
CPU time 0.64 seconds
Started Jun 11 01:48:45 PM PDT 24
Finished Jun 11 01:48:47 PM PDT 24
Peak memory 194252 kb
Host smart-914d8e38-8e13-449c-a60f-73633ae33b8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940892240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1940892240
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.3146440045
Short name T647
Test name
Test status
Simulation time 96082985 ps
CPU time 0.63 seconds
Started Jun 11 01:48:39 PM PDT 24
Finished Jun 11 01:48:41 PM PDT 24
Peak memory 194288 kb
Host smart-fa355cd3-a54a-4778-8d23-242a5b4bc8f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146440045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.3146440045
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.1517420832
Short name T595
Test name
Test status
Simulation time 18494237 ps
CPU time 0.68 seconds
Started Jun 11 01:48:54 PM PDT 24
Finished Jun 11 01:48:57 PM PDT 24
Peak memory 194240 kb
Host smart-e37a3d53-6582-495b-8f0a-92787d8aa4df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517420832 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.1517420832
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3316180371
Short name T88
Test name
Test status
Simulation time 136769914 ps
CPU time 3.08 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 199340 kb
Host smart-0c332148-e108-4c22-98e2-828c1fc1962d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316180371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3316180371
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3021362594
Short name T84
Test name
Test status
Simulation time 211491036 ps
CPU time 9.9 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:38 PM PDT 24
Peak memory 198480 kb
Host smart-5428273b-f56f-43ba-879c-24c722850455
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021362594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3021362594
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.4032875415
Short name T633
Test name
Test status
Simulation time 14300220 ps
CPU time 0.72 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:28 PM PDT 24
Peak memory 197404 kb
Host smart-604668b4-6622-4e53-be37-13705928abaf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032875415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.4032875415
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3440963714
Short name T625
Test name
Test status
Simulation time 249215190 ps
CPU time 3.13 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 199424 kb
Host smart-e2049fcf-bac4-4e28-be90-7b67ae489228
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440963714 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3440963714
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.960355123
Short name T678
Test name
Test status
Simulation time 24849782 ps
CPU time 0.85 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:17 PM PDT 24
Peak memory 198556 kb
Host smart-7aac53aa-200c-472b-b36d-c0020c0772ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960355123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.960355123
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.1076264365
Short name T604
Test name
Test status
Simulation time 49608820 ps
CPU time 0.6 seconds
Started Jun 11 01:48:11 PM PDT 24
Finished Jun 11 01:48:15 PM PDT 24
Peak memory 194248 kb
Host smart-f6e46071-3e3a-4ba3-8ff8-262560508d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076264365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.1076264365
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.1952910011
Short name T684
Test name
Test status
Simulation time 84364472 ps
CPU time 1.15 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:29 PM PDT 24
Peak memory 197840 kb
Host smart-694d6641-e318-47a4-b87f-a0de5e5412d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952910011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.1952910011
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1228489444
Short name T696
Test name
Test status
Simulation time 197215039 ps
CPU time 3.73 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:32 PM PDT 24
Peak memory 199204 kb
Host smart-db8f9228-71eb-42a0-9723-94ac156a1a23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228489444 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1228489444
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.2576614597
Short name T109
Test name
Test status
Simulation time 879413433 ps
CPU time 4.1 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:32 PM PDT 24
Peak memory 199404 kb
Host smart-a7d88345-f3f4-470f-8131-06e5fddf458c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576614597 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.2576614597
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.3212581625
Short name T629
Test name
Test status
Simulation time 16941088 ps
CPU time 0.61 seconds
Started Jun 11 01:48:41 PM PDT 24
Finished Jun 11 01:48:43 PM PDT 24
Peak memory 194204 kb
Host smart-ca97827d-3b81-4ac2-9f77-40f5f4ddd4ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212581625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.3212581625
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.336000677
Short name T681
Test name
Test status
Simulation time 34190935 ps
CPU time 0.59 seconds
Started Jun 11 01:48:45 PM PDT 24
Finished Jun 11 01:48:47 PM PDT 24
Peak memory 194244 kb
Host smart-e8a4ab08-8ac7-4c16-a921-d86367e0956d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336000677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.336000677
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.1257333052
Short name T672
Test name
Test status
Simulation time 31762544 ps
CPU time 0.59 seconds
Started Jun 11 01:48:41 PM PDT 24
Finished Jun 11 01:48:43 PM PDT 24
Peak memory 194280 kb
Host smart-636b2599-e14b-4347-9ba5-f56af9c2e552
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257333052 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.1257333052
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.1276564527
Short name T646
Test name
Test status
Simulation time 62624287 ps
CPU time 0.6 seconds
Started Jun 11 01:48:44 PM PDT 24
Finished Jun 11 01:48:46 PM PDT 24
Peak memory 194256 kb
Host smart-ba2f5d84-0dc6-43a8-9031-fb6b21d325a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276564527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.1276564527
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1309558046
Short name T664
Test name
Test status
Simulation time 12915974 ps
CPU time 0.62 seconds
Started Jun 11 01:48:51 PM PDT 24
Finished Jun 11 01:48:53 PM PDT 24
Peak memory 194380 kb
Host smart-587e5a26-803e-4b25-bc21-7986f868307e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309558046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1309558046
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3738716695
Short name T611
Test name
Test status
Simulation time 16583062 ps
CPU time 0.65 seconds
Started Jun 11 01:48:41 PM PDT 24
Finished Jun 11 01:48:43 PM PDT 24
Peak memory 194320 kb
Host smart-e7be1ec1-6f7e-4008-9f0c-b9142c8edc4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738716695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3738716695
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.301006302
Short name T694
Test name
Test status
Simulation time 12896808 ps
CPU time 0.58 seconds
Started Jun 11 01:48:37 PM PDT 24
Finished Jun 11 01:48:39 PM PDT 24
Peak memory 194312 kb
Host smart-bcde71f2-a066-4819-a0d7-e04bd3bce05f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301006302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.301006302
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2808654095
Short name T616
Test name
Test status
Simulation time 16687770 ps
CPU time 0.63 seconds
Started Jun 11 01:48:39 PM PDT 24
Finished Jun 11 01:48:40 PM PDT 24
Peak memory 194220 kb
Host smart-e30adc0a-98bc-4899-958a-b8d4123ddb0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808654095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2808654095
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.492504991
Short name T668
Test name
Test status
Simulation time 25140244 ps
CPU time 0.63 seconds
Started Jun 11 01:48:42 PM PDT 24
Finished Jun 11 01:48:44 PM PDT 24
Peak memory 194388 kb
Host smart-b4431f09-deb1-4ba0-a023-432686122bd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492504991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.492504991
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.514039997
Short name T673
Test name
Test status
Simulation time 13306354 ps
CPU time 0.6 seconds
Started Jun 11 01:48:38 PM PDT 24
Finished Jun 11 01:48:40 PM PDT 24
Peak memory 194252 kb
Host smart-15096d14-5645-46c7-a0f4-50eee7a7d219
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514039997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.514039997
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.416842279
Short name T76
Test name
Test status
Simulation time 153977263 ps
CPU time 8.1 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:48:26 PM PDT 24
Peak memory 199380 kb
Host smart-2b53d783-261b-44ef-8370-7b28dcab857e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416842279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.416842279
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.1221458156
Short name T709
Test name
Test status
Simulation time 111083315 ps
CPU time 5.06 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:48:23 PM PDT 24
Peak memory 199324 kb
Host smart-e8414310-bb88-4ca9-9f40-f4717d1bb3d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221458156 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.1221458156
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.1301086697
Short name T605
Test name
Test status
Simulation time 129411907 ps
CPU time 1.01 seconds
Started Jun 11 01:48:14 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 199116 kb
Host smart-a2446773-69db-4393-b47d-684c6cddee94
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301086697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.1301086697
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.391703491
Short name T715
Test name
Test status
Simulation time 68388654508 ps
CPU time 668.54 seconds
Started Jun 11 01:48:13 PM PDT 24
Finished Jun 11 01:59:26 PM PDT 24
Peak memory 225120 kb
Host smart-3e1a3507-b9eb-4303-8c24-6bf2505d46c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391703491 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.391703491
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.1903777079
Short name T650
Test name
Test status
Simulation time 23289465 ps
CPU time 0.68 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 197716 kb
Host smart-5c407b91-60b9-4d93-8b9f-310bdc8c9ba0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903777079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.1903777079
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.2529729003
Short name T708
Test name
Test status
Simulation time 17969289 ps
CPU time 0.64 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:48:19 PM PDT 24
Peak memory 194368 kb
Host smart-7266e4a1-4850-4f7f-9ac2-c6aaa47ab7e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529729003 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.2529729003
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2662514216
Short name T599
Test name
Test status
Simulation time 321341810 ps
CPU time 1.15 seconds
Started Jun 11 01:48:13 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 199344 kb
Host smart-3431a2b9-14bf-4552-a3b6-a4cc73fed174
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662514216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2662514216
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.3986824506
Short name T657
Test name
Test status
Simulation time 287063837 ps
CPU time 1.68 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:29 PM PDT 24
Peak memory 199432 kb
Host smart-06f0c56a-287e-4dfa-a7b9-78a9f4867d66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986824506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.3986824506
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.1348502797
Short name T113
Test name
Test status
Simulation time 452988731 ps
CPU time 4.42 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:48:23 PM PDT 24
Peak memory 199372 kb
Host smart-0e9c45d7-eac2-4ed6-9b72-e1e0f05c9f1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348502797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.1348502797
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.4136023611
Short name T663
Test name
Test status
Simulation time 10397179 ps
CPU time 0.58 seconds
Started Jun 11 01:48:40 PM PDT 24
Finished Jun 11 01:48:42 PM PDT 24
Peak memory 194276 kb
Host smart-377221a0-42cd-4684-8219-5db2489286ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136023611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.4136023611
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.1962801239
Short name T667
Test name
Test status
Simulation time 39859046 ps
CPU time 0.6 seconds
Started Jun 11 01:48:42 PM PDT 24
Finished Jun 11 01:48:44 PM PDT 24
Peak memory 194356 kb
Host smart-f53e28d1-a4d3-471d-b4e0-4d57ebc914b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962801239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.1962801239
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.3374508333
Short name T651
Test name
Test status
Simulation time 43727766 ps
CPU time 0.61 seconds
Started Jun 11 01:48:40 PM PDT 24
Finished Jun 11 01:48:43 PM PDT 24
Peak memory 194196 kb
Host smart-8e9eb35f-fa36-4ed1-81db-618bddd39a31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374508333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.3374508333
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1614276357
Short name T624
Test name
Test status
Simulation time 14652973 ps
CPU time 0.62 seconds
Started Jun 11 01:48:44 PM PDT 24
Finished Jun 11 01:48:46 PM PDT 24
Peak memory 194308 kb
Host smart-6cf4b530-2940-49c4-b981-259a99306a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614276357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1614276357
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.397610219
Short name T653
Test name
Test status
Simulation time 31117645 ps
CPU time 0.62 seconds
Started Jun 11 01:48:39 PM PDT 24
Finished Jun 11 01:48:41 PM PDT 24
Peak memory 194280 kb
Host smart-2e09656e-f5a8-4407-ab60-3b14a1dd2181
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397610219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.397610219
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2419321989
Short name T597
Test name
Test status
Simulation time 15975232 ps
CPU time 0.64 seconds
Started Jun 11 01:48:40 PM PDT 24
Finished Jun 11 01:48:42 PM PDT 24
Peak memory 194228 kb
Host smart-422b3a95-94a8-4eb5-ac74-381a75d5306a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419321989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2419321989
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.1976312843
Short name T614
Test name
Test status
Simulation time 16515216 ps
CPU time 0.61 seconds
Started Jun 11 01:48:52 PM PDT 24
Finished Jun 11 01:48:53 PM PDT 24
Peak memory 194284 kb
Host smart-e9bc491b-e6ca-4146-96f7-618fe5f644c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976312843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.1976312843
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3121329336
Short name T670
Test name
Test status
Simulation time 14187324 ps
CPU time 0.6 seconds
Started Jun 11 01:48:41 PM PDT 24
Finished Jun 11 01:48:43 PM PDT 24
Peak memory 194260 kb
Host smart-dc8ccd30-bea4-49a6-ada1-e7d2b1c1ba97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121329336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3121329336
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2176333184
Short name T628
Test name
Test status
Simulation time 144904609 ps
CPU time 0.65 seconds
Started Jun 11 01:48:42 PM PDT 24
Finished Jun 11 01:48:44 PM PDT 24
Peak memory 194212 kb
Host smart-84faefe9-eb89-4400-a698-f8623563ba2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176333184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2176333184
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.2294314013
Short name T606
Test name
Test status
Simulation time 13462075 ps
CPU time 0.57 seconds
Started Jun 11 01:48:49 PM PDT 24
Finished Jun 11 01:48:50 PM PDT 24
Peak memory 194304 kb
Host smart-3f1a7f6b-1a0c-4aa0-95be-cf6149082a32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294314013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.2294314013
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.1292552415
Short name T671
Test name
Test status
Simulation time 116039295 ps
CPU time 1.35 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 199484 kb
Host smart-bfec696f-f584-4336-8033-8ed34add7ab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292552415 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.1292552415
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2183072664
Short name T85
Test name
Test status
Simulation time 30606721 ps
CPU time 0.95 seconds
Started Jun 11 01:48:14 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 199040 kb
Host smart-58f3ad58-5f50-4b45-8c0a-7c7dca6b101b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183072664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2183072664
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3639968291
Short name T712
Test name
Test status
Simulation time 21751196 ps
CPU time 0.65 seconds
Started Jun 11 01:48:14 PM PDT 24
Finished Jun 11 01:48:18 PM PDT 24
Peak memory 194272 kb
Host smart-55b619cb-4ea9-42bb-82b9-fd35eecff7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639968291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3639968291
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.3319167254
Short name T632
Test name
Test status
Simulation time 234308595 ps
CPU time 2.38 seconds
Started Jun 11 01:48:12 PM PDT 24
Finished Jun 11 01:48:19 PM PDT 24
Peak memory 199340 kb
Host smart-165d588e-aceb-478c-bac0-84b90f364c4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319167254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.3319167254
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.355337105
Short name T701
Test name
Test status
Simulation time 36992032 ps
CPU time 2.05 seconds
Started Jun 11 01:48:14 PM PDT 24
Finished Jun 11 01:48:19 PM PDT 24
Peak memory 199436 kb
Host smart-fcda4d2f-c4db-432d-8eb2-e486d69a31f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355337105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.355337105
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1992408278
Short name T107
Test name
Test status
Simulation time 58194097 ps
CPU time 1.86 seconds
Started Jun 11 01:48:15 PM PDT 24
Finished Jun 11 01:48:19 PM PDT 24
Peak memory 199416 kb
Host smart-87339cc5-d958-46cc-8e4c-ccd9044f399c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992408278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1992408278
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2753731219
Short name T713
Test name
Test status
Simulation time 159853647117 ps
CPU time 1104.2 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 02:06:50 PM PDT 24
Peak memory 215964 kb
Host smart-d649380a-b3ad-47fa-9309-11c08b958877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753731219 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2753731219
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1738529836
Short name T723
Test name
Test status
Simulation time 81040770 ps
CPU time 0.83 seconds
Started Jun 11 01:48:27 PM PDT 24
Finished Jun 11 01:48:30 PM PDT 24
Peak memory 198588 kb
Host smart-38b1cb16-a5f8-49c0-ac55-462af1edfa85
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738529836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1738529836
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.740070619
Short name T661
Test name
Test status
Simulation time 62003801 ps
CPU time 0.64 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 194332 kb
Host smart-c59ac4b4-b0f3-4b46-ad54-d1386f7f567e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740070619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.740070619
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3919563033
Short name T720
Test name
Test status
Simulation time 538719428 ps
CPU time 1.51 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:26 PM PDT 24
Peak memory 199396 kb
Host smart-a8330192-e62f-4b54-8669-f46962518939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919563033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3919563033
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.272018241
Short name T630
Test name
Test status
Simulation time 237917081 ps
CPU time 3.16 seconds
Started Jun 11 01:48:13 PM PDT 24
Finished Jun 11 01:48:20 PM PDT 24
Peak memory 199416 kb
Host smart-19206a05-e943-4551-afef-498113d33931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272018241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.272018241
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2705044265
Short name T690
Test name
Test status
Simulation time 155249491 ps
CPU time 1.28 seconds
Started Jun 11 01:48:22 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 199272 kb
Host smart-ee8591b7-1099-410d-996c-b6702c6cdde9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705044265 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2705044265
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.2656995215
Short name T77
Test name
Test status
Simulation time 21234952 ps
CPU time 0.91 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:26 PM PDT 24
Peak memory 199140 kb
Host smart-7371a4f1-a187-49d7-8a5d-13eb98a8a67d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656995215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.2656995215
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.992227481
Short name T648
Test name
Test status
Simulation time 28375662 ps
CPU time 0.62 seconds
Started Jun 11 01:48:27 PM PDT 24
Finished Jun 11 01:48:30 PM PDT 24
Peak memory 194252 kb
Host smart-5b649182-5708-47d5-98ce-db414cafd378
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992227481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.992227481
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.346685266
Short name T654
Test name
Test status
Simulation time 247844293 ps
CPU time 1.28 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:26 PM PDT 24
Peak memory 197688 kb
Host smart-048296d7-3e63-43d6-a2f3-5c0451b035e1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346685266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.346685266
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.4171506291
Short name T707
Test name
Test status
Simulation time 223805490 ps
CPU time 4.1 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:32 PM PDT 24
Peak memory 199416 kb
Host smart-2480eae9-137d-4b01-8f6e-64e2bca6a1c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171506291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.4171506291
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3158785288
Short name T689
Test name
Test status
Simulation time 96699868 ps
CPU time 2.9 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:31 PM PDT 24
Peak memory 199440 kb
Host smart-1d445aa0-eb0a-4c47-9fbc-f201eda50f9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158785288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3158785288
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.4225914421
Short name T680
Test name
Test status
Simulation time 197950779 ps
CPU time 2.4 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 199464 kb
Host smart-cefa0a57-7a5e-4490-8305-e779029ef129
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225914421 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.4225914421
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.3221618951
Short name T612
Test name
Test status
Simulation time 30728266 ps
CPU time 0.72 seconds
Started Jun 11 01:48:26 PM PDT 24
Finished Jun 11 01:48:29 PM PDT 24
Peak memory 197668 kb
Host smart-b529f429-3c89-4da6-a8a5-83f41fd079f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221618951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.3221618951
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.2179757917
Short name T722
Test name
Test status
Simulation time 22190438 ps
CPU time 0.61 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 194200 kb
Host smart-3f3f9655-ea92-4bb7-952e-10147909b098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179757917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.2179757917
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3075008758
Short name T40
Test name
Test status
Simulation time 517216103 ps
CPU time 1.12 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 199416 kb
Host smart-68b414c4-084c-4f10-a510-4c2c7e19a19b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075008758 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3075008758
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.151328963
Short name T637
Test name
Test status
Simulation time 61755851 ps
CPU time 1.51 seconds
Started Jun 11 01:48:22 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 199448 kb
Host smart-61421ca2-cecf-49e8-bb68-eeab7d8e0305
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151328963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.151328963
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3939489580
Short name T111
Test name
Test status
Simulation time 136502359 ps
CPU time 4.04 seconds
Started Jun 11 01:48:25 PM PDT 24
Finished Jun 11 01:48:30 PM PDT 24
Peak memory 199376 kb
Host smart-c1e0d7cf-84cc-4bf3-b30c-addb5bcc2147
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939489580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3939489580
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1545624886
Short name T41
Test name
Test status
Simulation time 68251641 ps
CPU time 1.2 seconds
Started Jun 11 01:48:24 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 199276 kb
Host smart-b3aa39b1-189f-4f8e-a0eb-ff9570cfb68a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545624886 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1545624886
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4060576653
Short name T79
Test name
Test status
Simulation time 16387406 ps
CPU time 0.8 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 198300 kb
Host smart-e5ed958d-e688-4830-8de3-d696e2bddc6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060576653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.4060576653
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2215485394
Short name T655
Test name
Test status
Simulation time 28454082 ps
CPU time 0.57 seconds
Started Jun 11 01:48:22 PM PDT 24
Finished Jun 11 01:48:24 PM PDT 24
Peak memory 194244 kb
Host smart-e11cf9fa-d126-41e9-bd84-067f724ad667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215485394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2215485394
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2181186442
Short name T593
Test name
Test status
Simulation time 699683941 ps
CPU time 2.5 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 199416 kb
Host smart-2703909e-d735-4642-91fa-41fe994714c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181186442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2181186442
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.3524592408
Short name T63
Test name
Test status
Simulation time 235531009 ps
CPU time 3.5 seconds
Started Jun 11 01:48:23 PM PDT 24
Finished Jun 11 01:48:27 PM PDT 24
Peak memory 199456 kb
Host smart-33bfefa4-4a69-4cfb-9699-6b543a1a1d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524592408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.3524592408
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1429790014
Short name T114
Test name
Test status
Simulation time 154620955 ps
CPU time 3.22 seconds
Started Jun 11 01:48:21 PM PDT 24
Finished Jun 11 01:48:25 PM PDT 24
Peak memory 199304 kb
Host smart-b74dfd98-e010-45e7-923a-b995f9fc20c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429790014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1429790014
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.4097841826
Short name T238
Test name
Test status
Simulation time 13474922 ps
CPU time 0.6 seconds
Started Jun 11 02:15:22 PM PDT 24
Finished Jun 11 02:15:25 PM PDT 24
Peak memory 196368 kb
Host smart-9f4db03d-c7b5-4f7e-9388-66baa3f3272d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097841826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.4097841826
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.301836301
Short name T443
Test name
Test status
Simulation time 805432746 ps
CPU time 16.36 seconds
Started Jun 11 02:15:26 PM PDT 24
Finished Jun 11 02:15:43 PM PDT 24
Peak memory 208636 kb
Host smart-c15120f1-cfba-4732-8ec6-42aa97a184fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=301836301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.301836301
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1406996983
Short name T92
Test name
Test status
Simulation time 624091908 ps
CPU time 35.06 seconds
Started Jun 11 02:15:19 PM PDT 24
Finished Jun 11 02:15:56 PM PDT 24
Peak memory 200440 kb
Host smart-e225ce48-2fb0-48ca-a409-a908eaa5c9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406996983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1406996983
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2154059030
Short name T475
Test name
Test status
Simulation time 2143835213 ps
CPU time 79.76 seconds
Started Jun 11 02:15:21 PM PDT 24
Finished Jun 11 02:16:43 PM PDT 24
Peak memory 328956 kb
Host smart-81de908a-5900-49cc-b693-69c9d294ccd4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2154059030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2154059030
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.2404623339
Short name T68
Test name
Test status
Simulation time 111615793526 ps
CPU time 145.54 seconds
Started Jun 11 02:15:30 PM PDT 24
Finished Jun 11 02:17:56 PM PDT 24
Peak memory 200544 kb
Host smart-8d3740f6-4695-4203-ad07-3f7127e780a2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404623339 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2404623339
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.1706597642
Short name T322
Test name
Test status
Simulation time 326504349 ps
CPU time 5.08 seconds
Started Jun 11 02:15:20 PM PDT 24
Finished Jun 11 02:15:27 PM PDT 24
Peak memory 200440 kb
Host smart-96b6930f-b4c0-40c6-83ff-673708009eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706597642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.1706597642
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_smoke.2638385032
Short name T382
Test name
Test status
Simulation time 176287766 ps
CPU time 6 seconds
Started Jun 11 02:15:22 PM PDT 24
Finished Jun 11 02:15:30 PM PDT 24
Peak memory 200480 kb
Host smart-d104ca8e-7c21-4238-b44b-27a5c6ed41e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638385032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2638385032
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.2337496020
Short name T293
Test name
Test status
Simulation time 10429376692 ps
CPU time 133.72 seconds
Started Jun 11 02:15:19 PM PDT 24
Finished Jun 11 02:17:35 PM PDT 24
Peak memory 200564 kb
Host smart-5eb809a3-4485-4de6-bcca-8e0e6af9ea83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337496020 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.2337496020
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.4104770795
Short name T289
Test name
Test status
Simulation time 61940538 ps
CPU time 1.25 seconds
Started Jun 11 02:15:21 PM PDT 24
Finished Jun 11 02:15:25 PM PDT 24
Peak memory 200356 kb
Host smart-14a2b79e-5bee-47b8-b210-e82be194f6a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104770795 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.4104770795
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3525258560
Short name T217
Test name
Test status
Simulation time 7934802330 ps
CPU time 434.08 seconds
Started Jun 11 02:15:19 PM PDT 24
Finished Jun 11 02:22:35 PM PDT 24
Peak memory 200484 kb
Host smart-2559bb6a-4449-4583-93fc-126953f0e344
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525258560 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3525258560
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2008921306
Short name T431
Test name
Test status
Simulation time 183958949 ps
CPU time 3.94 seconds
Started Jun 11 02:15:20 PM PDT 24
Finished Jun 11 02:15:27 PM PDT 24
Peak memory 200564 kb
Host smart-0060f5e4-8f87-4dff-976d-90d91cbe02af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008921306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2008921306
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2842353282
Short name T435
Test name
Test status
Simulation time 20755348 ps
CPU time 0.58 seconds
Started Jun 11 02:15:24 PM PDT 24
Finished Jun 11 02:15:26 PM PDT 24
Peak memory 196420 kb
Host smart-cb768323-4228-459c-b7fb-4216b4d7d5e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842353282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2842353282
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.2457755423
Short name T14
Test name
Test status
Simulation time 1092373884 ps
CPU time 10.46 seconds
Started Jun 11 02:15:18 PM PDT 24
Finished Jun 11 02:15:31 PM PDT 24
Peak memory 208540 kb
Host smart-bbe47335-e86d-49ad-a945-2fd6ebd82eb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2457755423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.2457755423
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2690160546
Short name T163
Test name
Test status
Simulation time 1641325190 ps
CPU time 22.14 seconds
Started Jun 11 02:15:20 PM PDT 24
Finished Jun 11 02:15:44 PM PDT 24
Peak memory 200452 kb
Host smart-79097cb0-4a90-491f-a632-d4ccf2ae25a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690160546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2690160546
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.2816571996
Short name T105
Test name
Test status
Simulation time 6778290748 ps
CPU time 740.25 seconds
Started Jun 11 02:15:21 PM PDT 24
Finished Jun 11 02:27:44 PM PDT 24
Peak memory 674816 kb
Host smart-b3349c1f-f5e1-41cf-b3a6-253bb1be9d0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2816571996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.2816571996
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.1367077566
Short name T334
Test name
Test status
Simulation time 342673648 ps
CPU time 18.61 seconds
Started Jun 11 02:15:18 PM PDT 24
Finished Jun 11 02:15:38 PM PDT 24
Peak memory 200400 kb
Host smart-7b54ab26-43b1-43fa-95d6-ecc7ea8e237b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367077566 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.1367077566
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.1363672218
Short name T396
Test name
Test status
Simulation time 10061463423 ps
CPU time 68.7 seconds
Started Jun 11 02:15:19 PM PDT 24
Finished Jun 11 02:16:30 PM PDT 24
Peak memory 200548 kb
Host smart-0047cb43-7d27-4f0a-8299-39d04b7263af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363672218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.1363672218
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.2707262334
Short name T411
Test name
Test status
Simulation time 90418934 ps
CPU time 2.94 seconds
Started Jun 11 02:15:20 PM PDT 24
Finished Jun 11 02:15:24 PM PDT 24
Peak memory 200428 kb
Host smart-5849c32a-7116-40e1-853c-defedb199363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707262334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2707262334
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.74649640
Short name T350
Test name
Test status
Simulation time 45967828 ps
CPU time 1.09 seconds
Started Jun 11 02:15:20 PM PDT 24
Finished Jun 11 02:15:23 PM PDT 24
Peak memory 200336 kb
Host smart-1611bf58-7d61-49bf-acea-7041305aaf43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74649640 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.hmac_test_hmac_vectors.74649640
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.3311674384
Short name T483
Test name
Test status
Simulation time 24607101205 ps
CPU time 452 seconds
Started Jun 11 02:15:20 PM PDT 24
Finished Jun 11 02:22:54 PM PDT 24
Peak memory 200444 kb
Host smart-5abb3218-01af-4519-86b7-c72eacb746d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311674384 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.3311674384
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.9976357
Short name T188
Test name
Test status
Simulation time 2277411742 ps
CPU time 33.87 seconds
Started Jun 11 02:15:22 PM PDT 24
Finished Jun 11 02:15:58 PM PDT 24
Peak memory 200400 kb
Host smart-4cdcd091-a800-4438-a6d0-f7f5648f1186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9976357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.9976357
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2004673782
Short name T522
Test name
Test status
Simulation time 17656280 ps
CPU time 0.59 seconds
Started Jun 11 02:15:44 PM PDT 24
Finished Jun 11 02:15:47 PM PDT 24
Peak memory 196276 kb
Host smart-226bdc64-f52f-4d25-b684-432a791e6d56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004673782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2004673782
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2582698674
Short name T206
Test name
Test status
Simulation time 3872724165 ps
CPU time 47.19 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:16:35 PM PDT 24
Peak memory 228028 kb
Host smart-91340967-62c3-48ef-a6cd-2e8dc34c005c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582698674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2582698674
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.1072527797
Short name T437
Test name
Test status
Simulation time 6790811794 ps
CPU time 33.59 seconds
Started Jun 11 02:15:49 PM PDT 24
Finished Jun 11 02:16:24 PM PDT 24
Peak memory 200476 kb
Host smart-fb82fc6b-d939-4db0-954e-c59ca0a9419d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072527797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.1072527797
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_error.2928533224
Short name T167
Test name
Test status
Simulation time 31373210489 ps
CPU time 159.85 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:18:26 PM PDT 24
Peak memory 200540 kb
Host smart-fa75d240-1353-4906-bc0b-0f7769f92a62
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928533224 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.2928533224
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.1844570372
Short name T448
Test name
Test status
Simulation time 1853961136 ps
CPU time 35.82 seconds
Started Jun 11 02:15:50 PM PDT 24
Finished Jun 11 02:16:27 PM PDT 24
Peak memory 200656 kb
Host smart-c47820fe-cb0b-45cc-a41c-be47d393c5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844570372 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.1844570372
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3069368638
Short name T369
Test name
Test status
Simulation time 382617418 ps
CPU time 2.1 seconds
Started Jun 11 02:15:43 PM PDT 24
Finished Jun 11 02:15:47 PM PDT 24
Peak memory 200488 kb
Host smart-b9d585de-f15d-45e9-9d5e-114da35607d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069368638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3069368638
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.3439585255
Short name T60
Test name
Test status
Simulation time 385575364261 ps
CPU time 2686.19 seconds
Started Jun 11 02:15:44 PM PDT 24
Finished Jun 11 03:00:32 PM PDT 24
Peak memory 817332 kb
Host smart-ec13a79b-13b8-4db7-b4de-9dde7d71959a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439585255 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.3439585255
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.2748820346
Short name T438
Test name
Test status
Simulation time 215976777 ps
CPU time 1.09 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:15:49 PM PDT 24
Peak memory 200452 kb
Host smart-760c8364-8744-46d5-b9fb-7f5621e2ba2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748820346 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.2748820346
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.618543144
Short name T275
Test name
Test status
Simulation time 8010491189 ps
CPU time 436.51 seconds
Started Jun 11 02:15:44 PM PDT 24
Finished Jun 11 02:23:03 PM PDT 24
Peak memory 200500 kb
Host smart-bc811dc5-1c2f-48da-9af7-cea9e643eef6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618543144 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.618543144
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.976339721
Short name T147
Test name
Test status
Simulation time 48097280257 ps
CPU time 112.57 seconds
Started Jun 11 02:15:42 PM PDT 24
Finished Jun 11 02:17:36 PM PDT 24
Peak memory 200516 kb
Host smart-8ec00188-4ae6-4b6a-a9bd-58ca07331e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976339721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.976339721
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1708379123
Short name T343
Test name
Test status
Simulation time 14999833 ps
CPU time 0.63 seconds
Started Jun 11 02:15:50 PM PDT 24
Finished Jun 11 02:15:52 PM PDT 24
Peak memory 197296 kb
Host smart-1a18393b-c377-4d12-9cc0-7790836ef2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708379123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1708379123
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1982610414
Short name T176
Test name
Test status
Simulation time 445822296 ps
CPU time 20.87 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:16:07 PM PDT 24
Peak memory 216384 kb
Host smart-c271076d-a2fa-4fe1-a026-c55083ae8e44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1982610414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1982610414
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.2740060992
Short name T259
Test name
Test status
Simulation time 356176737 ps
CPU time 2.26 seconds
Started Jun 11 02:15:47 PM PDT 24
Finished Jun 11 02:15:51 PM PDT 24
Peak memory 200400 kb
Host smart-3511c9d7-bf7f-4c4f-abef-9a44f13d3eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740060992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.2740060992
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.3288147575
Short name T590
Test name
Test status
Simulation time 2836881598 ps
CPU time 635.35 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:26:24 PM PDT 24
Peak memory 713032 kb
Host smart-c257b34c-a4cb-42fa-ba47-11af7443f94f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3288147575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.3288147575
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.777498962
Short name T427
Test name
Test status
Simulation time 27321435385 ps
CPU time 126.55 seconds
Started Jun 11 02:16:01 PM PDT 24
Finished Jun 11 02:18:10 PM PDT 24
Peak memory 200544 kb
Host smart-752b0f1e-35f1-4ce4-924b-50fc1c7c8e7b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777498962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.777498962
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.3681598551
Short name T278
Test name
Test status
Simulation time 18523100523 ps
CPU time 67.62 seconds
Started Jun 11 02:15:43 PM PDT 24
Finished Jun 11 02:16:52 PM PDT 24
Peak memory 200384 kb
Host smart-f152bbfd-a3fa-49d6-8c53-60ad666612d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681598551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.3681598551
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2499026619
Short name T203
Test name
Test status
Simulation time 855182080 ps
CPU time 7.95 seconds
Started Jun 11 02:15:44 PM PDT 24
Finished Jun 11 02:15:54 PM PDT 24
Peak memory 200424 kb
Host smart-cebdada2-6777-4570-823c-a2d5d1cba7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499026619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2499026619
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.4292137309
Short name T462
Test name
Test status
Simulation time 38125878963 ps
CPU time 2268.93 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:53:36 PM PDT 24
Peak memory 235272 kb
Host smart-79f58008-391c-4014-a61f-c2331383c93e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292137309 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.4292137309
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.2162263509
Short name T305
Test name
Test status
Simulation time 58752073 ps
CPU time 1.13 seconds
Started Jun 11 02:15:48 PM PDT 24
Finished Jun 11 02:15:50 PM PDT 24
Peak memory 200224 kb
Host smart-048730b6-d860-4490-8e96-900822612560
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162263509 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.2162263509
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.4076110115
Short name T236
Test name
Test status
Simulation time 24417288555 ps
CPU time 425.58 seconds
Started Jun 11 02:15:44 PM PDT 24
Finished Jun 11 02:22:51 PM PDT 24
Peak memory 200492 kb
Host smart-6aecfb23-cc65-4995-9595-20d96e3abdf5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076110115 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.4076110115
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.3792805524
Short name T55
Test name
Test status
Simulation time 291959303 ps
CPU time 9.16 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:15:56 PM PDT 24
Peak memory 200476 kb
Host smart-6c51d15c-9f01-4b88-8480-184168293c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792805524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.3792805524
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3398023477
Short name T314
Test name
Test status
Simulation time 18732247 ps
CPU time 0.58 seconds
Started Jun 11 02:15:54 PM PDT 24
Finished Jun 11 02:15:55 PM PDT 24
Peak memory 196384 kb
Host smart-5f937ffc-afd2-4188-88e7-e372d73a405b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398023477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3398023477
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.3470944685
Short name T250
Test name
Test status
Simulation time 2865993719 ps
CPU time 34.76 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:16:31 PM PDT 24
Peak memory 208688 kb
Host smart-551f2593-31f0-4456-88f5-37d2d3a7789f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3470944685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.3470944685
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.3315487762
Short name T292
Test name
Test status
Simulation time 831724556 ps
CPU time 15.93 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:16:04 PM PDT 24
Peak memory 200448 kb
Host smart-f8d88a45-fe7c-4fd6-9003-abe20c5588e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315487762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.3315487762
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2519587718
Short name T254
Test name
Test status
Simulation time 560359187 ps
CPU time 32.52 seconds
Started Jun 11 02:15:48 PM PDT 24
Finished Jun 11 02:16:22 PM PDT 24
Peak memory 240544 kb
Host smart-9a074b83-265f-47d4-a069-61235973aa9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519587718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2519587718
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.232964079
Short name T145
Test name
Test status
Simulation time 70278681052 ps
CPU time 129.03 seconds
Started Jun 11 02:15:49 PM PDT 24
Finished Jun 11 02:17:59 PM PDT 24
Peak memory 200504 kb
Host smart-1979518a-9b00-429c-9e50-6c8edbfd2994
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232964079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.232964079
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.1937408233
Short name T398
Test name
Test status
Simulation time 4805899007 ps
CPU time 36.85 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:16:25 PM PDT 24
Peak memory 200472 kb
Host smart-c34b3dde-d0be-4e3c-8d88-6b6660211ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937408233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.1937408233
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.874138556
Short name T402
Test name
Test status
Simulation time 1183514653 ps
CPU time 9.46 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:15:57 PM PDT 24
Peak memory 200384 kb
Host smart-098729e1-bed3-4884-bd8a-3d271cbce1dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874138556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.874138556
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.1647338937
Short name T11
Test name
Test status
Simulation time 429996136686 ps
CPU time 1081.24 seconds
Started Jun 11 02:15:47 PM PDT 24
Finished Jun 11 02:33:50 PM PDT 24
Peak memory 200384 kb
Host smart-f572daac-a21a-4068-a258-d9873167ba5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647338937 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.1647338937
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.659236130
Short name T433
Test name
Test status
Simulation time 35152596 ps
CPU time 1.07 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:15:48 PM PDT 24
Peak memory 200248 kb
Host smart-8514854f-31c8-470b-af85-e6e16b125372
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659236130 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.659236130
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.2729596549
Short name T149
Test name
Test status
Simulation time 162211004249 ps
CPU time 527.26 seconds
Started Jun 11 02:15:47 PM PDT 24
Finished Jun 11 02:24:36 PM PDT 24
Peak memory 200448 kb
Host smart-d7565337-cdb2-46b6-9e31-4ecdef9b6902
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729596549 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.2729596549
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.999194819
Short name T417
Test name
Test status
Simulation time 16012033891 ps
CPU time 63.8 seconds
Started Jun 11 02:15:47 PM PDT 24
Finished Jun 11 02:16:52 PM PDT 24
Peak memory 200488 kb
Host smart-0bffa87b-8e2f-46b1-a805-1a2c7c35c672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999194819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.999194819
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2495865668
Short name T27
Test name
Test status
Simulation time 4178429068 ps
CPU time 52.51 seconds
Started Jun 11 02:15:47 PM PDT 24
Finished Jun 11 02:16:41 PM PDT 24
Peak memory 246384 kb
Host smart-4261bd73-507c-4197-bbe8-824b675ce64c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2495865668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2495865668
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2835386948
Short name T515
Test name
Test status
Simulation time 55006384 ps
CPU time 0.9 seconds
Started Jun 11 02:15:54 PM PDT 24
Finished Jun 11 02:15:55 PM PDT 24
Peak memory 200196 kb
Host smart-52bbf4fd-b7da-459b-8780-a110705da42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835386948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2835386948
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.613714699
Short name T568
Test name
Test status
Simulation time 3545524330 ps
CPU time 1020.57 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:32:48 PM PDT 24
Peak memory 758960 kb
Host smart-73de96a0-f383-4c60-b559-50c693339e7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613714699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.613714699
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.560167746
Short name T536
Test name
Test status
Simulation time 3127975503 ps
CPU time 42.02 seconds
Started Jun 11 02:15:47 PM PDT 24
Finished Jun 11 02:16:31 PM PDT 24
Peak memory 200516 kb
Host smart-be6afdf9-bea4-412f-973b-65a15fd1b287
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560167746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.560167746
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.4095295684
Short name T413
Test name
Test status
Simulation time 2285248549 ps
CPU time 42.78 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:16:39 PM PDT 24
Peak memory 200500 kb
Host smart-a765514d-da03-4404-99d1-9d427f66fb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095295684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.4095295684
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2453323653
Short name T479
Test name
Test status
Simulation time 98023961 ps
CPU time 2.02 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:15:50 PM PDT 24
Peak memory 200412 kb
Host smart-033fe256-c382-4faa-a28d-5868c8e786ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453323653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2453323653
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.4071261603
Short name T454
Test name
Test status
Simulation time 5729695091 ps
CPU time 639.5 seconds
Started Jun 11 02:15:47 PM PDT 24
Finished Jun 11 02:26:29 PM PDT 24
Peak memory 626888 kb
Host smart-beacc676-7539-4a65-a0e5-77be352ede17
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071261603 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.4071261603
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1934042956
Short name T424
Test name
Test status
Simulation time 114428011 ps
CPU time 1.32 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:15:49 PM PDT 24
Peak memory 200344 kb
Host smart-55acc2be-7678-483b-9279-0b1bc5f4dc53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934042956 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.1934042956
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3477861432
Short name T129
Test name
Test status
Simulation time 113316530015 ps
CPU time 510.23 seconds
Started Jun 11 02:15:49 PM PDT 24
Finished Jun 11 02:24:20 PM PDT 24
Peak memory 200412 kb
Host smart-8b6142ce-481a-48b1-8969-7c80137aa3bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477861432 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3477861432
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3524639723
Short name T269
Test name
Test status
Simulation time 17169455 ps
CPU time 0.61 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:16:03 PM PDT 24
Peak memory 197092 kb
Host smart-5626b229-349b-4b43-a118-49d876a8a091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524639723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3524639723
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.46739323
Short name T457
Test name
Test status
Simulation time 1064411747 ps
CPU time 48.99 seconds
Started Jun 11 02:15:48 PM PDT 24
Finished Jun 11 02:16:39 PM PDT 24
Peak memory 241724 kb
Host smart-aac4838e-fd39-4b94-92ec-3010859805d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46739323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.46739323
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3961142296
Short name T364
Test name
Test status
Simulation time 5854057885 ps
CPU time 18.65 seconds
Started Jun 11 02:15:49 PM PDT 24
Finished Jun 11 02:16:09 PM PDT 24
Peak memory 200516 kb
Host smart-5cb0d7be-ecb5-4650-979e-ee25919af9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961142296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3961142296
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2678542112
Short name T484
Test name
Test status
Simulation time 1260379278 ps
CPU time 266.78 seconds
Started Jun 11 02:15:47 PM PDT 24
Finished Jun 11 02:20:16 PM PDT 24
Peak memory 507032 kb
Host smart-40dda6f6-04de-46b2-b235-0018f9411633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2678542112 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2678542112
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.707275698
Short name T309
Test name
Test status
Simulation time 40820643839 ps
CPU time 145.9 seconds
Started Jun 11 02:15:48 PM PDT 24
Finished Jun 11 02:18:16 PM PDT 24
Peak memory 200572 kb
Host smart-2b20c151-6e8a-4970-ab1b-d5f5800d0910
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707275698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.707275698
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1859430509
Short name T47
Test name
Test status
Simulation time 95375281991 ps
CPU time 158.18 seconds
Started Jun 11 02:15:48 PM PDT 24
Finished Jun 11 02:18:28 PM PDT 24
Peak memory 200468 kb
Host smart-374ce129-8c03-40eb-999a-2d3e5babb82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859430509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1859430509
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.724856848
Short name T519
Test name
Test status
Simulation time 151883687 ps
CPU time 5.02 seconds
Started Jun 11 02:15:49 PM PDT 24
Finished Jun 11 02:15:55 PM PDT 24
Peak memory 200488 kb
Host smart-166ae0dd-9081-43fc-b000-dfed73a0fa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724856848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.724856848
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.365437136
Short name T194
Test name
Test status
Simulation time 25185801648 ps
CPU time 412.97 seconds
Started Jun 11 02:15:51 PM PDT 24
Finished Jun 11 02:22:45 PM PDT 24
Peak memory 215836 kb
Host smart-ac25eaf0-10f7-40d1-9b39-323685ccef99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365437136 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.365437136
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.582693491
Short name T192
Test name
Test status
Simulation time 123397078 ps
CPU time 1.24 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:15:50 PM PDT 24
Peak memory 200372 kb
Host smart-84a11c37-3656-4c6f-8799-f60b6d247f4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582693491 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.hmac_test_hmac_vectors.582693491
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.1930756830
Short name T399
Test name
Test status
Simulation time 16561030945 ps
CPU time 463.27 seconds
Started Jun 11 02:15:48 PM PDT 24
Finished Jun 11 02:23:33 PM PDT 24
Peak memory 200412 kb
Host smart-0ea9d816-7008-489e-8fe4-d84a8d7d0f48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930756830 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.1930756830
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.88858130
Short name T221
Test name
Test status
Simulation time 8786975678 ps
CPU time 78.92 seconds
Started Jun 11 02:15:47 PM PDT 24
Finished Jun 11 02:17:08 PM PDT 24
Peak memory 200520 kb
Host smart-86d93766-f5f9-45ae-9b92-acec61e9d35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88858130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.88858130
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/149.hmac_stress_all_with_rand_reset.2651898169
Short name T19
Test name
Test status
Simulation time 72313533380 ps
CPU time 1507.57 seconds
Started Jun 11 02:17:53 PM PDT 24
Finished Jun 11 02:43:02 PM PDT 24
Peak memory 406744 kb
Host smart-86b22cee-532b-48c1-881e-a583b70a1097
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651898169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 149.hmac_stress_all_with_rand_reset.2651898169
Directory /workspace/149.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.4239697508
Short name T229
Test name
Test status
Simulation time 12332939 ps
CPU time 0.62 seconds
Started Jun 11 02:15:54 PM PDT 24
Finished Jun 11 02:15:56 PM PDT 24
Peak memory 195252 kb
Host smart-f034be6f-64c5-4dbb-8587-190b8694858f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239697508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.4239697508
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.803605411
Short name T450
Test name
Test status
Simulation time 1666495794 ps
CPU time 12.13 seconds
Started Jun 11 02:16:08 PM PDT 24
Finished Jun 11 02:16:22 PM PDT 24
Peak memory 208512 kb
Host smart-9384e089-dd7d-489a-87dd-176b12e69acb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=803605411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.803605411
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1040216708
Short name T524
Test name
Test status
Simulation time 5419301973 ps
CPU time 69.73 seconds
Started Jun 11 02:16:02 PM PDT 24
Finished Jun 11 02:17:14 PM PDT 24
Peak memory 200480 kb
Host smart-e55c5506-45a2-43a0-9206-bbf45bc7ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040216708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1040216708
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3316220276
Short name T211
Test name
Test status
Simulation time 13325210875 ps
CPU time 979.11 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:32:16 PM PDT 24
Peak memory 671204 kb
Host smart-87d320a4-3ff4-4e38-a370-bcba41d7886e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3316220276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3316220276
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.3014530579
Short name T456
Test name
Test status
Simulation time 36238189543 ps
CPU time 97.38 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:17:35 PM PDT 24
Peak memory 200456 kb
Host smart-c9553343-076e-43a7-bf4d-e5f5d98f4f4f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014530579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.3014530579
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.811670302
Short name T553
Test name
Test status
Simulation time 19668812755 ps
CPU time 89.47 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:17:30 PM PDT 24
Peak memory 200480 kb
Host smart-5fbe5d03-9bac-4bca-bd53-fa99246f5f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811670302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.811670302
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.3011906391
Short name T7
Test name
Test status
Simulation time 220251033 ps
CPU time 3.79 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:16:02 PM PDT 24
Peak memory 200420 kb
Host smart-8a593104-fa76-4c39-9972-15d88c438c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011906391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.3011906391
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3676310094
Short name T582
Test name
Test status
Simulation time 12369633826 ps
CPU time 172.22 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:18:49 PM PDT 24
Peak memory 200548 kb
Host smart-f3be79c9-3e62-46c7-b4b6-71b1876454d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676310094 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3676310094
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2692627017
Short name T418
Test name
Test status
Simulation time 34885150 ps
CPU time 1.32 seconds
Started Jun 11 02:15:58 PM PDT 24
Finished Jun 11 02:16:02 PM PDT 24
Peak memory 200392 kb
Host smart-14b87c35-2167-45b9-8884-c463cbd09254
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692627017 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.2692627017
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.1392959707
Short name T358
Test name
Test status
Simulation time 25982764327 ps
CPU time 467.72 seconds
Started Jun 11 02:15:58 PM PDT 24
Finished Jun 11 02:23:48 PM PDT 24
Peak memory 200516 kb
Host smart-32542570-994f-46de-9c77-0334fd1eb5e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392959707 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.1392959707
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.2855346814
Short name T410
Test name
Test status
Simulation time 262971711 ps
CPU time 11.69 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:11 PM PDT 24
Peak memory 200476 kb
Host smart-0b669c25-c981-4fad-8561-994e912cfa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855346814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.2855346814
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.3677056276
Short name T357
Test name
Test status
Simulation time 14139312 ps
CPU time 0.59 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:15:59 PM PDT 24
Peak memory 196420 kb
Host smart-77b2d209-646c-4b8a-9431-a77551f5ef36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677056276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.3677056276
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.1515896875
Short name T308
Test name
Test status
Simulation time 133988398 ps
CPU time 8.47 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:08 PM PDT 24
Peak memory 216756 kb
Host smart-24eab65b-58c5-4759-9fcd-993772ab1335
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1515896875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.1515896875
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.4094190098
Short name T562
Test name
Test status
Simulation time 781934379 ps
CPU time 20.64 seconds
Started Jun 11 02:15:54 PM PDT 24
Finished Jun 11 02:16:16 PM PDT 24
Peak memory 200392 kb
Host smart-2cde74e7-8c07-4349-869c-f62c3a995dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094190098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4094190098
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.685412423
Short name T351
Test name
Test status
Simulation time 15559882762 ps
CPU time 1060.42 seconds
Started Jun 11 02:15:53 PM PDT 24
Finished Jun 11 02:33:34 PM PDT 24
Peak memory 762636 kb
Host smart-99ef57cd-4022-4ffa-8f88-12c76f1926b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=685412423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.685412423
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1739553994
Short name T160
Test name
Test status
Simulation time 20029375569 ps
CPU time 187.27 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:19:04 PM PDT 24
Peak memory 200480 kb
Host smart-06948df4-368c-42af-bc6f-506bbc2bbdfa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739553994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1739553994
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3515062531
Short name T116
Test name
Test status
Simulation time 463090544 ps
CPU time 23.06 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:22 PM PDT 24
Peak memory 200456 kb
Host smart-f7ed84cb-21f5-4339-98e2-3f504861306c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515062531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3515062531
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.1486792441
Short name T117
Test name
Test status
Simulation time 48918253 ps
CPU time 1.28 seconds
Started Jun 11 02:15:54 PM PDT 24
Finished Jun 11 02:15:56 PM PDT 24
Peak memory 200456 kb
Host smart-7ff077c6-7f26-41bc-96ed-2c717e19a971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486792441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.1486792441
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1746009560
Short name T187
Test name
Test status
Simulation time 46430525214 ps
CPU time 1137.04 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:34:59 PM PDT 24
Peak memory 518164 kb
Host smart-6b66e3bd-3936-46d8-ba9c-205a42cc13ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746009560 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1746009560
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2889880277
Short name T359
Test name
Test status
Simulation time 57244851 ps
CPU time 1.31 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:00 PM PDT 24
Peak memory 200472 kb
Host smart-f16b7ae0-7f96-4f8b-a54b-42de8d13ee91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889880277 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.2889880277
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.2937230727
Short name T318
Test name
Test status
Simulation time 28425018490 ps
CPU time 506.39 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:24:24 PM PDT 24
Peak memory 200448 kb
Host smart-35fcdd05-85e4-4d82-a7bf-65662aa9e9de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937230727 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.2937230727
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.4100180053
Short name T138
Test name
Test status
Simulation time 10192770440 ps
CPU time 44.29 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:16:42 PM PDT 24
Peak memory 200464 kb
Host smart-f2fb9e28-f708-43ca-aa70-69a61bdae4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100180053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.4100180053
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3328131404
Short name T240
Test name
Test status
Simulation time 10687830 ps
CPU time 0.56 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:15:57 PM PDT 24
Peak memory 195368 kb
Host smart-5803d290-59ef-4d28-83ce-c6629d6b48bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328131404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3328131404
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1615924212
Short name T383
Test name
Test status
Simulation time 6133873042 ps
CPU time 76.7 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:17:14 PM PDT 24
Peak memory 235164 kb
Host smart-0ee36d5f-2f70-4d55-ac0c-ba1500571a1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1615924212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1615924212
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.2397255747
Short name T311
Test name
Test status
Simulation time 16823367927 ps
CPU time 63 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:17:02 PM PDT 24
Peak memory 200460 kb
Host smart-44c2062c-6c37-431f-8111-7a40454a3c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397255747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.2397255747
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.748224711
Short name T497
Test name
Test status
Simulation time 4246356673 ps
CPU time 571.24 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:25:28 PM PDT 24
Peak memory 734252 kb
Host smart-7566ce59-df59-4753-99cc-1c0ec820f957
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=748224711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.748224711
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.4217162270
Short name T298
Test name
Test status
Simulation time 12167946865 ps
CPU time 85.15 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:17:22 PM PDT 24
Peak memory 200472 kb
Host smart-74c24105-4646-4537-be30-5796c91ad23e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217162270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.4217162270
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3205285901
Short name T166
Test name
Test status
Simulation time 346439528 ps
CPU time 6.44 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:16:05 PM PDT 24
Peak memory 200496 kb
Host smart-1432bfc2-effc-4236-837b-2c9884a9e84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205285901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3205285901
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2793789921
Short name T75
Test name
Test status
Simulation time 417634156 ps
CPU time 3.89 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:16:02 PM PDT 24
Peak memory 200396 kb
Host smart-14681698-cab5-41af-8bb3-029a6f8b2aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793789921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2793789921
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.264674711
Short name T58
Test name
Test status
Simulation time 172565666798 ps
CPU time 540.35 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:24:57 PM PDT 24
Peak memory 237328 kb
Host smart-d1eb4e02-2a48-4f8b-be8e-97e8211d2b19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264674711 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.264674711
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.984179128
Short name T200
Test name
Test status
Simulation time 99654373 ps
CPU time 1.09 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:15:59 PM PDT 24
Peak memory 199648 kb
Host smart-d717750f-e5f1-480a-b4e8-9ca9d6f8d7ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984179128 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.hmac_test_hmac_vectors.984179128
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.455884122
Short name T284
Test name
Test status
Simulation time 30642818773 ps
CPU time 549.08 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:25:07 PM PDT 24
Peak memory 200368 kb
Host smart-5dcb4864-b6c6-492a-8066-df66ffd2a5c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455884122 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.455884122
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.252586287
Short name T181
Test name
Test status
Simulation time 8449789678 ps
CPU time 83.12 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:17:21 PM PDT 24
Peak memory 200420 kb
Host smart-9cec72ef-deea-42de-b8fd-cf4f16aa130e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252586287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.252586287
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.101402645
Short name T164
Test name
Test status
Simulation time 20018601 ps
CPU time 0.65 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:00 PM PDT 24
Peak memory 196040 kb
Host smart-6bf93bde-07aa-4f97-ad8e-94368398dea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101402645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.101402645
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2773678084
Short name T460
Test name
Test status
Simulation time 425324580 ps
CPU time 7.96 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:16:06 PM PDT 24
Peak memory 232784 kb
Host smart-b81504ca-a0bb-4a5b-9789-b7e438b96a4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2773678084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2773678084
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.2889780295
Short name T376
Test name
Test status
Simulation time 17190842445 ps
CPU time 49.63 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:16:46 PM PDT 24
Peak memory 200388 kb
Host smart-8ba2c88c-43ae-46a0-89b9-a3edeb2ca72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889780295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.2889780295
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.2207602714
Short name T577
Test name
Test status
Simulation time 4137460962 ps
CPU time 531.76 seconds
Started Jun 11 02:15:58 PM PDT 24
Finished Jun 11 02:24:52 PM PDT 24
Peak memory 646772 kb
Host smart-9d879acd-f3d2-418b-b87d-1763040a670e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2207602714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.2207602714
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2759178248
Short name T349
Test name
Test status
Simulation time 76237921082 ps
CPU time 188.57 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:19:06 PM PDT 24
Peak memory 200468 kb
Host smart-5561a196-d08b-49ad-a3f2-9fd39471f143
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759178248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2759178248
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.2644659268
Short name T132
Test name
Test status
Simulation time 18109903091 ps
CPU time 70.17 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:17:07 PM PDT 24
Peak memory 200464 kb
Host smart-d1a21352-b963-4422-a8be-3f913d1d8d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644659268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.2644659268
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3209520196
Short name T444
Test name
Test status
Simulation time 659142847 ps
CPU time 7.07 seconds
Started Jun 11 02:16:03 PM PDT 24
Finished Jun 11 02:16:12 PM PDT 24
Peak memory 200444 kb
Host smart-3c31fb63-2a28-4625-a09e-0f77b0734977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209520196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3209520196
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.3965541838
Short name T534
Test name
Test status
Simulation time 35191718541 ps
CPU time 2563.28 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:58:42 PM PDT 24
Peak memory 525724 kb
Host smart-4f470d23-2b52-45e2-b978-7b174f1f751b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965541838 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.3965541838
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.3858432301
Short name T496
Test name
Test status
Simulation time 111757320 ps
CPU time 1.19 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:15:59 PM PDT 24
Peak memory 200424 kb
Host smart-ea4fcf37-8414-410b-b482-6688478e76b2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858432301 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.3858432301
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.4113830880
Short name T521
Test name
Test status
Simulation time 107355086963 ps
CPU time 491.01 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:24:09 PM PDT 24
Peak memory 200436 kb
Host smart-b568123e-572e-4a93-8958-745ab5150c2a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113830880 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.4113830880
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.1553701879
Short name T440
Test name
Test status
Simulation time 916133617 ps
CPU time 20.95 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:16:19 PM PDT 24
Peak memory 200400 kb
Host smart-60506fed-9757-42b1-bf64-8f8785187e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553701879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.1553701879
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.469872793
Short name T469
Test name
Test status
Simulation time 19462451 ps
CPU time 0.56 seconds
Started Jun 11 02:15:58 PM PDT 24
Finished Jun 11 02:16:01 PM PDT 24
Peak memory 195380 kb
Host smart-398f7940-4366-4ad2-8f7d-196723d4c0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469872793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.469872793
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.3421768391
Short name T459
Test name
Test status
Simulation time 262046668 ps
CPU time 10.12 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:16:07 PM PDT 24
Peak memory 208640 kb
Host smart-0582e176-d05d-43c4-9b63-12f4acbe246e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421768391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.3421768391
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.1772535374
Short name T512
Test name
Test status
Simulation time 331324658 ps
CPU time 1.65 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:01 PM PDT 24
Peak memory 200324 kb
Host smart-07c8733f-c984-47cc-9986-08b89a60c43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772535374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.1772535374
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2920039355
Short name T339
Test name
Test status
Simulation time 1137572657 ps
CPU time 302.07 seconds
Started Jun 11 02:15:58 PM PDT 24
Finished Jun 11 02:21:02 PM PDT 24
Peak memory 681504 kb
Host smart-a95ef085-1c21-4cc5-9020-ca4c06496d90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920039355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2920039355
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3557275704
Short name T558
Test name
Test status
Simulation time 133318309459 ps
CPU time 205.22 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:19:27 PM PDT 24
Peak memory 200488 kb
Host smart-cf251de8-fa65-47ea-9143-41ae42ff8cb0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557275704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3557275704
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.2278741412
Short name T230
Test name
Test status
Simulation time 122010066 ps
CPU time 2.2 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:16:00 PM PDT 24
Peak memory 200448 kb
Host smart-3ef06b39-00f4-4b4d-976d-964b03bf4271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278741412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.2278741412
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.1628615359
Short name T451
Test name
Test status
Simulation time 54464561 ps
CPU time 2.09 seconds
Started Jun 11 02:16:02 PM PDT 24
Finished Jun 11 02:16:06 PM PDT 24
Peak memory 200484 kb
Host smart-d570b973-86b9-416d-8d55-6191c122814d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628615359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.1628615359
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.874422597
Short name T268
Test name
Test status
Simulation time 27745592263 ps
CPU time 527.14 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:24:46 PM PDT 24
Peak memory 239116 kb
Host smart-7489e20c-0a0c-4bf8-9176-6d18a5636b4b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874422597 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.874422597
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.3813296109
Short name T313
Test name
Test status
Simulation time 74257795 ps
CPU time 1.36 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:01 PM PDT 24
Peak memory 200368 kb
Host smart-5305e4f1-15ef-4003-9e21-9dc5a622122c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813296109 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.3813296109
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.1683149633
Short name T458
Test name
Test status
Simulation time 56976088813 ps
CPU time 503.49 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:24:23 PM PDT 24
Peak memory 200364 kb
Host smart-f247d8f3-d295-4715-8820-a0cebce897d6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683149633 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.1683149633
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.3232043664
Short name T407
Test name
Test status
Simulation time 3385904492 ps
CPU time 68.21 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:17:05 PM PDT 24
Peak memory 200532 kb
Host smart-463b85e6-5191-4af6-b2b0-09ee69672e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232043664 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.3232043664
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.256173763
Short name T328
Test name
Test status
Simulation time 13253998 ps
CPU time 0.65 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:15:33 PM PDT 24
Peak memory 195384 kb
Host smart-7b7792e4-4710-4f75-90c6-88fe5776ea68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256173763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.256173763
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2919018526
Short name T102
Test name
Test status
Simulation time 389000720 ps
CPU time 9.67 seconds
Started Jun 11 02:15:20 PM PDT 24
Finished Jun 11 02:15:33 PM PDT 24
Peak memory 200476 kb
Host smart-fd978126-4b25-4b2a-87bb-f400d899429b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2919018526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2919018526
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.431070063
Short name T505
Test name
Test status
Simulation time 11410501132 ps
CPU time 23.11 seconds
Started Jun 11 02:15:19 PM PDT 24
Finished Jun 11 02:15:44 PM PDT 24
Peak memory 200464 kb
Host smart-bfaee725-f2f3-4176-8c29-a5d367232b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431070063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.431070063
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2696579132
Short name T133
Test name
Test status
Simulation time 10916769021 ps
CPU time 853.91 seconds
Started Jun 11 02:15:20 PM PDT 24
Finished Jun 11 02:29:37 PM PDT 24
Peak memory 739404 kb
Host smart-abae0693-49e6-4b9f-81dd-5bf4c093e70d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2696579132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2696579132
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.3230126942
Short name T538
Test name
Test status
Simulation time 18516400287 ps
CPU time 128.9 seconds
Started Jun 11 02:15:22 PM PDT 24
Finished Jun 11 02:17:33 PM PDT 24
Peak memory 200432 kb
Host smart-7e419222-a658-4b11-85ef-684d6788ad3a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230126942 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.3230126942
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.4069648306
Short name T401
Test name
Test status
Simulation time 897860544 ps
CPU time 19.17 seconds
Started Jun 11 02:15:24 PM PDT 24
Finished Jun 11 02:15:45 PM PDT 24
Peak memory 200508 kb
Host smart-294f7a8a-378d-4b78-aa9a-e6b0d8fa497d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069648306 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.4069648306
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3210301395
Short name T22
Test name
Test status
Simulation time 584693590 ps
CPU time 1.34 seconds
Started Jun 11 02:15:30 PM PDT 24
Finished Jun 11 02:15:32 PM PDT 24
Peak memory 219952 kb
Host smart-bf4cd1f4-83aa-40ac-8996-910ed20c8137
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210301395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3210301395
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1883885411
Short name T360
Test name
Test status
Simulation time 397706183 ps
CPU time 4.5 seconds
Started Jun 11 02:15:22 PM PDT 24
Finished Jun 11 02:15:29 PM PDT 24
Peak memory 200456 kb
Host smart-d99b67eb-5df6-4a99-83fe-4b9234a04f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883885411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1883885411
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.1298876524
Short name T381
Test name
Test status
Simulation time 60013967095 ps
CPU time 1233.42 seconds
Started Jun 11 02:15:22 PM PDT 24
Finished Jun 11 02:35:58 PM PDT 24
Peak memory 200540 kb
Host smart-74006ea7-be11-4e7c-9f3f-4f824d78a9b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298876524 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.1298876524
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1926317393
Short name T283
Test name
Test status
Simulation time 62430731 ps
CPU time 1.34 seconds
Started Jun 11 02:15:18 PM PDT 24
Finished Jun 11 02:15:22 PM PDT 24
Peak memory 200376 kb
Host smart-2cfb12b3-0af0-4c68-acb7-98846e0b08e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926317393 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.hmac_test_hmac_vectors.1926317393
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.1181446434
Short name T549
Test name
Test status
Simulation time 30337232129 ps
CPU time 404.75 seconds
Started Jun 11 02:15:26 PM PDT 24
Finished Jun 11 02:22:12 PM PDT 24
Peak memory 200452 kb
Host smart-3b2d5483-81da-44e3-a54e-815dec0fcc7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181446434 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.1181446434
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.1224068924
Short name T276
Test name
Test status
Simulation time 9972243945 ps
CPU time 36.49 seconds
Started Jun 11 02:15:23 PM PDT 24
Finished Jun 11 02:16:01 PM PDT 24
Peak memory 200516 kb
Host smart-9d9479e4-e57b-457b-88ca-0d0315b41e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224068924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.1224068924
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2460771954
Short name T315
Test name
Test status
Simulation time 53371435 ps
CPU time 0.6 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:16:01 PM PDT 24
Peak memory 196264 kb
Host smart-ff59e7c8-1704-43e2-8385-cc2c0c1b172a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460771954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2460771954
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.3518166606
Short name T273
Test name
Test status
Simulation time 613734079 ps
CPU time 31.42 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:16:34 PM PDT 24
Peak memory 228012 kb
Host smart-b90e384d-2b91-4019-acc6-554b61c2cb43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518166606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.3518166606
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3150225974
Short name T321
Test name
Test status
Simulation time 3171675766 ps
CPU time 42.21 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:16:45 PM PDT 24
Peak memory 200560 kb
Host smart-2cd92978-16a6-4ac3-ad87-b78eb4bf5d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150225974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3150225974
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.3776593681
Short name T473
Test name
Test status
Simulation time 2507390806 ps
CPU time 48.43 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:16:49 PM PDT 24
Peak memory 327588 kb
Host smart-1dea9889-e3c4-4e2d-b4c9-91e95eb04bdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776593681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.3776593681
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1434462961
Short name T286
Test name
Test status
Simulation time 14184292946 ps
CPU time 79.94 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:17:22 PM PDT 24
Peak memory 200188 kb
Host smart-4ea86482-e545-46d2-aeaf-4c968f2b9ed9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434462961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1434462961
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.161576173
Short name T281
Test name
Test status
Simulation time 8400299936 ps
CPU time 35.62 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:35 PM PDT 24
Peak memory 200544 kb
Host smart-e0a665de-0e08-4ecd-a27f-91673aac1ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161576173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.161576173
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.4177520331
Short name T533
Test name
Test status
Simulation time 539596032 ps
CPU time 6.31 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:05 PM PDT 24
Peak memory 200508 kb
Host smart-9e4a1622-3e87-47b4-b5ab-27f2f617d382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177520331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.4177520331
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.462915404
Short name T215
Test name
Test status
Simulation time 34784551056 ps
CPU time 940.64 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:31:43 PM PDT 24
Peak memory 200548 kb
Host smart-bcd2d6e2-ef95-441b-bd7d-2027f2ce8afc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462915404 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.462915404
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.426920852
Short name T146
Test name
Test status
Simulation time 36389338 ps
CPU time 1.36 seconds
Started Jun 11 02:15:54 PM PDT 24
Finished Jun 11 02:15:57 PM PDT 24
Peak memory 200404 kb
Host smart-1d229fc6-1543-4bca-bee5-e2ee0429c5ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426920852 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.426920852
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.3691263895
Short name T301
Test name
Test status
Simulation time 7981183228 ps
CPU time 446.56 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 200460 kb
Host smart-bedfd051-cd3d-4110-8088-516c8dda4091
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691263895 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.3691263895
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.653654844
Short name T209
Test name
Test status
Simulation time 14138340017 ps
CPU time 105.7 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:17:45 PM PDT 24
Peak memory 200528 kb
Host smart-eaec95f0-887c-45e5-8643-f6caee1b27e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653654844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.653654844
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.788720648
Short name T16
Test name
Test status
Simulation time 14256993 ps
CPU time 0.59 seconds
Started Jun 11 02:16:12 PM PDT 24
Finished Jun 11 02:16:15 PM PDT 24
Peak memory 196376 kb
Host smart-aa7978a2-0ae4-4db1-8c4f-08db285e290e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788720648 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.788720648
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.3902737105
Short name T291
Test name
Test status
Simulation time 897404733 ps
CPU time 44.58 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:16:45 PM PDT 24
Peak memory 224980 kb
Host smart-7829c2d7-1b26-4992-b793-04238d5b05d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3902737105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.3902737105
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4130544626
Short name T218
Test name
Test status
Simulation time 524202557 ps
CPU time 11.53 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:16:14 PM PDT 24
Peak memory 200436 kb
Host smart-b4b92f95-35e1-4262-ab4c-c249131bdf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130544626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4130544626
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3826112242
Short name T393
Test name
Test status
Simulation time 3552718913 ps
CPU time 803.07 seconds
Started Jun 11 02:15:58 PM PDT 24
Finished Jun 11 02:29:23 PM PDT 24
Peak memory 694276 kb
Host smart-bee335b6-e90b-450a-97c5-3a5d3f9bbd00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3826112242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3826112242
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.1536330250
Short name T191
Test name
Test status
Simulation time 243629916 ps
CPU time 14.01 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:16:15 PM PDT 24
Peak memory 200416 kb
Host smart-0b84d4e5-3be8-4a33-a787-fa9068204dfc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536330250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.1536330250
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1459907018
Short name T184
Test name
Test status
Simulation time 7304488178 ps
CPU time 88.74 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:17:31 PM PDT 24
Peak memory 200532 kb
Host smart-55d43dfb-1dc7-4c89-9022-7357b93e916c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459907018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1459907018
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3248637284
Short name T290
Test name
Test status
Simulation time 866717204 ps
CPU time 4.44 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:04 PM PDT 24
Peak memory 200316 kb
Host smart-4618747f-d854-463f-b263-8f7b5dfd8a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248637284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3248637284
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.350787732
Short name T251
Test name
Test status
Simulation time 13626684362 ps
CPU time 489.85 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:24:09 PM PDT 24
Peak memory 673548 kb
Host smart-2f09f538-ea7d-4d9c-8a3b-427206b5c852
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350787732 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.350787732
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.653592354
Short name T563
Test name
Test status
Simulation time 91256448 ps
CPU time 1.13 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:16:03 PM PDT 24
Peak memory 200488 kb
Host smart-28a03b8c-76b6-4f00-bf1a-b46e3765648b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653592354 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.hmac_test_hmac_vectors.653592354
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.164063649
Short name T384
Test name
Test status
Simulation time 30253493542 ps
CPU time 417.34 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:23:00 PM PDT 24
Peak memory 200524 kb
Host smart-9c58c8e4-723a-48e7-ae3b-7012438962fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164063649 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.164063649
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.556843232
Short name T135
Test name
Test status
Simulation time 8477133309 ps
CPU time 42.1 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:16:45 PM PDT 24
Peak memory 200488 kb
Host smart-8e789006-a0d1-4dda-b0d4-f847b3cc7705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556843232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.556843232
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.867710269
Short name T280
Test name
Test status
Simulation time 24667637 ps
CPU time 0.62 seconds
Started Jun 11 02:16:07 PM PDT 24
Finished Jun 11 02:16:09 PM PDT 24
Peak memory 196076 kb
Host smart-365efe37-87d3-469a-8fa0-635c6925d552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867710269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.867710269
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.1349428323
Short name T244
Test name
Test status
Simulation time 1850453851 ps
CPU time 28.07 seconds
Started Jun 11 02:16:10 PM PDT 24
Finished Jun 11 02:16:40 PM PDT 24
Peak memory 223004 kb
Host smart-0b80aa6d-cf0e-423b-9bd8-80e7af7e450e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1349428323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.1349428323
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2909384148
Short name T492
Test name
Test status
Simulation time 3569138280 ps
CPU time 47.98 seconds
Started Jun 11 02:15:58 PM PDT 24
Finished Jun 11 02:16:48 PM PDT 24
Peak memory 200512 kb
Host smart-b985cf5a-1235-4ebe-9c0a-f07794043801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909384148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2909384148
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2827398055
Short name T569
Test name
Test status
Simulation time 3007853935 ps
CPU time 742.39 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:28:18 PM PDT 24
Peak memory 757960 kb
Host smart-eb1b93a1-3c7d-408d-a93a-65a34cd0c98b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2827398055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2827398055
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1504385104
Short name T510
Test name
Test status
Simulation time 4711102659 ps
CPU time 129.75 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:18:09 PM PDT 24
Peak memory 200512 kb
Host smart-57ea3f86-a4ea-440b-b314-5575edff96af
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504385104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1504385104
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2166867064
Short name T389
Test name
Test status
Simulation time 11566433180 ps
CPU time 82.41 seconds
Started Jun 11 02:15:58 PM PDT 24
Finished Jun 11 02:17:23 PM PDT 24
Peak memory 200552 kb
Host smart-bf71c920-0f40-4502-b947-870b0a7d6154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166867064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2166867064
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.26902833
Short name T49
Test name
Test status
Simulation time 840371670 ps
CPU time 7.24 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:16:04 PM PDT 24
Peak memory 200412 kb
Host smart-fe6ba183-8a1d-4ac4-87f5-eeab41da50bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26902833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.26902833
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1263051217
Short name T247
Test name
Test status
Simulation time 16500978019 ps
CPU time 1559.26 seconds
Started Jun 11 02:16:07 PM PDT 24
Finished Jun 11 02:42:07 PM PDT 24
Peak memory 719708 kb
Host smart-e4d95f91-bda9-49d9-b8b1-abb15ad37efb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263051217 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1263051217
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.896164456
Short name T372
Test name
Test status
Simulation time 47876941 ps
CPU time 1.11 seconds
Started Jun 11 02:16:07 PM PDT 24
Finished Jun 11 02:16:09 PM PDT 24
Peak memory 200164 kb
Host smart-dc5bda17-b5ad-4365-8a0a-106af1923d08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896164456 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.hmac_test_hmac_vectors.896164456
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.35272909
Short name T119
Test name
Test status
Simulation time 87962047481 ps
CPU time 603.85 seconds
Started Jun 11 02:16:03 PM PDT 24
Finished Jun 11 02:26:08 PM PDT 24
Peak memory 200448 kb
Host smart-cc71432f-fa99-44b4-8c14-8c3138ae6e37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35272909 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.35272909
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.771572364
Short name T587
Test name
Test status
Simulation time 1940673022 ps
CPU time 86.3 seconds
Started Jun 11 02:16:02 PM PDT 24
Finished Jun 11 02:17:30 PM PDT 24
Peak memory 200440 kb
Host smart-01812f25-de88-4978-9901-37c78e1eafad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771572364 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.771572364
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.4268292670
Short name T263
Test name
Test status
Simulation time 38494118 ps
CPU time 0.6 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:16:01 PM PDT 24
Peak memory 196020 kb
Host smart-636894b2-0f85-48af-8d16-f1d94ec960ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268292670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4268292670
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.4130880592
Short name T461
Test name
Test status
Simulation time 2415606835 ps
CPU time 30.61 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:34 PM PDT 24
Peak memory 218916 kb
Host smart-e1cd01c8-1f56-45bd-91a9-1f0b81a16f27
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130880592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.4130880592
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.4259834756
Short name T507
Test name
Test status
Simulation time 22111462224 ps
CPU time 75.71 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:17:14 PM PDT 24
Peak memory 200472 kb
Host smart-239891c5-55a2-4f73-a897-2f72d4276c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259834756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.4259834756
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.52614701
Short name T257
Test name
Test status
Simulation time 1628478797 ps
CPU time 439.22 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:23:17 PM PDT 24
Peak memory 675212 kb
Host smart-fcb42e90-6d41-4ea7-86d1-ea564a0fc01b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=52614701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.52614701
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3841300411
Short name T317
Test name
Test status
Simulation time 19238938707 ps
CPU time 83.7 seconds
Started Jun 11 02:15:58 PM PDT 24
Finished Jun 11 02:17:23 PM PDT 24
Peak memory 200488 kb
Host smart-c8f1f6c8-9fb4-4f9a-829c-747eeebef9e1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841300411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3841300411
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4030692249
Short name T581
Test name
Test status
Simulation time 205770179 ps
CPU time 11.36 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:16:12 PM PDT 24
Peak memory 200420 kb
Host smart-435458df-3127-41f7-8b6d-599df87433f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030692249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4030692249
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2316876591
Short name T561
Test name
Test status
Simulation time 594009608 ps
CPU time 1.44 seconds
Started Jun 11 02:16:05 PM PDT 24
Finished Jun 11 02:16:07 PM PDT 24
Peak memory 200452 kb
Host smart-4c90382f-c645-4f53-b00d-278238724e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316876591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2316876591
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.4139439453
Short name T74
Test name
Test status
Simulation time 32826237 ps
CPU time 1.22 seconds
Started Jun 11 02:16:04 PM PDT 24
Finished Jun 11 02:16:07 PM PDT 24
Peak memory 200388 kb
Host smart-192f8885-0e23-4ee5-a22d-4adfc8cb2b81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139439453 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.hmac_test_hmac_vectors.4139439453
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.1538561712
Short name T231
Test name
Test status
Simulation time 167119102748 ps
CPU time 456.52 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:23:38 PM PDT 24
Peak memory 200420 kb
Host smart-667f0c8d-c64f-4a79-a4d4-1befe6fcb1df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538561712 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.1538561712
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.2144056868
Short name T153
Test name
Test status
Simulation time 324206932 ps
CPU time 18.14 seconds
Started Jun 11 02:15:55 PM PDT 24
Finished Jun 11 02:16:14 PM PDT 24
Peak memory 200472 kb
Host smart-5e46fac7-83da-469a-a02c-524725bd5a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144056868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.2144056868
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.4138391132
Short name T544
Test name
Test status
Simulation time 12195418 ps
CPU time 0.6 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:15:59 PM PDT 24
Peak memory 196000 kb
Host smart-4c1acaba-a879-4d2d-a7ae-3cb5bb59bcdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138391132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.4138391132
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.3165066433
Short name T567
Test name
Test status
Simulation time 3047805550 ps
CPU time 25.68 seconds
Started Jun 11 02:15:56 PM PDT 24
Finished Jun 11 02:16:24 PM PDT 24
Peak memory 216332 kb
Host smart-f8fa08ed-0cba-4f3b-b849-2072a7a668d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165066433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.3165066433
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.3326968092
Short name T54
Test name
Test status
Simulation time 2395565135 ps
CPU time 67.29 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:17:08 PM PDT 24
Peak memory 200508 kb
Host smart-0610f3cc-637a-43d4-aa89-5d5fab58a82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326968092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.3326968092
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.798974616
Short name T585
Test name
Test status
Simulation time 5337739837 ps
CPU time 225.69 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:19:48 PM PDT 24
Peak memory 496588 kb
Host smart-8dbf54f4-b412-4ebc-90b0-0d0a66073a33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=798974616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.798974616
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1930768045
Short name T371
Test name
Test status
Simulation time 3441426134 ps
CPU time 65.06 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:17:08 PM PDT 24
Peak memory 200524 kb
Host smart-73c41844-b028-4316-ae62-f680f3522dda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930768045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1930768045
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.4029121415
Short name T130
Test name
Test status
Simulation time 3946289298 ps
CPU time 57.96 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:17:00 PM PDT 24
Peak memory 200476 kb
Host smart-97c88bfc-a48c-4206-84b9-87b20e2871c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029121415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.4029121415
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.332413430
Short name T37
Test name
Test status
Simulation time 200642232 ps
CPU time 1.55 seconds
Started Jun 11 02:15:59 PM PDT 24
Finished Jun 11 02:16:03 PM PDT 24
Peak memory 200416 kb
Host smart-b196f008-a5a9-4709-943a-4577bbf4b108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332413430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.332413430
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.2678565950
Short name T436
Test name
Test status
Simulation time 93862341403 ps
CPU time 1444.4 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:40:07 PM PDT 24
Peak memory 636508 kb
Host smart-9c16e0b4-d9be-4ffc-bd4f-723d97a76e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678565950 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.2678565950
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.668452854
Short name T591
Test name
Test status
Simulation time 79354065 ps
CPU time 1.5 seconds
Started Jun 11 02:16:01 PM PDT 24
Finished Jun 11 02:16:05 PM PDT 24
Peak memory 200368 kb
Host smart-fb88d218-3c55-46c9-a3fc-e4a1913a025b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668452854 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.hmac_test_hmac_vectors.668452854
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.2921680195
Short name T196
Test name
Test status
Simulation time 156019552177 ps
CPU time 531.7 seconds
Started Jun 11 02:16:01 PM PDT 24
Finished Jun 11 02:24:55 PM PDT 24
Peak memory 200404 kb
Host smart-3d77e474-04ee-47e1-b13c-761611db1f58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921680195 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.2921680195
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.3630053552
Short name T388
Test name
Test status
Simulation time 20447734840 ps
CPU time 85.6 seconds
Started Jun 11 02:16:00 PM PDT 24
Finished Jun 11 02:17:28 PM PDT 24
Peak memory 200520 kb
Host smart-9b36fc4e-2ad9-4f4c-a43a-048da6970db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630053552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.3630053552
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2843542434
Short name T234
Test name
Test status
Simulation time 39919666 ps
CPU time 0.61 seconds
Started Jun 11 02:16:04 PM PDT 24
Finished Jun 11 02:16:05 PM PDT 24
Peak memory 195552 kb
Host smart-94c3b3b6-4c0d-40c2-8b94-44de13be23dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843542434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2843542434
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2793105199
Short name T367
Test name
Test status
Simulation time 459306679 ps
CPU time 21.16 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:16:41 PM PDT 24
Peak memory 216728 kb
Host smart-e0ad5d01-e6ae-4ebb-a99c-51c9e610dfdf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2793105199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2793105199
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.1380665375
Short name T152
Test name
Test status
Simulation time 3815860924 ps
CPU time 19.52 seconds
Started Jun 11 02:16:10 PM PDT 24
Finished Jun 11 02:16:31 PM PDT 24
Peak memory 200520 kb
Host smart-d5371243-3801-4e23-8ea2-4c6bc4c7e3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380665375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.1380665375
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3893294695
Short name T548
Test name
Test status
Simulation time 988024731 ps
CPU time 185.55 seconds
Started Jun 11 02:16:14 PM PDT 24
Finished Jun 11 02:19:21 PM PDT 24
Peak memory 464948 kb
Host smart-c1460136-fdc0-4425-92a8-aa43df5458fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3893294695 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3893294695
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2802958030
Short name T239
Test name
Test status
Simulation time 13210135459 ps
CPU time 120.82 seconds
Started Jun 11 02:16:12 PM PDT 24
Finished Jun 11 02:18:15 PM PDT 24
Peak memory 200564 kb
Host smart-36260453-b20a-415b-a996-a4b17ad18d5e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802958030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2802958030
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.1439241665
Short name T345
Test name
Test status
Simulation time 483195559 ps
CPU time 25.86 seconds
Started Jun 11 02:16:01 PM PDT 24
Finished Jun 11 02:16:29 PM PDT 24
Peak memory 200400 kb
Host smart-0b4a8445-dbbb-49e0-9d40-af007ffcd2cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439241665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.1439241665
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.187784042
Short name T476
Test name
Test status
Simulation time 1856771269 ps
CPU time 8.63 seconds
Started Jun 11 02:15:57 PM PDT 24
Finished Jun 11 02:16:08 PM PDT 24
Peak memory 200360 kb
Host smart-8fda06f8-109f-49b3-807e-b7be3381d897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187784042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.187784042
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2566593921
Short name T61
Test name
Test status
Simulation time 246585603374 ps
CPU time 2194.06 seconds
Started Jun 11 02:16:13 PM PDT 24
Finished Jun 11 02:52:49 PM PDT 24
Peak memory 672100 kb
Host smart-e1feeaf9-9d44-411b-b381-481265a52ef3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566593921 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2566593921
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.2059966921
Short name T197
Test name
Test status
Simulation time 50637875 ps
CPU time 1.16 seconds
Started Jun 11 02:16:13 PM PDT 24
Finished Jun 11 02:16:16 PM PDT 24
Peak memory 200376 kb
Host smart-1cdb196c-bee0-430d-961b-eed7153285d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059966921 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.2059966921
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.924187088
Short name T202
Test name
Test status
Simulation time 39792047379 ps
CPU time 531.97 seconds
Started Jun 11 02:16:16 PM PDT 24
Finished Jun 11 02:25:10 PM PDT 24
Peak memory 200356 kb
Host smart-156294f3-df1e-4d8d-a41a-4a4bf992b8a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924187088 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.924187088
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2511942106
Short name T509
Test name
Test status
Simulation time 5918275616 ps
CPU time 99.39 seconds
Started Jun 11 02:16:09 PM PDT 24
Finished Jun 11 02:17:50 PM PDT 24
Peak memory 200504 kb
Host smart-fc248782-d511-46e1-8dfe-98008d3e4e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511942106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2511942106
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2302132073
Short name T216
Test name
Test status
Simulation time 13235092 ps
CPU time 0.58 seconds
Started Jun 11 02:16:10 PM PDT 24
Finished Jun 11 02:16:12 PM PDT 24
Peak memory 195376 kb
Host smart-1107d14a-54ab-4a30-a789-d3a8cee67925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302132073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2302132073
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.1286923363
Short name T266
Test name
Test status
Simulation time 4348103957 ps
CPU time 47.52 seconds
Started Jun 11 02:16:07 PM PDT 24
Finished Jun 11 02:16:56 PM PDT 24
Peak memory 235304 kb
Host smart-e0a8e71e-f35c-4cbc-a4a0-5066be5b6d51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1286923363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.1286923363
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.755087404
Short name T227
Test name
Test status
Simulation time 3679077694 ps
CPU time 29.29 seconds
Started Jun 11 02:16:11 PM PDT 24
Finished Jun 11 02:16:43 PM PDT 24
Peak memory 200460 kb
Host smart-c644927c-2916-4b81-bbb3-04a3c1a26c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755087404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.755087404
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.4195038521
Short name T571
Test name
Test status
Simulation time 7427911304 ps
CPU time 1012.18 seconds
Started Jun 11 02:16:11 PM PDT 24
Finished Jun 11 02:33:06 PM PDT 24
Peak memory 750416 kb
Host smart-05e0a80f-4373-41cb-a989-200b147b7567
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4195038521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.4195038521
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3338310484
Short name T329
Test name
Test status
Simulation time 19680068476 ps
CPU time 95.89 seconds
Started Jun 11 02:16:12 PM PDT 24
Finished Jun 11 02:17:50 PM PDT 24
Peak memory 200504 kb
Host smart-273fcd94-353c-44c3-86ba-fe2778a8b5bb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338310484 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3338310484
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.988752844
Short name T493
Test name
Test status
Simulation time 11456582762 ps
CPU time 131.48 seconds
Started Jun 11 02:16:14 PM PDT 24
Finished Jun 11 02:18:27 PM PDT 24
Peak memory 200452 kb
Host smart-c047087b-958b-4f4d-ba99-d6a96fb45d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988752844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.988752844
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2978960525
Short name T574
Test name
Test status
Simulation time 1105425633 ps
CPU time 6.84 seconds
Started Jun 11 02:16:17 PM PDT 24
Finished Jun 11 02:16:25 PM PDT 24
Peak memory 200456 kb
Host smart-04ac30bb-bb78-4fd1-80de-1678fac8efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978960525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2978960525
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3482638484
Short name T170
Test name
Test status
Simulation time 46155217472 ps
CPU time 319.66 seconds
Started Jun 11 02:16:06 PM PDT 24
Finished Jun 11 02:21:27 PM PDT 24
Peak memory 200468 kb
Host smart-3e287e53-dfec-464c-b48d-b876a653e8dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482638484 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3482638484
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1005247668
Short name T576
Test name
Test status
Simulation time 32446918 ps
CPU time 1.32 seconds
Started Jun 11 02:16:07 PM PDT 24
Finished Jun 11 02:16:09 PM PDT 24
Peak memory 200412 kb
Host smart-0d658d3f-19e1-434d-8bfb-946207aecb31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005247668 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1005247668
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.3035268739
Short name T141
Test name
Test status
Simulation time 113465386772 ps
CPU time 528.43 seconds
Started Jun 11 02:16:12 PM PDT 24
Finished Jun 11 02:25:03 PM PDT 24
Peak memory 200448 kb
Host smart-b2fe9ff7-4bd1-4d3f-a32a-74bdff2efe24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035268739 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.3035268739
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1883804772
Short name T539
Test name
Test status
Simulation time 163838176 ps
CPU time 7.1 seconds
Started Jun 11 02:16:12 PM PDT 24
Finished Jun 11 02:16:21 PM PDT 24
Peak memory 200392 kb
Host smart-a4b7a278-9897-46b2-b668-d9f1add0c0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883804772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1883804772
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.1769434943
Short name T3
Test name
Test status
Simulation time 33197691 ps
CPU time 0.59 seconds
Started Jun 11 02:16:14 PM PDT 24
Finished Jun 11 02:16:16 PM PDT 24
Peak memory 197116 kb
Host smart-56535dc3-7118-448b-8244-58d00b638970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769434943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.1769434943
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.3139767125
Short name T403
Test name
Test status
Simulation time 849451270 ps
CPU time 21.32 seconds
Started Jun 11 02:16:11 PM PDT 24
Finished Jun 11 02:16:34 PM PDT 24
Peak memory 208608 kb
Host smart-ca76c6ac-f723-4b20-88cb-27bcb1fb6678
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3139767125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.3139767125
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.507763741
Short name T425
Test name
Test status
Simulation time 3562416646 ps
CPU time 9.38 seconds
Started Jun 11 02:16:11 PM PDT 24
Finished Jun 11 02:16:23 PM PDT 24
Peak memory 200492 kb
Host smart-4320cb6b-7fcf-4516-bca7-c9593075c84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507763741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.507763741
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.3275941577
Short name T504
Test name
Test status
Simulation time 36552406 ps
CPU time 0.68 seconds
Started Jun 11 02:16:07 PM PDT 24
Finished Jun 11 02:16:09 PM PDT 24
Peak memory 198488 kb
Host smart-464f87a4-06a2-4416-997d-00f8d090fb7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3275941577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.3275941577
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.1039829797
Short name T387
Test name
Test status
Simulation time 16157097330 ps
CPU time 186.91 seconds
Started Jun 11 02:16:12 PM PDT 24
Finished Jun 11 02:19:21 PM PDT 24
Peak memory 200468 kb
Host smart-9cc7acad-5408-4ce4-b769-b4ab169ee4ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039829797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1039829797
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3757835557
Short name T126
Test name
Test status
Simulation time 1947954136 ps
CPU time 119.88 seconds
Started Jun 11 02:16:13 PM PDT 24
Finished Jun 11 02:18:14 PM PDT 24
Peak memory 200408 kb
Host smart-46f15a7c-d878-4876-af7f-db4033857de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757835557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3757835557
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.2762056776
Short name T258
Test name
Test status
Simulation time 849289331 ps
CPU time 7.89 seconds
Started Jun 11 02:16:04 PM PDT 24
Finished Jun 11 02:16:13 PM PDT 24
Peak memory 200432 kb
Host smart-44926e56-c3ae-405a-8a71-2ebd0a27c176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762056776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.2762056776
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2513782335
Short name T474
Test name
Test status
Simulation time 178573493 ps
CPU time 1.11 seconds
Started Jun 11 02:16:11 PM PDT 24
Finished Jun 11 02:16:13 PM PDT 24
Peak memory 200244 kb
Host smart-472cffa3-3317-445d-a573-a47545e1907b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513782335 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2513782335
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.1849976873
Short name T252
Test name
Test status
Simulation time 44686406 ps
CPU time 1.05 seconds
Started Jun 11 02:16:07 PM PDT 24
Finished Jun 11 02:16:09 PM PDT 24
Peak memory 200188 kb
Host smart-5c78e7d8-089b-433c-9723-0ebcfee7faaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849976873 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.hmac_test_hmac_vectors.1849976873
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.399196573
Short name T390
Test name
Test status
Simulation time 55100316164 ps
CPU time 476.41 seconds
Started Jun 11 02:16:13 PM PDT 24
Finished Jun 11 02:24:11 PM PDT 24
Peak memory 200404 kb
Host smart-8358ee55-4765-4fed-9cf8-bd62e30d16e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399196573 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.399196573
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3072907397
Short name T379
Test name
Test status
Simulation time 1746912168 ps
CPU time 23.66 seconds
Started Jun 11 02:16:09 PM PDT 24
Finished Jun 11 02:16:34 PM PDT 24
Peak memory 200444 kb
Host smart-84f8033b-767c-4260-85da-9547f50140d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072907397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3072907397
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1956020211
Short name T523
Test name
Test status
Simulation time 29202093 ps
CPU time 0.55 seconds
Started Jun 11 02:16:06 PM PDT 24
Finished Jun 11 02:16:08 PM PDT 24
Peak memory 195376 kb
Host smart-7f27cd64-e1c8-4eeb-938f-36fb3914d965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956020211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1956020211
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.387267370
Short name T214
Test name
Test status
Simulation time 4029985692 ps
CPU time 36.58 seconds
Started Jun 11 02:16:10 PM PDT 24
Finished Jun 11 02:16:47 PM PDT 24
Peak memory 228040 kb
Host smart-d99f1a88-7610-4197-bea2-1c7c28789ff9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387267370 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.387267370
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.87118712
Short name T551
Test name
Test status
Simulation time 3740302879 ps
CPU time 58.55 seconds
Started Jun 11 02:16:10 PM PDT 24
Finished Jun 11 02:17:09 PM PDT 24
Peak memory 200444 kb
Host smart-b6dc17a7-592d-44ad-bff9-e2bb176973b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87118712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.87118712
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.162466414
Short name T348
Test name
Test status
Simulation time 16288306814 ps
CPU time 1083.25 seconds
Started Jun 11 02:16:13 PM PDT 24
Finished Jun 11 02:34:18 PM PDT 24
Peak memory 717684 kb
Host smart-aa0051c2-ed50-47b9-9b46-481e71cffc8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=162466414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.162466414
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1653292356
Short name T584
Test name
Test status
Simulation time 3696824768 ps
CPU time 33.43 seconds
Started Jun 11 02:16:10 PM PDT 24
Finished Jun 11 02:16:45 PM PDT 24
Peak memory 200476 kb
Host smart-5f8df200-a2ef-4d8f-8cce-60190cf10577
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653292356 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1653292356
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.3906914780
Short name T588
Test name
Test status
Simulation time 966157347 ps
CPU time 62.03 seconds
Started Jun 11 02:16:05 PM PDT 24
Finished Jun 11 02:17:08 PM PDT 24
Peak memory 200476 kb
Host smart-690aae0f-9128-40cf-8a5b-bb19fbd8374e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906914780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.3906914780
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1955028902
Short name T131
Test name
Test status
Simulation time 124454488 ps
CPU time 1.68 seconds
Started Jun 11 02:16:06 PM PDT 24
Finished Jun 11 02:16:10 PM PDT 24
Peak memory 199392 kb
Host smart-1426e2d2-6364-4231-bc14-f49072e2b2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955028902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1955028902
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.59682008
Short name T96
Test name
Test status
Simulation time 17658892070 ps
CPU time 88.33 seconds
Started Jun 11 02:16:05 PM PDT 24
Finished Jun 11 02:17:34 PM PDT 24
Peak memory 200568 kb
Host smart-ff2b9b8a-e1d7-4b0d-aa59-5f00d8a89757
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59682008 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.59682008
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.851332909
Short name T320
Test name
Test status
Simulation time 88142109 ps
CPU time 1.39 seconds
Started Jun 11 02:16:07 PM PDT 24
Finished Jun 11 02:16:09 PM PDT 24
Peak memory 200396 kb
Host smart-3275ebc1-a2d7-453c-8386-bbd8f9ab6de0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851332909 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.hmac_test_hmac_vectors.851332909
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.1823220041
Short name T127
Test name
Test status
Simulation time 51922878456 ps
CPU time 495.56 seconds
Started Jun 11 02:16:15 PM PDT 24
Finished Jun 11 02:24:32 PM PDT 24
Peak memory 200444 kb
Host smart-6409308b-78e1-43cd-8fcd-56cf90486a9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823220041 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.1823220041
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.324087750
Short name T282
Test name
Test status
Simulation time 281133632 ps
CPU time 7.2 seconds
Started Jun 11 02:16:08 PM PDT 24
Finished Jun 11 02:16:16 PM PDT 24
Peak memory 200420 kb
Host smart-c2a2f0d0-7e0d-474e-bfb2-b74422fefbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324087750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.324087750
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1002013792
Short name T267
Test name
Test status
Simulation time 35706547 ps
CPU time 0.6 seconds
Started Jun 11 02:16:14 PM PDT 24
Finished Jun 11 02:16:16 PM PDT 24
Peak memory 196364 kb
Host smart-3b68455f-3b4b-429a-b476-c838eb9222a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002013792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1002013792
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2327684860
Short name T15
Test name
Test status
Simulation time 3086862044 ps
CPU time 30.4 seconds
Started Jun 11 02:16:15 PM PDT 24
Finished Jun 11 02:16:47 PM PDT 24
Peak memory 231252 kb
Host smart-db4284aa-4bc4-4d4a-8c33-8454b2baa3ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2327684860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2327684860
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.376620738
Short name T420
Test name
Test status
Simulation time 2940924709 ps
CPU time 58.58 seconds
Started Jun 11 02:16:09 PM PDT 24
Finished Jun 11 02:17:09 PM PDT 24
Peak memory 200460 kb
Host smart-9ac7aa51-377e-4fab-89b8-ceaa85173a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376620738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.376620738
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_error.518487357
Short name T161
Test name
Test status
Simulation time 13029207057 ps
CPU time 167.84 seconds
Started Jun 11 02:16:13 PM PDT 24
Finished Jun 11 02:19:03 PM PDT 24
Peak memory 200496 kb
Host smart-e8268c53-d8bb-491b-a98c-c8820b2fccb1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518487357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.518487357
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.225199124
Short name T488
Test name
Test status
Simulation time 11582061162 ps
CPU time 55.79 seconds
Started Jun 11 02:16:07 PM PDT 24
Finished Jun 11 02:17:04 PM PDT 24
Peak memory 200492 kb
Host smart-3a3d3869-7bb4-4d5b-8b62-20c38c8a3f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225199124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.225199124
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.2609642678
Short name T589
Test name
Test status
Simulation time 1932836470 ps
CPU time 11.39 seconds
Started Jun 11 02:16:16 PM PDT 24
Finished Jun 11 02:16:29 PM PDT 24
Peak memory 200432 kb
Host smart-1b3cea7b-ab76-4b58-916a-bd5db9596d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609642678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.2609642678
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.1233410291
Short name T30
Test name
Test status
Simulation time 19064121647 ps
CPU time 892.1 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:31:12 PM PDT 24
Peak memory 764336 kb
Host smart-8a7d3218-fb35-4c41-aa30-da0757012e77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233410291 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.1233410291
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1633502564
Short name T365
Test name
Test status
Simulation time 137085549 ps
CPU time 1.3 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:16:21 PM PDT 24
Peak memory 200496 kb
Host smart-3439c190-3008-489a-a1be-4f321bfcbf0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633502564 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1633502564
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1636188333
Short name T485
Test name
Test status
Simulation time 18310776133 ps
CPU time 471.56 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:24:12 PM PDT 24
Peak memory 200472 kb
Host smart-b4536f10-442c-4057-af49-45ebd7451c4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636188333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.1636188333
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.2267248320
Short name T219
Test name
Test status
Simulation time 13477930755 ps
CPU time 103.43 seconds
Started Jun 11 02:16:16 PM PDT 24
Finished Jun 11 02:18:02 PM PDT 24
Peak memory 200536 kb
Host smart-54ee1171-ede6-463a-a8ec-9c6e063e8bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267248320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.2267248320
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2655575109
Short name T447
Test name
Test status
Simulation time 13341442 ps
CPU time 0.61 seconds
Started Jun 11 02:15:30 PM PDT 24
Finished Jun 11 02:15:32 PM PDT 24
Peak memory 196264 kb
Host smart-6efe2adf-c2b9-4b93-a31f-bd5f0458bd62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655575109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2655575109
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.726756194
Short name T336
Test name
Test status
Simulation time 666840570 ps
CPU time 36.49 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:16:10 PM PDT 24
Peak memory 248320 kb
Host smart-82761a56-3588-41d5-a3db-f2d43e744cef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=726756194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.726756194
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3173105169
Short name T235
Test name
Test status
Simulation time 191967568 ps
CPU time 1.29 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:15:34 PM PDT 24
Peak memory 200320 kb
Host smart-53d73848-2309-4a39-8173-01660e90dcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173105169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3173105169
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.4222002879
Short name T529
Test name
Test status
Simulation time 3494839637 ps
CPU time 264.31 seconds
Started Jun 11 02:15:28 PM PDT 24
Finished Jun 11 02:19:53 PM PDT 24
Peak memory 502196 kb
Host smart-6a7f30ce-5b15-4628-9c72-e6f42d19a625
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4222002879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.4222002879
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1976365226
Short name T429
Test name
Test status
Simulation time 9812954402 ps
CPU time 68.82 seconds
Started Jun 11 02:15:34 PM PDT 24
Finished Jun 11 02:16:45 PM PDT 24
Peak memory 200520 kb
Host smart-ead5bd00-dddf-470a-b84e-24c77849edb9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976365226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1976365226
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.1956065088
Short name T21
Test name
Test status
Simulation time 333545246 ps
CPU time 0.99 seconds
Started Jun 11 02:15:30 PM PDT 24
Finished Jun 11 02:15:32 PM PDT 24
Peak memory 219992 kb
Host smart-a5b12366-e50b-4dee-b724-aa0d7167bd40
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956065088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.1956065088
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.922567091
Short name T199
Test name
Test status
Simulation time 2420537377 ps
CPU time 11.39 seconds
Started Jun 11 02:15:33 PM PDT 24
Finished Jun 11 02:15:47 PM PDT 24
Peak memory 200408 kb
Host smart-7dbbea90-b7e8-407c-9350-f5a35feb0a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922567091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.922567091
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.2541214219
Short name T52
Test name
Test status
Simulation time 37459714786 ps
CPU time 211.96 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:19:05 PM PDT 24
Peak memory 200456 kb
Host smart-f42bc82a-e539-422c-9db0-22fc8b931c6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541214219 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.2541214219
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.667019757
Short name T414
Test name
Test status
Simulation time 58005796 ps
CPU time 1.13 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:15:35 PM PDT 24
Peak memory 200424 kb
Host smart-38b54625-c836-40f4-8ccc-d5634535f46e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667019757 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_hmac_vectors.667019757
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.3058657104
Short name T243
Test name
Test status
Simulation time 43378574480 ps
CPU time 462.91 seconds
Started Jun 11 02:15:32 PM PDT 24
Finished Jun 11 02:23:18 PM PDT 24
Peak memory 200448 kb
Host smart-fc3e102e-2629-455f-b8f2-fc8ef68a25bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058657104 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.3058657104
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.445802044
Short name T557
Test name
Test status
Simulation time 3503565151 ps
CPU time 66.49 seconds
Started Jun 11 02:15:35 PM PDT 24
Finished Jun 11 02:16:43 PM PDT 24
Peak memory 200528 kb
Host smart-0fefc464-e994-4985-8f18-3704637a8195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445802044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.445802044
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.902864520
Short name T312
Test name
Test status
Simulation time 16960631 ps
CPU time 0.58 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:16:21 PM PDT 24
Peak memory 197056 kb
Host smart-05a31b22-a1e2-48cb-9cf0-b79b599592e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902864520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.902864520
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.2341919213
Short name T525
Test name
Test status
Simulation time 427091540 ps
CPU time 5.31 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:16:25 PM PDT 24
Peak memory 200452 kb
Host smart-cc962409-c812-49e4-b7ac-6fa0e1769d25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2341919213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.2341919213
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.239256168
Short name T346
Test name
Test status
Simulation time 3828657453 ps
CPU time 29.74 seconds
Started Jun 11 02:16:15 PM PDT 24
Finished Jun 11 02:16:46 PM PDT 24
Peak memory 200544 kb
Host smart-ac64c0ce-bdaf-4021-87a9-916333d7cda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239256168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.239256168
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1793970687
Short name T122
Test name
Test status
Simulation time 4154691864 ps
CPU time 1058.11 seconds
Started Jun 11 02:16:16 PM PDT 24
Finished Jun 11 02:33:56 PM PDT 24
Peak memory 768328 kb
Host smart-613ac241-367d-4be2-823f-1b78efb050c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793970687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1793970687
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.2261005873
Short name T327
Test name
Test status
Simulation time 7551682142 ps
CPU time 135.51 seconds
Started Jun 11 02:16:13 PM PDT 24
Finished Jun 11 02:18:30 PM PDT 24
Peak memory 200424 kb
Host smart-6b3c4206-f13c-4000-9507-70922eadff5f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261005873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.2261005873
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.3982144724
Short name T537
Test name
Test status
Simulation time 6580001242 ps
CPU time 33.45 seconds
Started Jun 11 02:16:08 PM PDT 24
Finished Jun 11 02:16:43 PM PDT 24
Peak memory 200396 kb
Host smart-b22fc06b-6ee6-4621-a4d4-7e3c3f478f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982144724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.3982144724
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.2784205325
Short name T554
Test name
Test status
Simulation time 330345452 ps
CPU time 6.01 seconds
Started Jun 11 02:16:14 PM PDT 24
Finished Jun 11 02:16:21 PM PDT 24
Peak memory 200380 kb
Host smart-f64f91df-e875-41fe-b4e5-9ed9df7a0f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784205325 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.2784205325
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.3374226965
Short name T408
Test name
Test status
Simulation time 16601230112 ps
CPU time 1330.24 seconds
Started Jun 11 02:16:18 PM PDT 24
Finished Jun 11 02:38:30 PM PDT 24
Peak memory 633288 kb
Host smart-984e5b40-3774-48ae-b023-62a261af9167
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374226965 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.3374226965
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.2149319063
Short name T316
Test name
Test status
Simulation time 174438453 ps
CPU time 1.13 seconds
Started Jun 11 02:16:11 PM PDT 24
Finished Jun 11 02:16:14 PM PDT 24
Peak memory 200092 kb
Host smart-e59e0a43-d3d2-47ef-aa95-0cc6c6ebd74c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149319063 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.2149319063
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.4286790057
Short name T260
Test name
Test status
Simulation time 173041975679 ps
CPU time 552.67 seconds
Started Jun 11 02:16:23 PM PDT 24
Finished Jun 11 02:25:37 PM PDT 24
Peak memory 200432 kb
Host smart-467b5d3e-72d0-4b96-8940-ff3cc5c9f6f1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286790057 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.4286790057
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.3812095678
Short name T1
Test name
Test status
Simulation time 6359372306 ps
CPU time 23.58 seconds
Started Jun 11 02:16:16 PM PDT 24
Finished Jun 11 02:16:41 PM PDT 24
Peak memory 200508 kb
Host smart-f465ecfb-ec0f-4248-89a8-78e57067fb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812095678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.3812095678
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3291384387
Short name T363
Test name
Test status
Simulation time 17345173 ps
CPU time 0.61 seconds
Started Jun 11 02:16:21 PM PDT 24
Finished Jun 11 02:16:24 PM PDT 24
Peak memory 196352 kb
Host smart-25213484-6d77-4a71-bf90-6b6eb86d88bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291384387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3291384387
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.230450094
Short name T210
Test name
Test status
Simulation time 1252707648 ps
CPU time 55.54 seconds
Started Jun 11 02:16:22 PM PDT 24
Finished Jun 11 02:17:19 PM PDT 24
Peak memory 233132 kb
Host smart-ec7e0f81-ea59-4ba7-9fc9-443e3a93e9e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230450094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.230450094
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.230939103
Short name T241
Test name
Test status
Simulation time 2669616884 ps
CPU time 177.47 seconds
Started Jun 11 02:16:16 PM PDT 24
Finished Jun 11 02:19:15 PM PDT 24
Peak memory 603460 kb
Host smart-2f3664a0-2e04-4719-9bce-f8b9c34c1b68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230939103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.230939103
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3874595850
Short name T137
Test name
Test status
Simulation time 38326020762 ps
CPU time 134.51 seconds
Started Jun 11 02:16:16 PM PDT 24
Finished Jun 11 02:18:32 PM PDT 24
Peak memory 200456 kb
Host smart-e9559bcf-9ead-495c-8383-91c15f4e503e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874595850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3874595850
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.4059676122
Short name T455
Test name
Test status
Simulation time 10345029848 ps
CPU time 56.24 seconds
Started Jun 11 02:16:11 PM PDT 24
Finished Jun 11 02:17:09 PM PDT 24
Peak memory 200476 kb
Host smart-3d01f659-9ba8-4a07-b70d-b06d61e0651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059676122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.4059676122
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.486142090
Short name T579
Test name
Test status
Simulation time 2496220599 ps
CPU time 8.78 seconds
Started Jun 11 02:16:20 PM PDT 24
Finished Jun 11 02:16:30 PM PDT 24
Peak memory 200488 kb
Host smart-83310cb6-f546-4a5b-8748-1a93b8cce44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486142090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.486142090
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.4094697971
Short name T100
Test name
Test status
Simulation time 244584351003 ps
CPU time 5499.74 seconds
Started Jun 11 02:16:20 PM PDT 24
Finished Jun 11 03:48:02 PM PDT 24
Peak memory 923488 kb
Host smart-ce85d8e9-6250-41e2-ab39-2cf9ab635f07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094697971 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.4094697971
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.610209233
Short name T511
Test name
Test status
Simulation time 96418328 ps
CPU time 1.04 seconds
Started Jun 11 02:16:15 PM PDT 24
Finished Jun 11 02:16:18 PM PDT 24
Peak memory 200280 kb
Host smart-58ff4582-be69-4e17-8de0-87ecb9c18bae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610209233 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 31.hmac_test_hmac_vectors.610209233
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.4146473914
Short name T265
Test name
Test status
Simulation time 29374433738 ps
CPU time 579.32 seconds
Started Jun 11 02:16:21 PM PDT 24
Finished Jun 11 02:26:02 PM PDT 24
Peak memory 200388 kb
Host smart-bb6c12ac-0853-4c8c-9ffa-c8b2451a818b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146473914 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.4146473914
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.3819141703
Short name T535
Test name
Test status
Simulation time 919500389 ps
CPU time 9.57 seconds
Started Jun 11 02:16:22 PM PDT 24
Finished Jun 11 02:16:33 PM PDT 24
Peak memory 200392 kb
Host smart-6833f180-394f-47a0-8fe1-f23cd7c60bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819141703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.3819141703
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1118174969
Short name T17
Test name
Test status
Simulation time 44450139 ps
CPU time 0.58 seconds
Started Jun 11 02:16:21 PM PDT 24
Finished Jun 11 02:16:23 PM PDT 24
Peak memory 196344 kb
Host smart-a7a0ae00-3ce2-466d-9d57-e964b7c137e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118174969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1118174969
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.1970981936
Short name T33
Test name
Test status
Simulation time 3787660679 ps
CPU time 52.6 seconds
Started Jun 11 02:16:21 PM PDT 24
Finished Jun 11 02:17:16 PM PDT 24
Peak memory 228128 kb
Host smart-3bfa3e36-8a94-47cc-88e7-6059ca195f8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1970981936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.1970981936
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3508862790
Short name T255
Test name
Test status
Simulation time 1127563591 ps
CPU time 21.52 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:16:42 PM PDT 24
Peak memory 200420 kb
Host smart-d9df0298-d277-496a-ad06-f487dc119855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508862790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3508862790
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.604454265
Short name T560
Test name
Test status
Simulation time 866921979 ps
CPU time 125.64 seconds
Started Jun 11 02:16:14 PM PDT 24
Finished Jun 11 02:18:21 PM PDT 24
Peak memory 353244 kb
Host smart-0568118d-1c73-41ee-8f08-c2c5050a78f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=604454265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.604454265
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2365621941
Short name T296
Test name
Test status
Simulation time 5474328570 ps
CPU time 88.26 seconds
Started Jun 11 02:16:21 PM PDT 24
Finished Jun 11 02:17:51 PM PDT 24
Peak memory 200448 kb
Host smart-2be0a5ab-a14c-4cb2-8b10-2a92cf6e0c66
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365621941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2365621941
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2189410087
Short name T463
Test name
Test status
Simulation time 303740082 ps
CPU time 2.12 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:16:22 PM PDT 24
Peak memory 200336 kb
Host smart-c3e116d7-d8e7-42e4-9865-39e9c5594252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189410087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2189410087
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4065759299
Short name T185
Test name
Test status
Simulation time 120872151 ps
CPU time 4.23 seconds
Started Jun 11 02:16:18 PM PDT 24
Finished Jun 11 02:16:23 PM PDT 24
Peak memory 200348 kb
Host smart-427babf7-2cf5-4aa4-a1f3-e505ad736509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065759299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4065759299
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.1994376155
Short name T428
Test name
Test status
Simulation time 698415899 ps
CPU time 79.93 seconds
Started Jun 11 02:16:20 PM PDT 24
Finished Jun 11 02:17:42 PM PDT 24
Peak memory 476020 kb
Host smart-6f374dbd-0291-487f-82b7-3a0dd953da9b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994376155 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.1994376155
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.3179318765
Short name T415
Test name
Test status
Simulation time 146959830 ps
CPU time 1.3 seconds
Started Jun 11 02:16:18 PM PDT 24
Finished Jun 11 02:16:21 PM PDT 24
Peak memory 200400 kb
Host smart-0bb11b98-d51c-4183-a127-c984e1f4ace5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179318765 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.hmac_test_hmac_vectors.3179318765
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.2035531875
Short name T559
Test name
Test status
Simulation time 53593850659 ps
CPU time 471.66 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:24:12 PM PDT 24
Peak memory 200424 kb
Host smart-17af0ffc-e0fc-4c98-b556-0b4a9767364f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035531875 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.2035531875
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.315765863
Short name T186
Test name
Test status
Simulation time 6015902568 ps
CPU time 108.93 seconds
Started Jun 11 02:16:22 PM PDT 24
Finished Jun 11 02:18:13 PM PDT 24
Peak memory 200500 kb
Host smart-a0a748f6-4b37-4b04-a21e-62c30561dfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315765863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.315765863
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2170623530
Short name T392
Test name
Test status
Simulation time 36799823 ps
CPU time 0.6 seconds
Started Jun 11 02:16:21 PM PDT 24
Finished Jun 11 02:16:24 PM PDT 24
Peak memory 196424 kb
Host smart-7e1ff9e4-0b5d-42fd-b29a-a443f93bc6e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170623530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2170623530
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.1760513473
Short name T228
Test name
Test status
Simulation time 900813080 ps
CPU time 46.05 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:17:06 PM PDT 24
Peak memory 215848 kb
Host smart-148ea739-9fd8-46d1-8253-74e64d61e3dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760513473 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.1760513473
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1234545764
Short name T136
Test name
Test status
Simulation time 4082286291 ps
CPU time 57.87 seconds
Started Jun 11 02:16:21 PM PDT 24
Finished Jun 11 02:17:21 PM PDT 24
Peak memory 200500 kb
Host smart-2ae4b8e2-edbc-47b8-adfd-ac81eadce668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234545764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1234545764
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.2485109951
Short name T177
Test name
Test status
Simulation time 45957483 ps
CPU time 0.86 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:16:22 PM PDT 24
Peak memory 216444 kb
Host smart-79e21549-b4f8-40e0-8c0c-67d1946a05de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2485109951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.2485109951
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.379446994
Short name T270
Test name
Test status
Simulation time 4083717271 ps
CPU time 72.18 seconds
Started Jun 11 02:16:24 PM PDT 24
Finished Jun 11 02:17:37 PM PDT 24
Peak memory 200540 kb
Host smart-657a2aa0-9af8-4676-8e31-ad38e27c946a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379446994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.379446994
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.2731311544
Short name T543
Test name
Test status
Simulation time 78466702122 ps
CPU time 89.35 seconds
Started Jun 11 02:16:18 PM PDT 24
Finished Jun 11 02:17:49 PM PDT 24
Peak memory 200512 kb
Host smart-2fdd0605-36e8-4cd4-80af-200dbee0cbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731311544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.2731311544
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.3308603789
Short name T332
Test name
Test status
Simulation time 235089940 ps
CPU time 1.89 seconds
Started Jun 11 02:16:21 PM PDT 24
Finished Jun 11 02:16:24 PM PDT 24
Peak memory 200500 kb
Host smart-9e7f97ec-c6a2-43c7-ac21-3b4d3132e31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308603789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.3308603789
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1435676391
Short name T106
Test name
Test status
Simulation time 135651858099 ps
CPU time 1829.3 seconds
Started Jun 11 02:16:21 PM PDT 24
Finished Jun 11 02:46:52 PM PDT 24
Peak memory 799784 kb
Host smart-af586acc-50c7-4622-8ab3-5758463e0be9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435676391 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1435676391
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2824798646
Short name T307
Test name
Test status
Simulation time 252201958 ps
CPU time 1.32 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:16:22 PM PDT 24
Peak memory 200688 kb
Host smart-a4973ddf-1add-4977-beb6-2a36fa8beb59
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824798646 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2824798646
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.2756765834
Short name T452
Test name
Test status
Simulation time 43665171990 ps
CPU time 568.2 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:25:49 PM PDT 24
Peak memory 200452 kb
Host smart-a9173586-6e3c-4e80-9a01-6fc33f7d2ee3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756765834 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.2756765834
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.747289395
Short name T222
Test name
Test status
Simulation time 24783040185 ps
CPU time 81.93 seconds
Started Jun 11 02:16:27 PM PDT 24
Finished Jun 11 02:17:50 PM PDT 24
Peak memory 200492 kb
Host smart-22476d97-d84a-4215-b23e-dfc5235bc235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747289395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.747289395
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.1624010733
Short name T171
Test name
Test status
Simulation time 41473343 ps
CPU time 0.58 seconds
Started Jun 11 02:16:37 PM PDT 24
Finished Jun 11 02:16:39 PM PDT 24
Peak memory 197056 kb
Host smart-7dd30ca1-9b36-42fb-9196-2fd5489b6132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624010733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.1624010733
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.193264586
Short name T409
Test name
Test status
Simulation time 2066392347 ps
CPU time 55.54 seconds
Started Jun 11 02:16:20 PM PDT 24
Finished Jun 11 02:17:17 PM PDT 24
Peak memory 227020 kb
Host smart-952ac2b4-ecf8-4909-956e-e154aee7e531
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193264586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.193264586
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.335481979
Short name T69
Test name
Test status
Simulation time 3929799962 ps
CPU time 52.6 seconds
Started Jun 11 02:16:19 PM PDT 24
Finished Jun 11 02:17:13 PM PDT 24
Peak memory 200364 kb
Host smart-419b5863-09b5-42c9-a5a4-995cb87693d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335481979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.335481979
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3543355423
Short name T423
Test name
Test status
Simulation time 4403655525 ps
CPU time 1207.46 seconds
Started Jun 11 02:16:20 PM PDT 24
Finished Jun 11 02:36:29 PM PDT 24
Peak memory 758748 kb
Host smart-7eda2514-d08a-4ba5-9765-904b31c66744
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543355423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3543355423
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.810565977
Short name T155
Test name
Test status
Simulation time 154936776 ps
CPU time 8.41 seconds
Started Jun 11 02:16:30 PM PDT 24
Finished Jun 11 02:16:40 PM PDT 24
Peak memory 200436 kb
Host smart-a75736cb-44a4-4073-8490-05f5b578585d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810565977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.810565977
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3855589294
Short name T556
Test name
Test status
Simulation time 1134949609 ps
CPU time 19.05 seconds
Started Jun 11 02:16:21 PM PDT 24
Finished Jun 11 02:16:41 PM PDT 24
Peak memory 200444 kb
Host smart-1421a789-96e3-47d6-882b-5f621ff52e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855589294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3855589294
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.3331467247
Short name T391
Test name
Test status
Simulation time 210953141 ps
CPU time 7 seconds
Started Jun 11 02:16:17 PM PDT 24
Finished Jun 11 02:16:26 PM PDT 24
Peak memory 200420 kb
Host smart-f0e02b12-607d-4261-84e2-5e4179c3e591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331467247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.3331467247
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.382389472
Short name T279
Test name
Test status
Simulation time 16652219676 ps
CPU time 1825.23 seconds
Started Jun 11 02:16:37 PM PDT 24
Finished Jun 11 02:47:03 PM PDT 24
Peak memory 765928 kb
Host smart-72f88042-e5ae-4def-8c06-07e22076f06f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382389472 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.382389472
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.3997882970
Short name T300
Test name
Test status
Simulation time 127402686 ps
CPU time 1.34 seconds
Started Jun 11 02:16:32 PM PDT 24
Finished Jun 11 02:16:35 PM PDT 24
Peak memory 200372 kb
Host smart-2a985335-b67a-464b-b40c-1cb3f04f5c8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997882970 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.3997882970
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2640799649
Short name T333
Test name
Test status
Simulation time 34457949555 ps
CPU time 509.81 seconds
Started Jun 11 02:16:32 PM PDT 24
Finished Jun 11 02:25:04 PM PDT 24
Peak memory 200624 kb
Host smart-93169ff4-603b-470d-a204-d53e356b7fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640799649 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.2640799649
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.1687602921
Short name T272
Test name
Test status
Simulation time 4718653841 ps
CPU time 84.06 seconds
Started Jun 11 02:16:28 PM PDT 24
Finished Jun 11 02:17:53 PM PDT 24
Peak memory 200500 kb
Host smart-efeaff97-6a5a-4854-a718-8776e364101d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687602921 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.1687602921
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.3215984586
Short name T195
Test name
Test status
Simulation time 12448108 ps
CPU time 0.59 seconds
Started Jun 11 02:16:28 PM PDT 24
Finished Jun 11 02:16:30 PM PDT 24
Peak memory 195408 kb
Host smart-1911fbf3-be3c-4cd8-8713-806cf2aa7eca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215984586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.3215984586
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.169758972
Short name T154
Test name
Test status
Simulation time 474365895 ps
CPU time 10.59 seconds
Started Jun 11 02:16:29 PM PDT 24
Finished Jun 11 02:16:41 PM PDT 24
Peak memory 208656 kb
Host smart-76f72dca-f7d2-4008-8ffe-abcd392d3aca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=169758972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.169758972
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1707313969
Short name T564
Test name
Test status
Simulation time 1417104568 ps
CPU time 18.92 seconds
Started Jun 11 02:16:35 PM PDT 24
Finished Jun 11 02:16:55 PM PDT 24
Peak memory 200420 kb
Host smart-6c0657cb-a204-4254-b27d-ec6ba4e3f8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707313969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1707313969
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.2183612535
Short name T237
Test name
Test status
Simulation time 782193889 ps
CPU time 11.74 seconds
Started Jun 11 02:16:28 PM PDT 24
Finished Jun 11 02:16:41 PM PDT 24
Peak memory 225892 kb
Host smart-d70c2072-376a-41c4-a3b9-95b2a79d7cd7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183612535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.2183612535
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.3121265872
Short name T546
Test name
Test status
Simulation time 577966793 ps
CPU time 15.29 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:16:54 PM PDT 24
Peak memory 200432 kb
Host smart-846438ea-521d-4a9b-b3be-aaef3a78e352
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121265872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.3121265872
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.2425871309
Short name T2
Test name
Test status
Simulation time 70009583791 ps
CPU time 123.28 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:18:43 PM PDT 24
Peak memory 200436 kb
Host smart-8f40303a-1bb7-4f3b-9cc1-3ed592ded343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425871309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.2425871309
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.255525138
Short name T288
Test name
Test status
Simulation time 214990939 ps
CPU time 1.69 seconds
Started Jun 11 02:16:28 PM PDT 24
Finished Jun 11 02:16:31 PM PDT 24
Peak memory 200456 kb
Host smart-1bd166a6-6f46-4e80-9954-99543832c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255525138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.255525138
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.3160048034
Short name T201
Test name
Test status
Simulation time 2941313068 ps
CPU time 29.53 seconds
Started Jun 11 02:16:32 PM PDT 24
Finished Jun 11 02:17:03 PM PDT 24
Peak memory 200692 kb
Host smart-269f2c9f-5079-4803-9201-58a7b578766d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160048034 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.3160048034
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1992976443
Short name T482
Test name
Test status
Simulation time 211128782 ps
CPU time 1.08 seconds
Started Jun 11 02:16:29 PM PDT 24
Finished Jun 11 02:16:31 PM PDT 24
Peak memory 200296 kb
Host smart-d53822fb-e9d4-4250-9f32-318ac76601d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992976443 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1992976443
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.2637680304
Short name T48
Test name
Test status
Simulation time 431737689612 ps
CPU time 510.61 seconds
Started Jun 11 02:16:29 PM PDT 24
Finished Jun 11 02:25:01 PM PDT 24
Peak memory 200448 kb
Host smart-dd59fc45-b11b-47d0-8f8f-ffb72057acb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637680304 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.2637680304
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2976714589
Short name T464
Test name
Test status
Simulation time 672341449 ps
CPU time 10.13 seconds
Started Jun 11 02:16:37 PM PDT 24
Finished Jun 11 02:16:48 PM PDT 24
Peak memory 200380 kb
Host smart-9cedc16b-a50e-40cb-a419-37ad14d91d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976714589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2976714589
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1126249434
Short name T123
Test name
Test status
Simulation time 37923702 ps
CPU time 0.59 seconds
Started Jun 11 02:16:42 PM PDT 24
Finished Jun 11 02:16:44 PM PDT 24
Peak memory 195968 kb
Host smart-f73c07ac-376b-4f7d-a61b-8051e308a7da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126249434 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1126249434
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.2990694547
Short name T570
Test name
Test status
Simulation time 2950034648 ps
CPU time 35.19 seconds
Started Jun 11 02:16:31 PM PDT 24
Finished Jun 11 02:17:08 PM PDT 24
Peak memory 216896 kb
Host smart-5275bd68-f941-4598-a4ee-450da88b2312
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990694547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.2990694547
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1783857804
Short name T434
Test name
Test status
Simulation time 232694306 ps
CPU time 12.85 seconds
Started Jun 11 02:16:30 PM PDT 24
Finished Jun 11 02:16:45 PM PDT 24
Peak memory 200348 kb
Host smart-405c0a59-0772-4178-91fe-9975da9cd537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783857804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1783857804
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.1624458876
Short name T324
Test name
Test status
Simulation time 5315244635 ps
CPU time 575.32 seconds
Started Jun 11 02:16:28 PM PDT 24
Finished Jun 11 02:26:05 PM PDT 24
Peak memory 643556 kb
Host smart-34f1159d-7114-4a13-95c1-d625144aeac0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624458876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.1624458876
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.3927670847
Short name T248
Test name
Test status
Simulation time 110402183 ps
CPU time 3.57 seconds
Started Jun 11 02:16:31 PM PDT 24
Finished Jun 11 02:16:36 PM PDT 24
Peak memory 200272 kb
Host smart-9a61b3b4-7fa5-45c3-b6f0-2c9c036022da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927670847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.3927670847
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3951778515
Short name T124
Test name
Test status
Simulation time 229907949 ps
CPU time 14.51 seconds
Started Jun 11 02:16:35 PM PDT 24
Finished Jun 11 02:16:52 PM PDT 24
Peak memory 200416 kb
Host smart-513cc040-b934-4666-9c17-2c838a4a3b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951778515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3951778515
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.3792912777
Short name T516
Test name
Test status
Simulation time 2950906169 ps
CPU time 12.58 seconds
Started Jun 11 02:16:29 PM PDT 24
Finished Jun 11 02:16:43 PM PDT 24
Peak memory 200516 kb
Host smart-0b6cd279-733c-400c-a920-41aca22f25c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792912777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.3792912777
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3101026914
Short name T12
Test name
Test status
Simulation time 209095741440 ps
CPU time 854.25 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:30:54 PM PDT 24
Peak memory 200528 kb
Host smart-5bec6327-166a-414e-83a6-ae7659712afe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101026914 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3101026914
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.3083800421
Short name T165
Test name
Test status
Simulation time 115058142 ps
CPU time 1.15 seconds
Started Jun 11 02:16:31 PM PDT 24
Finished Jun 11 02:16:34 PM PDT 24
Peak memory 200384 kb
Host smart-6f813354-adab-4fee-95fc-194e6a029970
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083800421 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.3083800421
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3207599430
Short name T426
Test name
Test status
Simulation time 84096315825 ps
CPU time 547.03 seconds
Started Jun 11 02:16:31 PM PDT 24
Finished Jun 11 02:25:40 PM PDT 24
Peak memory 200408 kb
Host smart-a8f7e01a-e213-403d-91d8-45d7d566ffab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207599430 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3207599430
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.290150403
Short name T223
Test name
Test status
Simulation time 4809065180 ps
CPU time 24.69 seconds
Started Jun 11 02:16:28 PM PDT 24
Finished Jun 11 02:16:54 PM PDT 24
Peak memory 200496 kb
Host smart-e7a48d0d-e17d-411c-999a-08db6a769c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290150403 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.290150403
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2147875127
Short name T572
Test name
Test status
Simulation time 44540591 ps
CPU time 0.59 seconds
Started Jun 11 02:16:39 PM PDT 24
Finished Jun 11 02:16:41 PM PDT 24
Peak memory 196376 kb
Host smart-cbfb7f52-cab9-4097-b63b-8dfba6fbda83
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147875127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2147875127
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.2720237442
Short name T400
Test name
Test status
Simulation time 3316130160 ps
CPU time 43.25 seconds
Started Jun 11 02:16:39 PM PDT 24
Finished Jun 11 02:17:23 PM PDT 24
Peak memory 222016 kb
Host smart-a3847180-99a5-4d10-9618-d773b023ecac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2720237442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.2720237442
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1275669618
Short name T208
Test name
Test status
Simulation time 1143406075 ps
CPU time 23.03 seconds
Started Jun 11 02:16:44 PM PDT 24
Finished Jun 11 02:17:07 PM PDT 24
Peak memory 200372 kb
Host smart-b39483fc-cd34-4a71-9926-9ed637770ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275669618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1275669618
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2418466983
Short name T397
Test name
Test status
Simulation time 12148731613 ps
CPU time 513.49 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:25:12 PM PDT 24
Peak memory 719524 kb
Host smart-5fed3014-4801-435d-bcff-5db75041f331
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2418466983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2418466983
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.3133453733
Short name T330
Test name
Test status
Simulation time 12388288081 ps
CPU time 159.69 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:19:19 PM PDT 24
Peak memory 200472 kb
Host smart-dc6af19a-3f8a-4bf8-9c1c-28a7b1634837
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133453733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.3133453733
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3200891189
Short name T528
Test name
Test status
Simulation time 1311719614 ps
CPU time 13.41 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:16:52 PM PDT 24
Peak memory 200312 kb
Host smart-14695f3a-d5f6-4575-a85a-9cd7f668a845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200891189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3200891189
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.2535611727
Short name T151
Test name
Test status
Simulation time 2404055764 ps
CPU time 7.79 seconds
Started Jun 11 02:16:40 PM PDT 24
Finished Jun 11 02:16:49 PM PDT 24
Peak memory 200564 kb
Host smart-7b0040ea-dc0c-4e46-b394-fb63522b74d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535611727 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.2535611727
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.850119132
Short name T370
Test name
Test status
Simulation time 1140062966 ps
CPU time 32.13 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:17:12 PM PDT 24
Peak memory 226432 kb
Host smart-56896fe3-386a-4c37-9957-c971b01f4323
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850119132 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.850119132
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.2663635659
Short name T495
Test name
Test status
Simulation time 241198545 ps
CPU time 1.25 seconds
Started Jun 11 02:16:40 PM PDT 24
Finished Jun 11 02:16:42 PM PDT 24
Peak memory 200452 kb
Host smart-ec3fa028-df28-4d7e-bef1-d3a4ed14ab07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663635659 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.2663635659
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.1509516542
Short name T261
Test name
Test status
Simulation time 45073927075 ps
CPU time 444.99 seconds
Started Jun 11 02:16:39 PM PDT 24
Finished Jun 11 02:24:05 PM PDT 24
Peak memory 200364 kb
Host smart-c05e43fa-795c-408c-ac1f-bb063c4bc0c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509516542 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.1509516542
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3658311591
Short name T354
Test name
Test status
Simulation time 6139902997 ps
CPU time 89.75 seconds
Started Jun 11 02:16:39 PM PDT 24
Finished Jun 11 02:18:10 PM PDT 24
Peak memory 200540 kb
Host smart-52bb6dfa-0207-44f4-9a98-9ac3692845ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658311591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3658311591
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.259675540
Short name T319
Test name
Test status
Simulation time 13689737 ps
CPU time 0.55 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:16:39 PM PDT 24
Peak memory 195204 kb
Host smart-eaf830ff-3fa2-42a0-8e8a-c8d249f62aa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259675540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.259675540
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.1540571725
Short name T212
Test name
Test status
Simulation time 3991415569 ps
CPU time 56.24 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:17:36 PM PDT 24
Peak memory 240404 kb
Host smart-c9bb6c98-2c49-4ef3-a065-c3a6b5b1f327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540571725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.1540571725
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.710505428
Short name T501
Test name
Test status
Simulation time 3969775836 ps
CPU time 55.69 seconds
Started Jun 11 02:16:40 PM PDT 24
Finished Jun 11 02:17:37 PM PDT 24
Peak memory 200544 kb
Host smart-12d13943-0160-439c-8327-4f11a15aff28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710505428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.710505428
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.754831570
Short name T125
Test name
Test status
Simulation time 4005213495 ps
CPU time 412.71 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:23:32 PM PDT 24
Peak memory 681048 kb
Host smart-2dfb2a85-8f24-4473-bd82-7a50b46fdfd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=754831570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.754831570
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.698482291
Short name T550
Test name
Test status
Simulation time 3408613487 ps
CPU time 46.33 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:17:26 PM PDT 24
Peak memory 200416 kb
Host smart-01779c43-76dc-45c6-9e3f-e882f0e12133
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698482291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.698482291
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.2015479913
Short name T341
Test name
Test status
Simulation time 6008180757 ps
CPU time 89.02 seconds
Started Jun 11 02:16:41 PM PDT 24
Finished Jun 11 02:18:11 PM PDT 24
Peak memory 200696 kb
Host smart-d0c80e89-c4f0-4cbb-8728-9b9edbc9facd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015479913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.2015479913
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.2051483264
Short name T302
Test name
Test status
Simulation time 726010098 ps
CPU time 5.61 seconds
Started Jun 11 02:16:40 PM PDT 24
Finished Jun 11 02:16:47 PM PDT 24
Peak memory 200456 kb
Host smart-43de1aca-2954-4ca8-bb2d-976d6870a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051483264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.2051483264
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.602452160
Short name T226
Test name
Test status
Simulation time 11562411497 ps
CPU time 622.65 seconds
Started Jun 11 02:16:42 PM PDT 24
Finished Jun 11 02:27:06 PM PDT 24
Peak memory 200500 kb
Host smart-49071033-796c-467d-900f-2b4886a806bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602452160 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.602452160
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.1461466767
Short name T326
Test name
Test status
Simulation time 358796000 ps
CPU time 1.13 seconds
Started Jun 11 02:16:40 PM PDT 24
Finished Jun 11 02:16:42 PM PDT 24
Peak memory 200236 kb
Host smart-318d5bdb-cc98-4da5-990a-02d539c91057
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461466767 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.1461466767
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.1408429455
Short name T156
Test name
Test status
Simulation time 54967753601 ps
CPU time 452.51 seconds
Started Jun 11 02:16:40 PM PDT 24
Finished Jun 11 02:24:13 PM PDT 24
Peak memory 200468 kb
Host smart-6f06bb60-1f19-40b8-b47c-ba21095ac28a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408429455 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.1408429455
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.1123645900
Short name T487
Test name
Test status
Simulation time 12730105234 ps
CPU time 82.62 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:18:02 PM PDT 24
Peak memory 200552 kb
Host smart-624a177b-70c3-4e79-845a-73090f7c509a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123645900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.1123645900
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.4005800657
Short name T352
Test name
Test status
Simulation time 22488814 ps
CPU time 0.63 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:16:51 PM PDT 24
Peak memory 195344 kb
Host smart-0494b456-5070-493d-a07d-8325eab0687c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005800657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.4005800657
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.4221944289
Short name T29
Test name
Test status
Simulation time 305731381 ps
CPU time 8.55 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:16:57 PM PDT 24
Peak memory 216668 kb
Host smart-726d2c36-6ad7-4465-975b-565764253525
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221944289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.4221944289
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3721183048
Short name T115
Test name
Test status
Simulation time 1031671657 ps
CPU time 57.61 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:17:48 PM PDT 24
Peak memory 200500 kb
Host smart-68b554b6-6b25-434b-9a9f-42b049799742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721183048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3721183048
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.2147776809
Short name T25
Test name
Test status
Simulation time 16017026745 ps
CPU time 1154.29 seconds
Started Jun 11 02:16:53 PM PDT 24
Finished Jun 11 02:36:09 PM PDT 24
Peak memory 746232 kb
Host smart-a84b4b55-535f-469a-9b90-790fe93af77f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2147776809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.2147776809
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.2492771878
Short name T356
Test name
Test status
Simulation time 17580699048 ps
CPU time 186.1 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:19:57 PM PDT 24
Peak memory 200532 kb
Host smart-17de9d0c-e670-4f87-8ad5-0012ae259e70
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492771878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.2492771878
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1098250386
Short name T274
Test name
Test status
Simulation time 4896796933 ps
CPU time 25.66 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:17:15 PM PDT 24
Peak memory 200472 kb
Host smart-0cf1573d-db2e-457e-9717-3ac4fcc24b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098250386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1098250386
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1719138641
Short name T310
Test name
Test status
Simulation time 199387388 ps
CPU time 3.52 seconds
Started Jun 11 02:16:38 PM PDT 24
Finished Jun 11 02:16:42 PM PDT 24
Peak memory 200456 kb
Host smart-f0abcf06-a0c9-425f-bf9f-232c5c202348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719138641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1719138641
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3736453274
Short name T527
Test name
Test status
Simulation time 20293845127 ps
CPU time 193.71 seconds
Started Jun 11 02:16:47 PM PDT 24
Finished Jun 11 02:20:02 PM PDT 24
Peak memory 200432 kb
Host smart-06e22592-f3b9-4654-be79-f806cd49f011
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736453274 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3736453274
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2602070550
Short name T432
Test name
Test status
Simulation time 61325175 ps
CPU time 1.43 seconds
Started Jun 11 02:16:50 PM PDT 24
Finished Jun 11 02:16:52 PM PDT 24
Peak memory 200380 kb
Host smart-2e6e799b-227a-4cd9-8b2f-385606991ee9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602070550 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2602070550
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.3413467331
Short name T220
Test name
Test status
Simulation time 42546341676 ps
CPU time 426 seconds
Started Jun 11 02:16:50 PM PDT 24
Finished Jun 11 02:23:58 PM PDT 24
Peak memory 200372 kb
Host smart-8b6c2d45-a799-49bf-a05d-6efc9be926e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413467331 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.3413467331
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3318284847
Short name T491
Test name
Test status
Simulation time 5351654057 ps
CPU time 99.82 seconds
Started Jun 11 02:16:51 PM PDT 24
Finished Jun 11 02:18:32 PM PDT 24
Peak memory 200496 kb
Host smart-16f0fc27-3dc4-4383-9fb8-e59916b832c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318284847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3318284847
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.488999918
Short name T374
Test name
Test status
Simulation time 36106052 ps
CPU time 0.63 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:15:34 PM PDT 24
Peak memory 197292 kb
Host smart-403f5e6c-11a6-4c53-b237-e75d85b3f480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488999918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.488999918
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.2342918068
Short name T542
Test name
Test status
Simulation time 1368050820 ps
CPU time 28.72 seconds
Started Jun 11 02:15:36 PM PDT 24
Finished Jun 11 02:16:06 PM PDT 24
Peak memory 209632 kb
Host smart-0b73f2aa-dbb7-412a-a3e9-40c334fcd992
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2342918068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.2342918068
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.721344587
Short name T466
Test name
Test status
Simulation time 1229576984 ps
CPU time 42.82 seconds
Started Jun 11 02:15:32 PM PDT 24
Finished Jun 11 02:16:17 PM PDT 24
Peak memory 200432 kb
Host smart-8e1b7edd-476d-471f-9145-512eeb7f8521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721344587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.721344587
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.3176177323
Short name T198
Test name
Test status
Simulation time 2678518730 ps
CPU time 131.28 seconds
Started Jun 11 02:15:28 PM PDT 24
Finished Jun 11 02:17:40 PM PDT 24
Peak memory 483284 kb
Host smart-e64e1f64-6808-4fdd-a1e0-894b0c87604a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3176177323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.3176177323
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.870604976
Short name T441
Test name
Test status
Simulation time 5811575634 ps
CPU time 38.87 seconds
Started Jun 11 02:15:28 PM PDT 24
Finished Jun 11 02:16:08 PM PDT 24
Peak memory 200520 kb
Host smart-03a85aaf-5d42-4c21-8562-7a8469c58014
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870604976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.870604976
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1510021431
Short name T144
Test name
Test status
Simulation time 6809695012 ps
CPU time 62.15 seconds
Started Jun 11 02:15:29 PM PDT 24
Finished Jun 11 02:16:32 PM PDT 24
Peak memory 200496 kb
Host smart-d7c91ddc-6420-4beb-8fc5-1459de1756a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510021431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1510021431
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.1444185846
Short name T23
Test name
Test status
Simulation time 39856393 ps
CPU time 0.83 seconds
Started Jun 11 02:15:32 PM PDT 24
Finished Jun 11 02:15:35 PM PDT 24
Peak memory 218928 kb
Host smart-bc84b49c-4582-488f-a684-1f471fb0b6b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444185846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.1444185846
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2310877385
Short name T385
Test name
Test status
Simulation time 1225534128 ps
CPU time 6.27 seconds
Started Jun 11 02:15:36 PM PDT 24
Finished Jun 11 02:15:44 PM PDT 24
Peak memory 200416 kb
Host smart-f53d4cf8-7a3a-4c04-ac83-124bafc7e5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310877385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2310877385
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.168585611
Short name T481
Test name
Test status
Simulation time 80640655 ps
CPU time 1.43 seconds
Started Jun 11 02:15:30 PM PDT 24
Finished Jun 11 02:15:33 PM PDT 24
Peak memory 200456 kb
Host smart-05196275-3160-4a9e-842a-d64f9efd0000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168585611 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.hmac_test_hmac_vectors.168585611
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.2050781579
Short name T13
Test name
Test status
Simulation time 38290142524 ps
CPU time 525.96 seconds
Started Jun 11 02:15:34 PM PDT 24
Finished Jun 11 02:24:22 PM PDT 24
Peak memory 200500 kb
Host smart-84b1a7a1-6ebd-4a2f-9d5b-a96b2716e4fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050781579 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.2050781579
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1380264531
Short name T395
Test name
Test status
Simulation time 625342987 ps
CPU time 33.91 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:16:07 PM PDT 24
Peak memory 200456 kb
Host smart-1006be59-c341-4e7b-af70-48beaf41fbc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380264531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1380264531
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2843301716
Short name T378
Test name
Test status
Simulation time 31796866 ps
CPU time 0.61 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:16:51 PM PDT 24
Peak memory 196324 kb
Host smart-c8057638-6769-40d7-a120-a5725b9a0a9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843301716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2843301716
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1598514386
Short name T246
Test name
Test status
Simulation time 645166703 ps
CPU time 16.86 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:17:06 PM PDT 24
Peak memory 216784 kb
Host smart-19ae1c3f-4546-47c2-84b9-bc6ac7e47f7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1598514386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1598514386
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.70430115
Short name T64
Test name
Test status
Simulation time 3764128514 ps
CPU time 10.95 seconds
Started Jun 11 02:16:50 PM PDT 24
Finished Jun 11 02:17:02 PM PDT 24
Peak memory 200396 kb
Host smart-d6fd3fb9-197b-43a3-9c6f-9b2e0975d274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70430115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.70430115
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.303233139
Short name T513
Test name
Test status
Simulation time 2469103974 ps
CPU time 265.15 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:21:15 PM PDT 24
Peak memory 634504 kb
Host smart-ac5d7588-22a5-477f-97ff-d44091a7148d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=303233139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.303233139
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2878931580
Short name T256
Test name
Test status
Simulation time 11825237869 ps
CPU time 159.59 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:19:30 PM PDT 24
Peak memory 200468 kb
Host smart-9ce5bf16-1d6e-44ce-87d3-55fadf6e6599
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878931580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2878931580
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.619801067
Short name T583
Test name
Test status
Simulation time 1452444683 ps
CPU time 37.35 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:17:26 PM PDT 24
Peak memory 200384 kb
Host smart-1bbf4c62-0695-4583-826d-ffdf9244bea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619801067 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.619801067
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.167652063
Short name T118
Test name
Test status
Simulation time 195172008 ps
CPU time 3.4 seconds
Started Jun 11 02:16:47 PM PDT 24
Finished Jun 11 02:16:51 PM PDT 24
Peak memory 200452 kb
Host smart-bb58b6de-664f-4c37-a9b6-cfe10e86e4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167652063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.167652063
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.224878302
Short name T173
Test name
Test status
Simulation time 24038496799 ps
CPU time 1385.12 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:39:55 PM PDT 24
Peak memory 249900 kb
Host smart-2536d269-5edf-40e2-8da6-417caaf360b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224878302 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.224878302
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.636948854
Short name T566
Test name
Test status
Simulation time 159776638 ps
CPU time 1.33 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:16:50 PM PDT 24
Peak memory 200408 kb
Host smart-511d34f7-153b-4a88-8a36-4a6549ff94d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636948854 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.hmac_test_hmac_vectors.636948854
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1228870216
Short name T134
Test name
Test status
Simulation time 8206421654 ps
CPU time 473.66 seconds
Started Jun 11 02:16:50 PM PDT 24
Finished Jun 11 02:24:45 PM PDT 24
Peak memory 200536 kb
Host smart-7c6279b2-6726-419d-aee4-f8830e150ecc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228870216 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.1228870216
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2960028537
Short name T340
Test name
Test status
Simulation time 4739521112 ps
CPU time 62.09 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:17:51 PM PDT 24
Peak memory 200516 kb
Host smart-9583a191-12bf-4f7a-8b64-44b46a8407d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960028537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2960028537
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1201433496
Short name T547
Test name
Test status
Simulation time 48473214 ps
CPU time 0.58 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:16:49 PM PDT 24
Peak memory 195368 kb
Host smart-2185ecdf-d45d-4a0c-9772-0b9e3160fb10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201433496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1201433496
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.133865322
Short name T412
Test name
Test status
Simulation time 2217901814 ps
CPU time 29.3 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:17:20 PM PDT 24
Peak memory 200548 kb
Host smart-4fa5b292-4c17-42fd-a90f-c5ee74572cc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=133865322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.133865322
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.196704167
Short name T430
Test name
Test status
Simulation time 602862448 ps
CPU time 16.68 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:17:06 PM PDT 24
Peak memory 200372 kb
Host smart-884c0369-24a5-4661-ae00-b6ec994e0da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196704167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.196704167
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.283851722
Short name T143
Test name
Test status
Simulation time 1197451450 ps
CPU time 122.4 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:18:53 PM PDT 24
Peak memory 475756 kb
Host smart-3e64fc38-51df-4474-8ef7-dc07fdc06100
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=283851722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.283851722
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.631060023
Short name T421
Test name
Test status
Simulation time 4557241435 ps
CPU time 61.77 seconds
Started Jun 11 02:16:52 PM PDT 24
Finished Jun 11 02:17:55 PM PDT 24
Peak memory 200380 kb
Host smart-f4576e49-6476-4944-b574-4b7899f95f8c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631060023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.631060023
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3321738098
Short name T285
Test name
Test status
Simulation time 5167271635 ps
CPU time 57.93 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:17:48 PM PDT 24
Peak memory 200396 kb
Host smart-d4beb910-bd1b-4133-b153-8f368c706783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321738098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3321738098
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.448580276
Short name T449
Test name
Test status
Simulation time 1336407427 ps
CPU time 8.78 seconds
Started Jun 11 02:16:51 PM PDT 24
Finished Jun 11 02:17:01 PM PDT 24
Peak memory 200472 kb
Host smart-7ac62a17-c6a1-48e6-ab48-cf3fe7db864f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448580276 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.448580276
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.919377219
Short name T94
Test name
Test status
Simulation time 262901697912 ps
CPU time 1721.14 seconds
Started Jun 11 02:16:52 PM PDT 24
Finished Jun 11 02:45:34 PM PDT 24
Peak memory 765084 kb
Host smart-63bf9b04-4b85-4d23-9426-78ab66c5cf53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919377219 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.919377219
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.2505431252
Short name T72
Test name
Test status
Simulation time 28935677 ps
CPU time 1.06 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:16:50 PM PDT 24
Peak memory 200248 kb
Host smart-38f88131-f4e5-4703-a8e9-e0cf7ff87d75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505431252 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.hmac_test_hmac_vectors.2505431252
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.1907149367
Short name T287
Test name
Test status
Simulation time 16901676647 ps
CPU time 503.82 seconds
Started Jun 11 02:16:53 PM PDT 24
Finished Jun 11 02:25:18 PM PDT 24
Peak memory 200312 kb
Host smart-f904c57b-96b9-47f3-a558-cddf5d6f7b42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907149367 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.1907149367
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1764608145
Short name T162
Test name
Test status
Simulation time 1284519448 ps
CPU time 5.3 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:16:56 PM PDT 24
Peak memory 200416 kb
Host smart-106445f1-3820-4ce9-9938-1c380267dc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764608145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1764608145
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.8148793
Short name T224
Test name
Test status
Simulation time 35125235 ps
CPU time 0.57 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:16:50 PM PDT 24
Peak memory 196064 kb
Host smart-d61f9001-8c52-4321-ae80-d11c01474bb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8148793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.8148793
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2513304849
Short name T98
Test name
Test status
Simulation time 919300214 ps
CPU time 50.62 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:17:40 PM PDT 24
Peak memory 233256 kb
Host smart-2ab3839b-d755-4589-8b30-374f3c39664c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2513304849 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2513304849
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.25543929
Short name T555
Test name
Test status
Simulation time 7239163261 ps
CPU time 56.04 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:17:46 PM PDT 24
Peak memory 200556 kb
Host smart-4612dec4-1391-401c-833e-39f2078440b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25543929 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.25543929
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3596339858
Short name T422
Test name
Test status
Simulation time 317829276 ps
CPU time 38.84 seconds
Started Jun 11 02:16:50 PM PDT 24
Finished Jun 11 02:17:30 PM PDT 24
Peak memory 263228 kb
Host smart-102ca157-4a31-409f-a975-c439ac64bb87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3596339858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3596339858
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2416023622
Short name T498
Test name
Test status
Simulation time 4328355609 ps
CPU time 38.14 seconds
Started Jun 11 02:16:51 PM PDT 24
Finished Jun 11 02:17:31 PM PDT 24
Peak memory 200492 kb
Host smart-fd1d4276-1aea-4907-978b-d36fcd034669
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416023622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2416023622
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.282091337
Short name T207
Test name
Test status
Simulation time 152629923 ps
CPU time 5.15 seconds
Started Jun 11 02:16:47 PM PDT 24
Finished Jun 11 02:16:53 PM PDT 24
Peak memory 200436 kb
Host smart-3ee286c2-6e9b-46ce-8c51-c86febbd3d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282091337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.282091337
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1657642034
Short name T514
Test name
Test status
Simulation time 534923523 ps
CPU time 5.5 seconds
Started Jun 11 02:16:51 PM PDT 24
Finished Jun 11 02:16:58 PM PDT 24
Peak memory 200420 kb
Host smart-856a6ad8-6216-44ad-846a-de41bf9d9e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657642034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1657642034
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.1047429013
Short name T299
Test name
Test status
Simulation time 25273514271 ps
CPU time 586.29 seconds
Started Jun 11 02:16:50 PM PDT 24
Finished Jun 11 02:26:38 PM PDT 24
Peak memory 200428 kb
Host smart-49043f61-636f-4436-88ca-764d2955c02e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047429013 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.1047429013
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.1702653942
Short name T552
Test name
Test status
Simulation time 106305207 ps
CPU time 1.15 seconds
Started Jun 11 02:16:51 PM PDT 24
Finished Jun 11 02:16:53 PM PDT 24
Peak memory 200456 kb
Host smart-6f52dcc0-4923-4cba-8165-7c97b058215c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702653942 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.1702653942
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2937714026
Short name T375
Test name
Test status
Simulation time 8719625939 ps
CPU time 507 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:25:17 PM PDT 24
Peak memory 200412 kb
Host smart-2d289b6a-a050-4ad2-8abe-f06144c68ed3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937714026 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2937714026
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.785902691
Short name T150
Test name
Test status
Simulation time 290430828 ps
CPU time 16.97 seconds
Started Jun 11 02:16:48 PM PDT 24
Finished Jun 11 02:17:06 PM PDT 24
Peak memory 200440 kb
Host smart-0492f6cc-5854-41ce-99d7-e5edc18a7e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785902691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.785902691
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1044123397
Short name T178
Test name
Test status
Simulation time 25333907 ps
CPU time 0.61 seconds
Started Jun 11 02:17:01 PM PDT 24
Finished Jun 11 02:17:03 PM PDT 24
Peak memory 196332 kb
Host smart-3be27a8b-2073-49f6-a9e6-91c0b4adc918
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044123397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1044123397
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2368745823
Short name T32
Test name
Test status
Simulation time 628037746 ps
CPU time 28.29 seconds
Started Jun 11 02:16:58 PM PDT 24
Finished Jun 11 02:17:27 PM PDT 24
Peak memory 216792 kb
Host smart-eab7daf0-1610-4e33-a3e4-53ba06ff2971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2368745823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2368745823
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.4017189864
Short name T331
Test name
Test status
Simulation time 7708714962 ps
CPU time 48.28 seconds
Started Jun 11 02:17:07 PM PDT 24
Finished Jun 11 02:17:57 PM PDT 24
Peak memory 200468 kb
Host smart-6a91a8de-1f3c-43da-a232-6390725446dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017189864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.4017189864
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.557772530
Short name T342
Test name
Test status
Simulation time 15492055697 ps
CPU time 562.01 seconds
Started Jun 11 02:16:59 PM PDT 24
Finished Jun 11 02:26:22 PM PDT 24
Peak memory 444884 kb
Host smart-f0cab846-d295-4158-a2ee-6ad23df44c78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=557772530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.557772530
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2928222058
Short name T121
Test name
Test status
Simulation time 7897660733 ps
CPU time 95.6 seconds
Started Jun 11 02:17:00 PM PDT 24
Finished Jun 11 02:18:37 PM PDT 24
Peak memory 200576 kb
Host smart-9383202f-9d3d-4a0f-92c2-1ef02d91aa33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928222058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2928222058
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.3426686041
Short name T503
Test name
Test status
Simulation time 93594746590 ps
CPU time 130.69 seconds
Started Jun 11 02:16:49 PM PDT 24
Finished Jun 11 02:19:01 PM PDT 24
Peak memory 200552 kb
Host smart-6170bccf-438d-4dd7-bcf8-5aa7667edef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426686041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.3426686041
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.38858573
Short name T353
Test name
Test status
Simulation time 136101409 ps
CPU time 5.1 seconds
Started Jun 11 02:16:53 PM PDT 24
Finished Jun 11 02:16:59 PM PDT 24
Peak memory 200636 kb
Host smart-ab627e52-338e-443c-92f6-e823667a7f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38858573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.38858573
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.974564451
Short name T57
Test name
Test status
Simulation time 63028165551 ps
CPU time 896.21 seconds
Started Jun 11 02:16:59 PM PDT 24
Finished Jun 11 02:31:56 PM PDT 24
Peak memory 200592 kb
Host smart-e7698808-f84b-404c-8665-02240c12e4e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974564451 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.974564451
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3281460608
Short name T518
Test name
Test status
Simulation time 148410650 ps
CPU time 1.4 seconds
Started Jun 11 02:17:06 PM PDT 24
Finished Jun 11 02:17:08 PM PDT 24
Peak memory 200468 kb
Host smart-41d005ca-41af-4d72-bbfa-ce7153554d31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281460608 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3281460608
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.2480501243
Short name T168
Test name
Test status
Simulation time 160630414974 ps
CPU time 493.82 seconds
Started Jun 11 02:17:00 PM PDT 24
Finished Jun 11 02:25:15 PM PDT 24
Peak memory 200448 kb
Host smart-7472f9df-d553-4368-b07b-2bdd29f2bf45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480501243 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.2480501243
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3568123558
Short name T517
Test name
Test status
Simulation time 5854998467 ps
CPU time 82.57 seconds
Started Jun 11 02:17:02 PM PDT 24
Finished Jun 11 02:18:26 PM PDT 24
Peak memory 200516 kb
Host smart-410a792a-d3f8-4d00-a504-e09c57d966dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568123558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3568123558
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1098226937
Short name T179
Test name
Test status
Simulation time 40461157 ps
CPU time 0.61 seconds
Started Jun 11 02:17:01 PM PDT 24
Finished Jun 11 02:17:03 PM PDT 24
Peak memory 196404 kb
Host smart-5f7538bc-d159-408f-8da7-7cd030559487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098226937 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1098226937
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.2084961811
Short name T70
Test name
Test status
Simulation time 3358257565 ps
CPU time 39.59 seconds
Started Jun 11 02:16:59 PM PDT 24
Finished Jun 11 02:17:40 PM PDT 24
Peak memory 216520 kb
Host smart-d4e09878-c4c1-406d-a006-700f99f9201e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084961811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.2084961811
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.1283230090
Short name T93
Test name
Test status
Simulation time 1047747858 ps
CPU time 51.4 seconds
Started Jun 11 02:16:59 PM PDT 24
Finished Jun 11 02:17:51 PM PDT 24
Peak memory 200352 kb
Host smart-72ed638c-e0a5-41d2-82e3-2084ad9c8a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283230090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.1283230090
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.4098944046
Short name T532
Test name
Test status
Simulation time 1704452551 ps
CPU time 429.12 seconds
Started Jun 11 02:16:59 PM PDT 24
Finished Jun 11 02:24:09 PM PDT 24
Peak memory 664524 kb
Host smart-f3a32789-a822-41a4-b8fc-c7489bf8a323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4098944046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.4098944046
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3610692061
Short name T233
Test name
Test status
Simulation time 1770409197 ps
CPU time 17.27 seconds
Started Jun 11 02:16:59 PM PDT 24
Finished Jun 11 02:17:17 PM PDT 24
Peak memory 200312 kb
Host smart-0051612c-aef3-410f-adf4-bf6dfcd8da33
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610692061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3610692061
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.133233940
Short name T368
Test name
Test status
Simulation time 2893846408 ps
CPU time 25.58 seconds
Started Jun 11 02:16:59 PM PDT 24
Finished Jun 11 02:17:26 PM PDT 24
Peak memory 200484 kb
Host smart-15a7cd9c-e789-4d98-9cf7-281fd3eb7c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133233940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.133233940
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.644422102
Short name T404
Test name
Test status
Simulation time 2800726596 ps
CPU time 13.6 seconds
Started Jun 11 02:17:01 PM PDT 24
Finished Jun 11 02:17:16 PM PDT 24
Peak memory 200488 kb
Host smart-39a8c0b6-8377-4c09-a478-7728249bcbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644422102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.644422102
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1293107518
Short name T73
Test name
Test status
Simulation time 33839345 ps
CPU time 1.3 seconds
Started Jun 11 02:17:01 PM PDT 24
Finished Jun 11 02:17:03 PM PDT 24
Peak memory 200444 kb
Host smart-e8fbc20d-3749-40cf-a824-77f1d3282fb4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293107518 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1293107518
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.1350897997
Short name T232
Test name
Test status
Simulation time 25673885728 ps
CPU time 472.68 seconds
Started Jun 11 02:17:01 PM PDT 24
Finished Jun 11 02:24:54 PM PDT 24
Peak memory 200424 kb
Host smart-06a12623-b557-4cdb-ab67-d3cd80dd3ecb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350897997 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.1350897997
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.247974992
Short name T271
Test name
Test status
Simulation time 4330002564 ps
CPU time 60.47 seconds
Started Jun 11 02:16:59 PM PDT 24
Finished Jun 11 02:18:00 PM PDT 24
Peak memory 200432 kb
Host smart-5c261b9c-8bbe-445c-97dd-553330a9b95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247974992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.247974992
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.1927034231
Short name T337
Test name
Test status
Simulation time 14130742 ps
CPU time 0.58 seconds
Started Jun 11 02:16:57 PM PDT 24
Finished Jun 11 02:16:58 PM PDT 24
Peak memory 195400 kb
Host smart-48452eef-9050-4714-b7f6-a92317c93283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927034231 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.1927034231
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.2522860704
Short name T361
Test name
Test status
Simulation time 3749348679 ps
CPU time 42.24 seconds
Started Jun 11 02:17:02 PM PDT 24
Finished Jun 11 02:17:45 PM PDT 24
Peak memory 220812 kb
Host smart-8d3833bb-d854-4059-9b84-1bceb2f9ef92
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2522860704 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.2522860704
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2010380305
Short name T262
Test name
Test status
Simulation time 1076910712 ps
CPU time 59.66 seconds
Started Jun 11 02:16:59 PM PDT 24
Finished Jun 11 02:17:59 PM PDT 24
Peak memory 200452 kb
Host smart-492f92a2-5e58-49a3-9acc-9d0204a04b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010380305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2010380305
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.3805491427
Short name T325
Test name
Test status
Simulation time 851489217 ps
CPU time 25.27 seconds
Started Jun 11 02:16:58 PM PDT 24
Finished Jun 11 02:17:24 PM PDT 24
Peak memory 254428 kb
Host smart-155d2e73-6885-43bd-83fa-6b702bb57536
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3805491427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.3805491427
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.1386751037
Short name T120
Test name
Test status
Simulation time 49076364737 ps
CPU time 239.07 seconds
Started Jun 11 02:17:00 PM PDT 24
Finished Jun 11 02:21:00 PM PDT 24
Peak memory 200408 kb
Host smart-31ff94ce-2bd5-4452-b914-74ecca50a72c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386751037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.1386751037
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.4057825255
Short name T545
Test name
Test status
Simulation time 4580682368 ps
CPU time 67.56 seconds
Started Jun 11 02:17:02 PM PDT 24
Finished Jun 11 02:18:10 PM PDT 24
Peak memory 200496 kb
Host smart-3e1d4883-e51d-4cd9-ad37-ade89732f34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057825255 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.4057825255
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.3767411883
Short name T26
Test name
Test status
Simulation time 430276623 ps
CPU time 6.36 seconds
Started Jun 11 02:17:02 PM PDT 24
Finished Jun 11 02:17:09 PM PDT 24
Peak memory 200504 kb
Host smart-e1599696-394f-4c29-8e66-c0d7dbb0ff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767411883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.3767411883
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.664826854
Short name T586
Test name
Test status
Simulation time 244465199458 ps
CPU time 1991.72 seconds
Started Jun 11 02:17:02 PM PDT 24
Finished Jun 11 02:50:15 PM PDT 24
Peak memory 809152 kb
Host smart-75929621-6368-48d0-9f46-38c8c6c8d4ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664826854 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.664826854
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.2033957784
Short name T465
Test name
Test status
Simulation time 82346536 ps
CPU time 1.43 seconds
Started Jun 11 02:17:01 PM PDT 24
Finished Jun 11 02:17:03 PM PDT 24
Peak memory 200436 kb
Host smart-7b1630cb-635b-4373-91a1-aefb745a86f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033957784 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.2033957784
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.2226512212
Short name T90
Test name
Test status
Simulation time 28324450472 ps
CPU time 505.77 seconds
Started Jun 11 02:17:00 PM PDT 24
Finished Jun 11 02:25:27 PM PDT 24
Peak memory 200404 kb
Host smart-c6497b0d-b23d-4a30-b3d6-7050479d0d4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226512212 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.2226512212
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4218306785
Short name T406
Test name
Test status
Simulation time 7462378720 ps
CPU time 36.49 seconds
Started Jun 11 02:16:59 PM PDT 24
Finished Jun 11 02:17:36 PM PDT 24
Peak memory 200472 kb
Host smart-12526ef4-0407-4554-a9ab-c52c6910fc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218306785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4218306785
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.559632027
Short name T71
Test name
Test status
Simulation time 12277425 ps
CPU time 0.6 seconds
Started Jun 11 02:17:09 PM PDT 24
Finished Jun 11 02:17:10 PM PDT 24
Peak memory 195344 kb
Host smart-15efc2fb-7495-418e-a7b7-85b5121cb59a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559632027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.559632027
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.2003844030
Short name T242
Test name
Test status
Simulation time 839444057 ps
CPU time 38.4 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:17:50 PM PDT 24
Peak memory 216520 kb
Host smart-e55384bb-85b2-46e8-a47f-92e8fbd7ae83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2003844030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.2003844030
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1412811033
Short name T377
Test name
Test status
Simulation time 2504799074 ps
CPU time 43.32 seconds
Started Jun 11 02:17:08 PM PDT 24
Finished Jun 11 02:17:52 PM PDT 24
Peak memory 200532 kb
Host smart-f6eedf53-32fc-492a-81a0-5e43248c90af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412811033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1412811033
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.75321493
Short name T6
Test name
Test status
Simulation time 661059048 ps
CPU time 44.89 seconds
Started Jun 11 02:17:10 PM PDT 24
Finished Jun 11 02:17:56 PM PDT 24
Peak memory 259668 kb
Host smart-6a4d1edf-82c6-46f3-a4e7-5294fb93c5e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=75321493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.75321493
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2688667826
Short name T380
Test name
Test status
Simulation time 10940254109 ps
CPU time 66.15 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:18:18 PM PDT 24
Peak memory 200536 kb
Host smart-219c37ee-e0a7-4639-ae54-6fa8ebf2c072
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688667826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2688667826
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1156073756
Short name T526
Test name
Test status
Simulation time 4022283767 ps
CPU time 28.9 seconds
Started Jun 11 02:17:13 PM PDT 24
Finished Jun 11 02:17:43 PM PDT 24
Peak memory 200460 kb
Host smart-2334721d-43b4-4fdc-b73f-42c574e8a88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156073756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1156073756
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3153158878
Short name T157
Test name
Test status
Simulation time 824104870 ps
CPU time 7.15 seconds
Started Jun 11 02:17:07 PM PDT 24
Finished Jun 11 02:17:15 PM PDT 24
Peak memory 200420 kb
Host smart-094a85c8-e135-4428-8958-33867c116c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153158878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3153158878
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.1674248394
Short name T20
Test name
Test status
Simulation time 10563517762 ps
CPU time 129.19 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:19:21 PM PDT 24
Peak memory 200524 kb
Host smart-c06267f3-ad3a-44f3-be25-ce358ba468eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674248394 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.1674248394
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3087187499
Short name T294
Test name
Test status
Simulation time 362430297 ps
CPU time 1.37 seconds
Started Jun 11 02:17:09 PM PDT 24
Finished Jun 11 02:17:12 PM PDT 24
Peak memory 200420 kb
Host smart-048f4152-dd4e-4cbe-af6a-56c14e822549
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087187499 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3087187499
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.1732946320
Short name T578
Test name
Test status
Simulation time 130822452390 ps
CPU time 474.78 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:25:07 PM PDT 24
Peak memory 200492 kb
Host smart-4d821218-fc11-457f-b462-c17ce9c01be3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732946320 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.1732946320
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1068115395
Short name T264
Test name
Test status
Simulation time 318989928 ps
CPU time 9.83 seconds
Started Jun 11 02:17:13 PM PDT 24
Finished Jun 11 02:17:23 PM PDT 24
Peak memory 200344 kb
Host smart-4a704c11-66cc-4438-acd1-75e6bfd4bfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068115395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1068115395
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3271753856
Short name T394
Test name
Test status
Simulation time 31937535 ps
CPU time 0.6 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:17:12 PM PDT 24
Peak memory 196032 kb
Host smart-a74eade0-e021-4f71-ae2f-35f4bf8300bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271753856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3271753856
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3569753564
Short name T53
Test name
Test status
Simulation time 355792747 ps
CPU time 5.46 seconds
Started Jun 11 02:17:08 PM PDT 24
Finished Jun 11 02:17:14 PM PDT 24
Peak memory 200336 kb
Host smart-a3086759-08ca-4d28-a40e-e653cd5e513e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569753564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3569753564
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.2228601714
Short name T520
Test name
Test status
Simulation time 1828516728 ps
CPU time 29.86 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:17:42 PM PDT 24
Peak memory 200444 kb
Host smart-9f81dd3b-e581-4190-ae78-b6b72b648766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228601714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.2228601714
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.1232048707
Short name T169
Test name
Test status
Simulation time 3214633270 ps
CPU time 750.98 seconds
Started Jun 11 02:17:10 PM PDT 24
Finished Jun 11 02:29:42 PM PDT 24
Peak memory 739140 kb
Host smart-085a0c96-9aab-45e9-b4ce-c0f0148bb401
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232048707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.1232048707
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.4121663207
Short name T66
Test name
Test status
Simulation time 18283652108 ps
CPU time 122.43 seconds
Started Jun 11 02:17:07 PM PDT 24
Finished Jun 11 02:19:10 PM PDT 24
Peak memory 200476 kb
Host smart-4e1d47b7-5048-416e-8eb5-9608c32e9e79
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121663207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.4121663207
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.1200141475
Short name T245
Test name
Test status
Simulation time 34713608181 ps
CPU time 136.52 seconds
Started Jun 11 02:17:09 PM PDT 24
Finished Jun 11 02:19:26 PM PDT 24
Peak memory 200476 kb
Host smart-7cfd7996-d9d7-41e0-b5b5-146ed4c979cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200141475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.1200141475
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.3844010459
Short name T323
Test name
Test status
Simulation time 1215047690 ps
CPU time 5.7 seconds
Started Jun 11 02:17:13 PM PDT 24
Finished Jun 11 02:17:19 PM PDT 24
Peak memory 200384 kb
Host smart-1ae012cc-a247-4f7e-a4b9-6bcf053d24f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844010459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.3844010459
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.1067016298
Short name T62
Test name
Test status
Simulation time 19573396465 ps
CPU time 414.15 seconds
Started Jun 11 02:17:09 PM PDT 24
Finished Jun 11 02:24:04 PM PDT 24
Peak memory 467516 kb
Host smart-748cfeff-dacd-459b-a6c7-f1cc894e93c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067016298 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.1067016298
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.1807275975
Short name T442
Test name
Test status
Simulation time 166537762 ps
CPU time 1.17 seconds
Started Jun 11 02:17:10 PM PDT 24
Finished Jun 11 02:17:12 PM PDT 24
Peak memory 200204 kb
Host smart-cae72719-4fa1-45b2-b081-fc1a3299346a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807275975 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.1807275975
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.828156209
Short name T386
Test name
Test status
Simulation time 29232845972 ps
CPU time 532.64 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:26:05 PM PDT 24
Peak memory 200428 kb
Host smart-389c0c53-6a6d-43d4-b5f4-2459af732ad9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828156209 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.828156209
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.4274453482
Short name T213
Test name
Test status
Simulation time 5821387882 ps
CPU time 46.35 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:17:59 PM PDT 24
Peak memory 200424 kb
Host smart-ce9960f5-4de1-45bc-8b1d-6da86c7ce994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274453482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.4274453482
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1902363737
Short name T541
Test name
Test status
Simulation time 65174394 ps
CPU time 0.57 seconds
Started Jun 11 02:17:19 PM PDT 24
Finished Jun 11 02:17:20 PM PDT 24
Peak memory 195368 kb
Host smart-efd4982a-963a-4d16-becb-e6390fa0f091
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902363737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1902363737
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.969202781
Short name T4
Test name
Test status
Simulation time 926107669 ps
CPU time 39.98 seconds
Started Jun 11 02:17:09 PM PDT 24
Finished Jun 11 02:17:50 PM PDT 24
Peak memory 208644 kb
Host smart-ccbb7176-546e-46fe-88dd-da17eabab2b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=969202781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.969202781
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1002233892
Short name T472
Test name
Test status
Simulation time 18915369663 ps
CPU time 74.79 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:18:27 PM PDT 24
Peak memory 200488 kb
Host smart-1849170b-d8c0-4eee-8e75-3a87642372e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002233892 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1002233892
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.507832401
Short name T453
Test name
Test status
Simulation time 13432498967 ps
CPU time 815.99 seconds
Started Jun 11 02:17:13 PM PDT 24
Finished Jun 11 02:30:50 PM PDT 24
Peak memory 487556 kb
Host smart-2fb0bea7-0cf9-428f-a4ae-187c5bd28802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=507832401 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.507832401
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.1270694845
Short name T565
Test name
Test status
Simulation time 16895172912 ps
CPU time 43.87 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:17:56 PM PDT 24
Peak memory 200324 kb
Host smart-1dac3b06-8fda-4b40-9dba-7b59ac3a7f52
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270694845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.1270694845
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.4282393232
Short name T253
Test name
Test status
Simulation time 23950651646 ps
CPU time 94.94 seconds
Started Jun 11 02:17:08 PM PDT 24
Finished Jun 11 02:18:44 PM PDT 24
Peak memory 200476 kb
Host smart-e2961b99-bd91-4b63-abf9-2a6b1778daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282393232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.4282393232
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3265236098
Short name T182
Test name
Test status
Simulation time 103023396 ps
CPU time 2.56 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:17:15 PM PDT 24
Peak memory 200348 kb
Host smart-bfc17097-72ff-4f7a-9424-636ba9b94f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265236098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3265236098
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2131826219
Short name T158
Test name
Test status
Simulation time 222163579254 ps
CPU time 725.08 seconds
Started Jun 11 02:17:18 PM PDT 24
Finished Jun 11 02:29:25 PM PDT 24
Peak memory 200500 kb
Host smart-3eea54a9-99bb-4cd8-8dd1-326ee62c8c68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131826219 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2131826219
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3979164473
Short name T205
Test name
Test status
Simulation time 74818293 ps
CPU time 1.43 seconds
Started Jun 11 02:17:11 PM PDT 24
Finished Jun 11 02:17:14 PM PDT 24
Peak memory 200320 kb
Host smart-cfdc3419-83ad-4014-99ed-89a1190b9af6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979164473 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.3979164473
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.3454434009
Short name T362
Test name
Test status
Simulation time 8343319416 ps
CPU time 461.51 seconds
Started Jun 11 02:17:10 PM PDT 24
Finished Jun 11 02:24:52 PM PDT 24
Peak memory 200516 kb
Host smart-3299c2c5-c3f8-4553-8571-879ce80d72c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454434009 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.3454434009
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2489346269
Short name T89
Test name
Test status
Simulation time 337504041 ps
CPU time 15.8 seconds
Started Jun 11 02:17:12 PM PDT 24
Finished Jun 11 02:17:29 PM PDT 24
Peak memory 200632 kb
Host smart-d44b7494-c580-48df-b32b-835de815436a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489346269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2489346269
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2811647967
Short name T67
Test name
Test status
Simulation time 12932911 ps
CPU time 0.59 seconds
Started Jun 11 02:17:20 PM PDT 24
Finished Jun 11 02:17:22 PM PDT 24
Peak memory 196380 kb
Host smart-a329476a-6468-4154-b875-2e5bc93e8f43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811647967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2811647967
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.2150850123
Short name T193
Test name
Test status
Simulation time 5950889660 ps
CPU time 52.14 seconds
Started Jun 11 02:17:21 PM PDT 24
Finished Jun 11 02:18:14 PM PDT 24
Peak memory 232976 kb
Host smart-2ff0ed3c-8fcb-428c-9987-f212057682a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2150850123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.2150850123
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.999300979
Short name T477
Test name
Test status
Simulation time 1005155092 ps
CPU time 6.25 seconds
Started Jun 11 02:17:17 PM PDT 24
Finished Jun 11 02:17:24 PM PDT 24
Peak memory 200492 kb
Host smart-a2daaa0f-1d58-40a7-9395-1777d63c4b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999300979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.999300979
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2345808679
Short name T540
Test name
Test status
Simulation time 4660673214 ps
CPU time 1389.23 seconds
Started Jun 11 02:17:18 PM PDT 24
Finished Jun 11 02:40:28 PM PDT 24
Peak memory 737076 kb
Host smart-151abbd8-ae73-416e-9056-0b019c5f6ca4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345808679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2345808679
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2361743757
Short name T174
Test name
Test status
Simulation time 56372581439 ps
CPU time 122.08 seconds
Started Jun 11 02:17:22 PM PDT 24
Finished Jun 11 02:19:26 PM PDT 24
Peak memory 200484 kb
Host smart-29d6acb6-669b-4b3e-870a-a758bf27fb61
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361743757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2361743757
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.1042276428
Short name T502
Test name
Test status
Simulation time 1309005747 ps
CPU time 70.49 seconds
Started Jun 11 02:17:22 PM PDT 24
Finished Jun 11 02:18:34 PM PDT 24
Peak memory 200328 kb
Host smart-0834f1bf-fdbc-4d0d-a8a4-48c74804c01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042276428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.1042276428
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.2999698221
Short name T439
Test name
Test status
Simulation time 1012706539 ps
CPU time 5.38 seconds
Started Jun 11 02:17:20 PM PDT 24
Finished Jun 11 02:17:26 PM PDT 24
Peak memory 200416 kb
Host smart-9f47fa2c-5bb6-49cd-a45c-703496c41516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999698221 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.2999698221
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.465610873
Short name T306
Test name
Test status
Simulation time 55003746 ps
CPU time 1.08 seconds
Started Jun 11 02:17:20 PM PDT 24
Finished Jun 11 02:17:22 PM PDT 24
Peak memory 200268 kb
Host smart-c065069a-67ef-48db-ad44-fa467220fb3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465610873 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.465610873
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.1885444706
Short name T344
Test name
Test status
Simulation time 102873699494 ps
CPU time 462.65 seconds
Started Jun 11 02:17:17 PM PDT 24
Finished Jun 11 02:25:01 PM PDT 24
Peak memory 200416 kb
Host smart-af3ed84e-6abd-44dc-99d7-f1b5eedffa2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885444706 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.1885444706
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.2987613428
Short name T575
Test name
Test status
Simulation time 2507182480 ps
CPU time 44.51 seconds
Started Jun 11 02:17:19 PM PDT 24
Finished Jun 11 02:18:05 PM PDT 24
Peak memory 200528 kb
Host smart-d0e854ba-1c98-4faf-9df5-b1cae8029a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987613428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.2987613428
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.377758668
Short name T478
Test name
Test status
Simulation time 11860880 ps
CPU time 0.61 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:15:34 PM PDT 24
Peak memory 195352 kb
Host smart-2b1d2b96-66ce-4c04-8ef7-386fa7b2973f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377758668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.377758668
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.965927646
Short name T28
Test name
Test status
Simulation time 452197382 ps
CPU time 27.36 seconds
Started Jun 11 02:15:33 PM PDT 24
Finished Jun 11 02:16:03 PM PDT 24
Peak memory 233092 kb
Host smart-2c2119bb-f8d1-4339-999d-862aeacbda13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965927646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.965927646
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1151579443
Short name T468
Test name
Test status
Simulation time 172349227 ps
CPU time 3.93 seconds
Started Jun 11 02:15:29 PM PDT 24
Finished Jun 11 02:15:34 PM PDT 24
Peak memory 200184 kb
Host smart-f6f94738-1d26-4e4f-a91f-819e14dc54bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151579443 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1151579443
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2096488634
Short name T204
Test name
Test status
Simulation time 9158095130 ps
CPU time 478.84 seconds
Started Jun 11 02:15:35 PM PDT 24
Finished Jun 11 02:23:36 PM PDT 24
Peak memory 514256 kb
Host smart-f21099bf-3e0e-44e0-b22d-482f66a8d377
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2096488634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2096488634
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.4046128455
Short name T373
Test name
Test status
Simulation time 9860928046 ps
CPU time 31.56 seconds
Started Jun 11 02:15:33 PM PDT 24
Finished Jun 11 02:16:07 PM PDT 24
Peak memory 200544 kb
Host smart-567f05a0-69ad-4a86-ba34-c20adfa88f58
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046128455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.4046128455
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.4135371754
Short name T486
Test name
Test status
Simulation time 518582938 ps
CPU time 15.58 seconds
Started Jun 11 02:15:33 PM PDT 24
Finished Jun 11 02:15:51 PM PDT 24
Peak memory 200296 kb
Host smart-ec49b1c0-ccc4-4aaf-a87a-3658bd99cc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135371754 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.4135371754
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.1328248309
Short name T277
Test name
Test status
Simulation time 430007356 ps
CPU time 7.26 seconds
Started Jun 11 02:15:32 PM PDT 24
Finished Jun 11 02:15:42 PM PDT 24
Peak memory 200428 kb
Host smart-f0e28c76-1480-408e-9df5-0712230324e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328248309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.1328248309
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.2006644699
Short name T297
Test name
Test status
Simulation time 799875074 ps
CPU time 1.11 seconds
Started Jun 11 02:15:30 PM PDT 24
Finished Jun 11 02:15:33 PM PDT 24
Peak memory 200264 kb
Host smart-144a8531-acda-4ac1-b09d-7c4cd38ead02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006644699 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.2006644699
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.2972889570
Short name T592
Test name
Test status
Simulation time 31961078 ps
CPU time 1.14 seconds
Started Jun 11 02:15:36 PM PDT 24
Finished Jun 11 02:15:39 PM PDT 24
Peak memory 200444 kb
Host smart-5b427ccf-24b3-481b-a184-9499b17a6fbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972889570 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.2972889570
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.2723888566
Short name T470
Test name
Test status
Simulation time 8221028590 ps
CPU time 482.08 seconds
Started Jun 11 02:15:32 PM PDT 24
Finished Jun 11 02:23:37 PM PDT 24
Peak memory 200460 kb
Host smart-7654cbfe-0700-492f-8ba1-cc8431079eb2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723888566 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.2723888566
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.209739448
Short name T580
Test name
Test status
Simulation time 2257311130 ps
CPU time 18.24 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:15:52 PM PDT 24
Peak memory 200488 kb
Host smart-41173162-0120-4f4b-8523-f1f7a1aaf6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209739448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.209739448
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3496223699
Short name T128
Test name
Test status
Simulation time 18297343 ps
CPU time 0.59 seconds
Started Jun 11 02:15:30 PM PDT 24
Finished Jun 11 02:15:32 PM PDT 24
Peak memory 197024 kb
Host smart-dbf0c15f-c5ee-4845-b903-280e6933fce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496223699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3496223699
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.1889318753
Short name T499
Test name
Test status
Simulation time 759440815 ps
CPU time 37.1 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:16:09 PM PDT 24
Peak memory 208580 kb
Host smart-6eee4dab-cebb-46d3-9bd8-7466409e90f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1889318753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.1889318753
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.4011281455
Short name T51
Test name
Test status
Simulation time 761135195 ps
CPU time 12.12 seconds
Started Jun 11 02:15:35 PM PDT 24
Finished Jun 11 02:15:49 PM PDT 24
Peak memory 200404 kb
Host smart-6af468c3-e757-42b4-a147-77b2a0dfb2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011281455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.4011281455
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3440581625
Short name T467
Test name
Test status
Simulation time 1328790944 ps
CPU time 10.21 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:15:42 PM PDT 24
Peak memory 216844 kb
Host smart-553e6c28-9edd-4960-b5ab-7bf2030220b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3440581625 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3440581625
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.1768796629
Short name T183
Test name
Test status
Simulation time 7237161716 ps
CPU time 49.6 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:16:22 PM PDT 24
Peak memory 200424 kb
Host smart-65a4d0a2-a85f-42c9-835b-bfda6e20fec5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768796629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.1768796629
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1489386663
Short name T419
Test name
Test status
Simulation time 4039719139 ps
CPU time 78.17 seconds
Started Jun 11 02:15:34 PM PDT 24
Finished Jun 11 02:16:55 PM PDT 24
Peak memory 200504 kb
Host smart-86dffb99-a911-48a6-9a72-4c4b1436c266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489386663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1489386663
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.4070410967
Short name T10
Test name
Test status
Simulation time 136481189 ps
CPU time 4.95 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:15:38 PM PDT 24
Peak memory 200436 kb
Host smart-0ce34575-5791-41d0-8087-4bcb153b7590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070410967 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.4070410967
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.142775814
Short name T56
Test name
Test status
Simulation time 66578896164 ps
CPU time 2765.41 seconds
Started Jun 11 02:15:35 PM PDT 24
Finished Jun 11 03:01:43 PM PDT 24
Peak memory 858708 kb
Host smart-30c59186-7c8c-4b85-ba38-4cc395e0f259
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142775814 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.142775814
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.2671262012
Short name T159
Test name
Test status
Simulation time 59150832 ps
CPU time 1.16 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:15:34 PM PDT 24
Peak memory 200220 kb
Host smart-681bfe01-9000-4d2e-a077-56651684f3b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671262012 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.2671262012
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.2123796642
Short name T139
Test name
Test status
Simulation time 169566941481 ps
CPU time 488.82 seconds
Started Jun 11 02:15:29 PM PDT 24
Finished Jun 11 02:23:39 PM PDT 24
Peak memory 200332 kb
Host smart-ab696525-10ce-4839-b468-ad5f32080022
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123796642 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.2123796642
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2911460456
Short name T140
Test name
Test status
Simulation time 15321558262 ps
CPU time 16.96 seconds
Started Jun 11 02:15:34 PM PDT 24
Finished Jun 11 02:15:53 PM PDT 24
Peak memory 200508 kb
Host smart-82d7eb36-cc54-488f-9f84-b765777b6908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911460456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2911460456
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.1459629992
Short name T506
Test name
Test status
Simulation time 30030081 ps
CPU time 0.61 seconds
Started Jun 11 02:15:43 PM PDT 24
Finished Jun 11 02:15:45 PM PDT 24
Peak memory 195372 kb
Host smart-b38f2357-3223-4045-ac5c-f72672a62f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459629992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.1459629992
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.137526387
Short name T446
Test name
Test status
Simulation time 343967350 ps
CPU time 16.09 seconds
Started Jun 11 02:15:34 PM PDT 24
Finished Jun 11 02:15:52 PM PDT 24
Peak memory 200440 kb
Host smart-e51fe159-892d-41bb-a277-e5818d389cf5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137526387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.137526387
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.3153839567
Short name T494
Test name
Test status
Simulation time 2234958762 ps
CPU time 58.31 seconds
Started Jun 11 02:15:31 PM PDT 24
Finished Jun 11 02:16:31 PM PDT 24
Peak memory 200492 kb
Host smart-dec7c481-261d-44ae-962a-54736c60b3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153839567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.3153839567
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1719895164
Short name T355
Test name
Test status
Simulation time 2299148224 ps
CPU time 106.33 seconds
Started Jun 11 02:15:32 PM PDT 24
Finished Jun 11 02:17:21 PM PDT 24
Peak memory 446948 kb
Host smart-03027765-6805-429f-8e4c-7ece34c5ba01
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1719895164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1719895164
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2661643774
Short name T338
Test name
Test status
Simulation time 6865388645 ps
CPU time 87.26 seconds
Started Jun 11 02:15:34 PM PDT 24
Finished Jun 11 02:17:03 PM PDT 24
Peak memory 200476 kb
Host smart-e9d1f9f5-e5eb-4c46-a1f3-23f82bc4f732
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661643774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2661643774
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.1206998875
Short name T295
Test name
Test status
Simulation time 1822569339 ps
CPU time 33.67 seconds
Started Jun 11 02:15:30 PM PDT 24
Finished Jun 11 02:16:04 PM PDT 24
Peak memory 200268 kb
Host smart-aa033a68-7d09-41ed-8b7f-b2898305668e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206998875 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.1206998875
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.2623318803
Short name T531
Test name
Test status
Simulation time 1063495901 ps
CPU time 9.58 seconds
Started Jun 11 02:15:30 PM PDT 24
Finished Jun 11 02:15:41 PM PDT 24
Peak memory 200520 kb
Host smart-f34e771f-1267-4b26-b74e-c8775773b245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623318803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.2623318803
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.2895488580
Short name T500
Test name
Test status
Simulation time 176925757529 ps
CPU time 853.66 seconds
Started Jun 11 02:15:43 PM PDT 24
Finished Jun 11 02:29:58 PM PDT 24
Peak memory 244020 kb
Host smart-7a8d273d-61fe-4f78-85a4-9d3858c7524a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895488580 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.2895488580
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.490882602
Short name T172
Test name
Test status
Simulation time 82302788 ps
CPU time 1.47 seconds
Started Jun 11 02:15:35 PM PDT 24
Finished Jun 11 02:15:39 PM PDT 24
Peak memory 200476 kb
Host smart-be441f86-d867-43d4-bf9b-c6a85b9ed920
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490882602 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 7.hmac_test_hmac_vectors.490882602
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.4203565743
Short name T530
Test name
Test status
Simulation time 27433135116 ps
CPU time 512 seconds
Started Jun 11 02:15:33 PM PDT 24
Finished Jun 11 02:24:08 PM PDT 24
Peak memory 200348 kb
Host smart-91ce19f0-088d-4672-8c2e-ac6e6462558b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203565743 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.4203565743
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1128275269
Short name T225
Test name
Test status
Simulation time 2305959736 ps
CPU time 25.54 seconds
Started Jun 11 02:15:32 PM PDT 24
Finished Jun 11 02:16:00 PM PDT 24
Peak memory 200564 kb
Host smart-72154df2-39dc-4b0a-88de-da619cc17f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128275269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1128275269
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.116345859
Short name T490
Test name
Test status
Simulation time 13682054 ps
CPU time 0.62 seconds
Started Jun 11 02:15:50 PM PDT 24
Finished Jun 11 02:15:52 PM PDT 24
Peak memory 196580 kb
Host smart-ac6eb31f-d59e-44c7-bff0-1d6cdcf93a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116345859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.116345859
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.1863931263
Short name T347
Test name
Test status
Simulation time 1188770385 ps
CPU time 14.86 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:16:02 PM PDT 24
Peak memory 215992 kb
Host smart-2f1f4a57-5783-4884-9e26-08c5c9f35938
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863931263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.1863931263
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.3442594293
Short name T480
Test name
Test status
Simulation time 6868716319 ps
CPU time 37.81 seconds
Started Jun 11 02:15:44 PM PDT 24
Finished Jun 11 02:16:23 PM PDT 24
Peak memory 200412 kb
Host smart-9b504b6b-32e1-411f-9688-fb8ca5a967b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442594293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.3442594293
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2190545997
Short name T104
Test name
Test status
Simulation time 823379036 ps
CPU time 197.34 seconds
Started Jun 11 02:15:49 PM PDT 24
Finished Jun 11 02:19:08 PM PDT 24
Peak memory 620336 kb
Host smart-e8566ec8-4ae2-45fa-a08d-dc43dcacdecd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2190545997 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2190545997
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3158555188
Short name T142
Test name
Test status
Simulation time 7986306194 ps
CPU time 100.37 seconds
Started Jun 11 02:15:43 PM PDT 24
Finished Jun 11 02:17:25 PM PDT 24
Peak memory 200528 kb
Host smart-80d140f0-bd20-4f58-b437-e3f6f83ae1e9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158555188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3158555188
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.2025682858
Short name T489
Test name
Test status
Simulation time 6091903641 ps
CPU time 81.46 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:17:09 PM PDT 24
Peak memory 200544 kb
Host smart-4542c610-b131-4d40-a65f-a9591b74c263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025682858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.2025682858
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2512885043
Short name T190
Test name
Test status
Simulation time 21361300 ps
CPU time 0.93 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:15:47 PM PDT 24
Peak memory 200280 kb
Host smart-f0a3e1a2-7ae0-4394-be25-f08ac9109632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512885043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2512885043
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1454795132
Short name T405
Test name
Test status
Simulation time 1291897274 ps
CPU time 52.82 seconds
Started Jun 11 02:15:43 PM PDT 24
Finished Jun 11 02:16:38 PM PDT 24
Peak memory 200460 kb
Host smart-e27bf182-cf92-4c1f-9275-c6bc14158535
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454795132 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1454795132
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3583557756
Short name T508
Test name
Test status
Simulation time 51241126 ps
CPU time 1.03 seconds
Started Jun 11 02:15:43 PM PDT 24
Finished Jun 11 02:15:46 PM PDT 24
Peak memory 200204 kb
Host smart-9046e254-39db-455c-a23a-f6a07f6d6fc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583557756 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.3583557756
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.38375916
Short name T366
Test name
Test status
Simulation time 62807844341 ps
CPU time 460.05 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:23:26 PM PDT 24
Peak memory 200452 kb
Host smart-9057ad37-f580-4b2c-8585-d9925c5cfc02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38375916 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.38375916
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1475668839
Short name T249
Test name
Test status
Simulation time 4732252066 ps
CPU time 16.05 seconds
Started Jun 11 02:15:43 PM PDT 24
Finished Jun 11 02:16:01 PM PDT 24
Peak memory 200456 kb
Host smart-503f05ca-cd82-4065-8d24-17d7032a2ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475668839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1475668839
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2955361804
Short name T445
Test name
Test status
Simulation time 14951480 ps
CPU time 0.6 seconds
Started Jun 11 02:15:42 PM PDT 24
Finished Jun 11 02:15:44 PM PDT 24
Peak memory 196424 kb
Host smart-fd0ce306-d63a-4138-96ac-7d83660375b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955361804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2955361804
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.4255365355
Short name T50
Test name
Test status
Simulation time 2662531035 ps
CPU time 31.01 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:16:17 PM PDT 24
Peak memory 208644 kb
Host smart-c897925c-106b-4abe-8a6a-bfa77c12b2e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4255365355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.4255365355
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.80428601
Short name T180
Test name
Test status
Simulation time 2649134549 ps
CPU time 51.62 seconds
Started Jun 11 02:15:48 PM PDT 24
Finished Jun 11 02:16:41 PM PDT 24
Peak memory 200560 kb
Host smart-45ae9769-fa4e-4b02-a36a-1ce9b3dbe076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80428601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.80428601
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.1674981725
Short name T335
Test name
Test status
Simulation time 6778228813 ps
CPU time 717.43 seconds
Started Jun 11 02:15:49 PM PDT 24
Finished Jun 11 02:27:48 PM PDT 24
Peak memory 650828 kb
Host smart-e3424bf3-991b-4665-be2d-25cc46254c43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674981725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.1674981725
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.3988332809
Short name T573
Test name
Test status
Simulation time 34881574480 ps
CPU time 129.6 seconds
Started Jun 11 02:15:46 PM PDT 24
Finished Jun 11 02:17:58 PM PDT 24
Peak memory 200480 kb
Host smart-52c3b7ba-6d8e-4e0d-b3a7-d701daa64973
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988332809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.3988332809
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.670153793
Short name T304
Test name
Test status
Simulation time 15625735236 ps
CPU time 110.25 seconds
Started Jun 11 02:15:54 PM PDT 24
Finished Jun 11 02:17:45 PM PDT 24
Peak memory 200544 kb
Host smart-8ee90f63-31f5-4363-a61f-677e77076958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670153793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.670153793
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3261440882
Short name T189
Test name
Test status
Simulation time 1658119597 ps
CPU time 9.06 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:15:55 PM PDT 24
Peak memory 200400 kb
Host smart-0b81d5f9-552a-4272-9c25-e36ee2b2c9d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261440882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3261440882
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.1016459870
Short name T471
Test name
Test status
Simulation time 4260945405 ps
CPU time 81.26 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:17:08 PM PDT 24
Peak memory 200512 kb
Host smart-ac83d19b-f128-42de-9d57-c085daad5694
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016459870 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.1016459870
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1614237799
Short name T303
Test name
Test status
Simulation time 58905869 ps
CPU time 1.43 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:15:48 PM PDT 24
Peak memory 200492 kb
Host smart-77998190-9220-473d-822f-7af53b0bbd42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614237799 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1614237799
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.529619108
Short name T416
Test name
Test status
Simulation time 33013959741 ps
CPU time 479.69 seconds
Started Jun 11 02:15:45 PM PDT 24
Finished Jun 11 02:23:46 PM PDT 24
Peak memory 200432 kb
Host smart-43b20910-1cfa-4b8b-aae2-ee2bb16a4126
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529619108 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.529619108
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.3258464955
Short name T148
Test name
Test status
Simulation time 5270658142 ps
CPU time 73 seconds
Started Jun 11 02:15:43 PM PDT 24
Finished Jun 11 02:16:57 PM PDT 24
Peak memory 200556 kb
Host smart-9cd329c5-bd22-48ec-b643-963a912a4d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258464955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.3258464955
Directory /workspace/9.hmac_wipe_secret/latest
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