Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	13174736	1			T1	9225		T2	13610		T3	14889
all_values[1]	13174736	1			T1	9225		T2	13610		T3	14889
all_values[2]	13174736	1			T1	9225		T2	13610		T3	14889

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

144287

1

T1

3

T3

326

T4

395

auto[1]

39379921

1

T1

27672

T2

40830

T3

44341

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32968837

1

T1

25530

T2

32945

T3

40260

auto[1]

6555371

1

T1

2145

T2

7885

T3

4407

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	54914	1			T6	131		T14	212		T42	3454
all_values[0]	auto[0]	auto[1]	346	1			T6	2		T42	2		T27	6
all_values[0]	auto[1]	auto[0]	13084803	1			T1	9211		T2	13600		T3	14806
all_values[0]	auto[1]	auto[1]	34673	1			T1	14		T2	10		T3	83
all_values[1]	auto[0]	auto[0]	48705	1			T3	326		T4	395		T21	61
all_values[1]	auto[0]	auto[1]	215	1			T21	1		T26	1		T27	4
all_values[1]	auto[1]	auto[0]	13125495	1			T1	9225		T2	13610		T3	14562
all_values[1]	auto[1]	auto[1]	321	1			T3	1		T26	1		T27	3
all_values[2]	auto[0]	auto[0]	19775	1			T1	1		T21	62		T42	106
all_values[2]	auto[0]	auto[1]	20332	1			T1	2		T26	2		T27	2
all_values[2]	auto[1]	auto[0]	6635145	1			T1	7093		T2	5735		T3	10566
all_values[2]	auto[1]	auto[1]	6499484	1			T1	2129		T2	7875		T3	4323