Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
18.62	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	51	13	20.31
Crosses	124	102	22	17.74

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	61	50	11	18.03	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	122	100	22	18.03	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

146755

1

T2

32

T3

1408

T4

20

auto[1]

121818

1

T1

28

T2

12

T3

1782

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	61	50	11	18.03

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto_lens[1]	0	1	1
auto_lens[2]	0	1	1
auto_lens[3]	0	1	1
auto_lens[4]	0	1	1
auto_lens[5]	0	1	1
auto_lens[6]	0	1	1
auto_lens[7]	0	1	1
auto_lens[8]	0	1	1
auto_lens[9]	0	1	1
auto_lens[10]	0	1	1
auto_lens[11]	0	1	1
auto_lens[12]	0	1	1
auto_lens[13]	0	1	1
auto_lens[14]	0	1	1
auto_lens[15]	0	1	1
auto_lens[16]	0	1	1
auto_lens[17]	0	1	1
auto_lens[18]	0	1	1
auto_lens[19]	0	1	1
auto_lens[20]	0	1	1
auto_lens[21]	0	1	1
auto_lens[22]	0	1	1
auto_lens[23]	0	1	1
auto_lens[24]	0	1	1
auto_lens[25]	0	1	1
auto_lens[26]	0	1	1
auto_lens[27]	0	1	1
auto_lens[28]	0	1	1
auto_lens[29]	0	1	1
auto_lens[30]	0	1	1
auto_lens[31]	0	1	1
auto_lens[32]	0	1	1
auto_lens[33]	0	1	1
auto_lens[34]	0	1	1
auto_lens[35]	0	1	1
auto_lens[36]	0	1	1
auto_lens[37]	0	1	1
auto_lens[38]	0	1	1
auto_lens[39]	0	1	1
auto_lens[40]	0	1	1
auto_lens[41]	0	1	1
auto_lens[42]	0	1	1
auto_lens[43]	0	1	1
auto_lens[44]	0	1	1
auto_lens[45]	0	1	1
auto_lens[46]	0	1	1
auto_lens[47]	0	1	1
auto_lens[48]	0	1	1
auto_lens[49]	0	1	1
len_2047	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto_lens[0]	125483	1			T1	6		T2	19		T3	1411
len_2049	2	1			T86	1		T87	1		-	-
len_2048	103	1			T3	2		T88	1		T27	1
len_1025	14	1			T89	3		T60	1		T65	2
len_1024	168	1			T3	5		T21	2		T88	3
len_1023	2	1			T90	1		T91	1		-	-
len_513	41	1			T92	35		T66	6		-	-
len_512	178	1			T3	3		T21	2		T88	2
len_511	351	1			T93	349		T94	1		T95	1
len_1	1294	1			T1	8		T5	2		T42	11
len_0	6649	1			T2	3		T3	174		T4	2

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	122	100	22	18.03	100

Automatically Generated Cross Bins for msg_len_lower_cross

Element holes

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto_lens[1] , auto_lens[2] , auto_lens[3] , auto_lens[4] , auto_lens[5] , auto_lens[6] , auto_lens[7] , auto_lens[8] , auto_lens[9] , auto_lens[10] , auto_lens[11] , auto_lens[12] , auto_lens[13] , auto_lens[14] , auto_lens[15] , auto_lens[16] , auto_lens[17] , auto_lens[18] , auto_lens[19] , auto_lens[20] , auto_lens[21] , auto_lens[22] , auto_lens[23] , auto_lens[24] , auto_lens[25] , auto_lens[26] , auto_lens[27] , auto_lens[28] , auto_lens[29] , auto_lens[30] , auto_lens[31] , auto_lens[32] , auto_lens[33] , auto_lens[34] , auto_lens[35] , auto_lens[36] , auto_lens[37] , auto_lens[38] , auto_lens[39] , auto_lens[40] , auto_lens[41] , auto_lens[42] , auto_lens[43] , auto_lens[44] , auto_lens[45] , auto_lens[46] , auto_lens[47] , auto_lens[48] , auto_lens[49]]	--	--	98
*	[len_2047]	--	--	2

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto_lens[0]	69915	1			T2	13		T3	692		T4	8
auto[0]	len_2049	1	1			T87	1		-	-		-	-
auto[0]	len_2048	63	1			T3	1		T88	1		T27	1
auto[0]	len_1025	1	1			T96	1		-	-		-	-
auto[0]	len_1024	95	1			T3	2		T21	2		T88	2
auto[0]	len_1023	1	1			T90	1		-	-		-	-
auto[0]	len_513	23	1			T92	23		-	-		-	-
auto[0]	len_512	102	1			T3	2		T21	2		T88	2
auto[0]	len_511	1	1			T94	1		-	-		-	-
auto[0]	len_1	142	1			T5	2		T44	1		T46	1
auto[0]	len_0	3032	1			T2	3		T3	7		T4	2
auto[1]	auto_lens[0]	55568	1			T1	6		T2	6		T3	719
auto[1]	len_2049	1	1			T86	1		-	-		-	-
auto[1]	len_2048	40	1			T3	1		T97	2		T34	1
auto[1]	len_1025	13	1			T89	3		T60	1		T65	2
auto[1]	len_1024	73	1			T3	3		T88	1		T97	1
auto[1]	len_1023	1	1			T91	1		-	-		-	-
auto[1]	len_513	18	1			T92	12		T66	6		-	-
auto[1]	len_512	76	1			T3	1		T97	1		T34	2
auto[1]	len_511	350	1			T93	349		T95	1		-	-
auto[1]	len_1	1152	1			T1	8		T42	11		T72	10
auto[1]	len_0	3617	1			T3	167		T21	12		T13	1

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2