Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6283431

1

T1

5993

T2

3710

T3

15811

auto[1]

2418598

1

T1

2930

T2

2483

T3

14525

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2472283

1

T1

4832

T2

2102

T3

14969

auto[1]

6229746

1

T1

4091

T2

4091

T3

15367

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5174579

1

T2

5239

T3

16751

T4

2979

auto[1]

3527450

1

T1

8923

T2

954

T3

13585

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	6970999	1			T1	5896		T2	5972		T3	10414
fifo_depth[1]	275512	1			T1	250		T2	107		T3	445
fifo_depth[2]	215932	1			T1	270		T2	53		T3	520
fifo_depth[3]	167614	1			T1	297		T2	35		T3	492
fifo_depth[4]	140890	1			T1	304		T2	17		T3	631
fifo_depth[5]	120016	1			T1	288		T2	7		T3	506
fifo_depth[6]	112978	1			T1	260		T2	2		T3	629
fifo_depth[7]	99463	1			T1	273		T3	501		T4	185

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1731030

1

T1

3027

T2

221

T3

19922

auto[1]

6970999

1

T1

5896

T2

5972

T3

10414

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8684214

1

T1

8923

T2

6193

T3

28067

auto[1]

17815

1

T3

2269

T6

3

T21

339

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

108726

1

T2

35

T3

1334

T4

377

auto[0]

auto[0]

auto[0]

auto[1]

83033

1

T3

4669

T4

304

T6

1

auto[0]

auto[0]

auto[1]

auto[0]

723570

1

T2

119

T3

3135

T4

71

auto[0]

auto[0]

auto[1]

auto[1]

105473

1

T2

18

T3

2742

T4

205

auto[0]

auto[1]

auto[0]

auto[0]

172677

1

T1

1122

T2

43

T3

1144

auto[0]

auto[1]

auto[0]

auto[1]

177935

1

T3

1962

T4

319

T17

2

auto[0]

auto[1]

auto[1]

auto[0]

185364

1

T1

1363

T2

6

T3

4035

auto[0]

auto[1]

auto[1]

auto[1]

174252

1

T1

542

T3

901

T4

125

auto[1]

auto[0]

auto[0]

auto[0]

263451

1

T2

940

T3

1621

T4

591

auto[1]

auto[0]

auto[0]

auto[1]

259080

1

T2

463

T3

1518

T4

1006

auto[1]

auto[0]

auto[1]

auto[0]

3357127

1

T2

1682

T3

421

T4

131

auto[1]

auto[0]

auto[1]

auto[1]

274119

1

T2

1982

T3

1311

T4

294

auto[1]

auto[1]

auto[0]

auto[0]

761141

1

T1

1586

T2

604

T3

2020

auto[1]

auto[1]

auto[0]

auto[1]

646240

1

T1

2124

T2

17

T3

701

auto[1]

auto[1]

auto[1]

auto[0]

711375

1

T1

1922

T2

281

T3

2101

auto[1]

auto[1]

auto[1]

auto[1]

698466

1

T1

264

T2

3

T3

721

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

368565

1

T2

975

T3

2904

T4

968

auto[0]

auto[0]

auto[0]

auto[1]

341124

1

T2

463

T3

6153

T4

1310

auto[0]

auto[0]

auto[1]

auto[0]

4075862

1

T2

1801

T3

2324

T4

202

auto[0]

auto[0]

auto[1]

auto[1]

377573

1

T2

2000

T3

3700

T4

499

auto[0]

auto[1]

auto[0]

auto[0]

931878

1

T1

2708

T2

647

T3

3164

auto[0]

auto[1]

auto[0]

auto[1]

822869

1

T1

2124

T2

17

T3

2270

auto[0]

auto[1]

auto[1]

auto[0]

894876

1

T1

3285

T2

287

T3

5937

auto[0]

auto[1]

auto[1]

auto[1]

871467

1

T1

806

T2

3

T3

1615

auto[1]

auto[0]

auto[0]

auto[0]

3612

1

T3

51

T6

1

T21

221

auto[1]

auto[0]

auto[0]

auto[1]

989

1

T3

34

T21

3

T31

1

auto[1]

auto[0]

auto[1]

auto[0]

4835

1

T3

1232

T21

10

T111

1

auto[1]

auto[0]

auto[1]

auto[1]

2019

1

T3

353

T6

1

T46

29

auto[1]

auto[1]

auto[0]

auto[0]

1940

1

T46

8

T112

159

T34

108

auto[1]

auto[1]

auto[0]

auto[1]

1306

1

T3

393

T31

1

T112

1

auto[1]

auto[1]

auto[1]

auto[0]

1863

1

T3

199

T6

1

T112

1

auto[1]

auto[1]

auto[1]

auto[1]

1251

1

T3

7

T21

105

T46

4

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	263451	1			T2	940		T3	1621		T4	591
fifo_depth[0]	auto[0]	auto[0]	auto[1]	259080	1			T2	463		T3	1518		T4	1006
fifo_depth[0]	auto[0]	auto[1]	auto[0]	3357127	1			T2	1682		T3	421		T4	131
fifo_depth[0]	auto[0]	auto[1]	auto[1]	274119	1			T2	1982		T3	1311		T4	294
fifo_depth[0]	auto[1]	auto[0]	auto[0]	761141	1			T1	1586		T2	604		T3	2020
fifo_depth[0]	auto[1]	auto[0]	auto[1]	646240	1			T1	2124		T2	17		T3	701
fifo_depth[0]	auto[1]	auto[1]	auto[0]	711375	1			T1	1922		T2	281		T3	2101
fifo_depth[0]	auto[1]	auto[1]	auto[1]	698466	1			T1	264		T2	3		T3	721
fifo_depth[1]	auto[0]	auto[0]	auto[0]	8436	1			T2	22		T3	68		T4	41
fifo_depth[1]	auto[0]	auto[0]	auto[1]	8563	1			T3	80		T4	39		T21	3
fifo_depth[1]	auto[0]	auto[1]	auto[0]	174563	1			T2	51		T3	43		T4	10
fifo_depth[1]	auto[0]	auto[1]	auto[1]	9042	1			T2	13		T3	56		T4	14
fifo_depth[1]	auto[1]	auto[0]	auto[0]	18919	1			T1	83		T2	15		T3	127
fifo_depth[1]	auto[1]	auto[0]	auto[1]	17523	1			T3	4		T4	27		T41	2
fifo_depth[1]	auto[1]	auto[1]	auto[0]	18819	1			T1	109		T2	6		T3	62
fifo_depth[1]	auto[1]	auto[1]	auto[1]	19647	1			T1	58		T3	5		T4	17
fifo_depth[2]	auto[0]	auto[0]	auto[0]	7347	1			T2	6		T3	79		T4	41
fifo_depth[2]	auto[0]	auto[0]	auto[1]	7610	1			T3	111		T4	25		T21	1
fifo_depth[2]	auto[0]	auto[1]	auto[0]	125571	1			T2	33		T3	37		T4	8
fifo_depth[2]	auto[0]	auto[1]	auto[1]	7961	1			T2	4		T3	53		T4	16
fifo_depth[2]	auto[1]	auto[0]	auto[0]	17176	1			T1	107		T2	10		T3	119
fifo_depth[2]	auto[1]	auto[0]	auto[1]	15957	1			T3	48		T4	37		T13	2
fifo_depth[2]	auto[1]	auto[1]	auto[0]	17152	1			T1	106		T3	59		T4	12
fifo_depth[2]	auto[1]	auto[1]	auto[1]	17158	1			T1	57		T3	14		T4	19
fifo_depth[3]	auto[0]	auto[0]	auto[0]	5720	1			T2	7		T3	73		T4	47
fifo_depth[3]	auto[0]	auto[0]	auto[1]	6144	1			T3	125		T4	29		T21	1
fifo_depth[3]	auto[0]	auto[1]	auto[0]	91752	1			T2	19		T3	49		T4	7
fifo_depth[3]	auto[0]	auto[1]	auto[1]	6458	1			T2	1		T3	54		T4	24
fifo_depth[3]	auto[1]	auto[0]	auto[0]	14316	1			T1	99		T2	8		T3	112
fifo_depth[3]	auto[1]	auto[0]	auto[1]	13988	1			T3	9		T4	26		T13	1
fifo_depth[3]	auto[1]	auto[1]	auto[0]	14852	1			T1	133		T3	48		T4	10
fifo_depth[3]	auto[1]	auto[1]	auto[1]	14384	1			T1	65		T3	22		T4	9
fifo_depth[4]	auto[0]	auto[0]	auto[0]	6060	1			T3	69		T4	34		T21	10
fifo_depth[4]	auto[0]	auto[0]	auto[1]	5977	1			T3	150		T4	46		T21	1
fifo_depth[4]	auto[0]	auto[1]	auto[0]	66601	1			T2	11		T3	29		T4	8
fifo_depth[4]	auto[0]	auto[1]	auto[1]	6310	1			T3	59		T4	16		T21	2
fifo_depth[4]	auto[1]	auto[0]	auto[0]	14082	1			T1	103		T2	6		T3	99
fifo_depth[4]	auto[1]	auto[0]	auto[1]	13811	1			T3	49		T4	26		T72	70
fifo_depth[4]	auto[1]	auto[1]	auto[0]	14229	1			T1	135		T3	158		T4	18
fifo_depth[4]	auto[1]	auto[1]	auto[1]	13820	1			T1	66		T3	18		T4	12
fifo_depth[5]	auto[0]	auto[0]	auto[0]	4806	1			T3	72		T4	36		T21	9
fifo_depth[5]	auto[0]	auto[0]	auto[1]	4991	1			T3	144		T4	29		T88	6
fifo_depth[5]	auto[0]	auto[1]	auto[0]	53976	1			T2	5		T3	36		T4	6
fifo_depth[5]	auto[0]	auto[1]	auto[1]	5219	1			T3	54		T4	23		T88	2
fifo_depth[5]	auto[1]	auto[0]	auto[0]	12592	1			T1	115		T2	2		T3	101
fifo_depth[5]	auto[1]	auto[0]	auto[1]	12907	1			T3	11		T4	25		T72	59
fifo_depth[5]	auto[1]	auto[1]	auto[0]	12945	1			T1	119		T3	60		T4	14
fifo_depth[5]	auto[1]	auto[1]	auto[1]	12580	1			T1	54		T3	28		T4	17
fifo_depth[6]	auto[0]	auto[0]	auto[0]	5305	1			T3	79		T4	37		T21	8
fifo_depth[6]	auto[0]	auto[0]	auto[1]	4660	1			T3	146		T4	29		T21	1
fifo_depth[6]	auto[0]	auto[1]	auto[0]	46561	1			T3	30		T4	9		T21	7
fifo_depth[6]	auto[0]	auto[1]	auto[1]	5408	1			T3	60		T4	13		T88	1
fifo_depth[6]	auto[1]	auto[0]	auto[0]	12842	1			T1	96		T2	2		T3	99
fifo_depth[6]	auto[1]	auto[0]	auto[1]	12831	1			T3	52		T4	24		T72	71
fifo_depth[6]	auto[1]	auto[1]	auto[0]	12752	1			T1	112		T3	150		T4	15
fifo_depth[6]	auto[1]	auto[1]	auto[1]	12619	1			T1	52		T3	13		T4	14
fifo_depth[7]	auto[0]	auto[0]	auto[0]	4682	1			T3	53		T4	38		T21	17
fifo_depth[7]	auto[0]	auto[0]	auto[1]	4014	1			T3	154		T4	29		T88	5
fifo_depth[7]	auto[0]	auto[1]	auto[0]	37784	1			T3	37		T4	8		T21	7
fifo_depth[7]	auto[0]	auto[1]	auto[1]	4801	1			T3	69		T4	14		T88	1
fifo_depth[7]	auto[1]	auto[0]	auto[0]	11836	1			T1	96		T3	90		T4	50
fifo_depth[7]	auto[1]	auto[0]	auto[1]	12236	1			T3	10		T4	23		T13	2
fifo_depth[7]	auto[1]	auto[1]	auto[0]	12380	1			T1	122		T3	59		T4	14
fifo_depth[7]	auto[1]	auto[1]	auto[1]	11730	1			T1	55		T3	29		T4	9