Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	13174736	1			T1	9225		T2	13610		T3	14889
all_pins[1]	13174736	1			T1	9225		T2	13610		T3	14889
all_pins[2]	13174736	1			T1	9225		T2	13610		T3	14889

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	32989071	1			T1	25531		T2	32945		T3	40252
values[0x1]	6535137	1			T1	2144		T2	7885		T3	4415
transitions[0x0=>0x1]	6534975	1			T1	2144		T2	7885		T3	4415
transitions[0x1=>0x0]	6534992	1			T1	2144		T2	7885		T3	4415

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	13139414	1			T1	9210		T2	13600		T3	14798
all_pins[0]	values[0x1]	35322	1			T1	15		T2	10		T3	91
all_pins[0]	transitions[0x0=>0x1]	35231	1			T1	15		T2	10		T3	91
all_pins[0]	transitions[0x1=>0x0]	6499410	1			T1	2129		T2	7875		T3	4323
all_pins[1]	values[0x0]	13174405	1			T1	9225		T2	13610		T3	14888
all_pins[1]	values[0x1]	331	1			T3	1		T26	1		T27	3
all_pins[1]	transitions[0x0=>0x1]	298	1			T3	1		T26	1		T27	2
all_pins[1]	transitions[0x1=>0x0]	35289	1			T1	15		T2	10		T3	91
all_pins[2]	values[0x0]	6675252	1			T1	7096		T2	5735		T3	10566
all_pins[2]	values[0x1]	6499484	1			T1	2129		T2	7875		T3	4323
all_pins[2]	transitions[0x0=>0x1]	6499446	1			T1	2129		T2	7875		T3	4323
all_pins[2]	transitions[0x1=>0x0]	293	1			T3	1		T27	2		T46	5