Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 807 1 T26 7 T27 15 T46 17
all_values[1] 807 1 T26 7 T27 15 T46 17
all_values[2] 807 1 T26 7 T27 15 T46 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1259 1 T26 12 T27 21 T46 22
auto[1] 1162 1 T26 9 T27 24 T46 29


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 829 1 T26 11 T27 13 T46 11
auto[1] 1592 1 T26 10 T27 32 T46 40


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1362 1 T26 16 T27 26 T46 24
auto[1] 1059 1 T26 5 T27 19 T46 27


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 144 1 T26 3 T27 1 T46 1
all_values[0] auto[0] auto[0] auto[1] 99 1 T27 4 T46 2 T98 2
all_values[0] auto[0] auto[1] auto[0] 147 1 T26 3 T27 5 T46 1
all_values[0] auto[0] auto[1] auto[1] 86 1 T27 2 T46 2 T34 2
all_values[0] auto[1] auto[0] auto[1] 164 1 T27 2 T46 4 T99 2
all_values[0] auto[1] auto[1] auto[1] 167 1 T26 1 T27 1 T46 7
all_values[1] auto[0] auto[0] auto[0] 117 1 T26 3 T27 2 T34 3
all_values[1] auto[0] auto[0] auto[1] 118 1 T27 3 T46 3 T34 2
all_values[1] auto[0] auto[1] auto[0] 109 1 T27 1 T46 1 T98 1
all_values[1] auto[0] auto[1] auto[1] 91 1 T26 2 T27 2 T46 1
all_values[1] auto[1] auto[0] auto[1] 216 1 T26 1 T27 5 T46 5
all_values[1] auto[1] auto[1] auto[1] 156 1 T26 1 T27 2 T46 7
all_values[2] auto[0] auto[0] auto[0] 161 1 T26 2 T27 2 T46 3
all_values[2] auto[0] auto[0] auto[1] 70 1 T26 1 T46 3 T34 2
all_values[2] auto[0] auto[1] auto[0] 151 1 T27 2 T46 5 T34 1
all_values[2] auto[0] auto[1] auto[1] 69 1 T26 2 T27 2 T46 2
all_values[2] auto[1] auto[0] auto[1] 170 1 T26 2 T27 2 T46 1
all_values[2] auto[1] auto[1] auto[1] 186 1 T27 7 T46 3 T34 5


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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