Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
89.26 94.84 92.14 100.00 76.92 89.38 99.49 72.04


Total test records in report: 728
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T531 /workspace/coverage/default/42.hmac_back_pressure.1272216851 Jun 13 01:11:00 PM PDT 24 Jun 13 01:11:06 PM PDT 24 32264189 ps
T532 /workspace/coverage/default/8.hmac_error.3768504321 Jun 13 01:09:40 PM PDT 24 Jun 13 01:11:01 PM PDT 24 26335367070 ps
T533 /workspace/coverage/default/18.hmac_smoke.501803332 Jun 13 01:10:10 PM PDT 24 Jun 13 01:10:12 PM PDT 24 55256617 ps
T534 /workspace/coverage/default/20.hmac_alert_test.2890630305 Jun 13 01:09:53 PM PDT 24 Jun 13 01:09:56 PM PDT 24 19163390 ps
T535 /workspace/coverage/default/32.hmac_stress_all.11019786 Jun 13 01:11:06 PM PDT 24 Jun 13 01:37:41 PM PDT 24 260063252670 ps
T536 /workspace/coverage/default/18.hmac_burst_wr.3972942251 Jun 13 01:09:52 PM PDT 24 Jun 13 01:10:07 PM PDT 24 246922972 ps
T537 /workspace/coverage/default/35.hmac_datapath_stress.1656763324 Jun 13 01:10:54 PM PDT 24 Jun 13 01:17:25 PM PDT 24 1461005045 ps
T538 /workspace/coverage/default/34.hmac_burst_wr.199320046 Jun 13 01:10:49 PM PDT 24 Jun 13 01:11:01 PM PDT 24 1986199586 ps
T539 /workspace/coverage/default/24.hmac_wipe_secret.2906027933 Jun 13 01:10:18 PM PDT 24 Jun 13 01:11:31 PM PDT 24 14383730747 ps
T540 /workspace/coverage/default/7.hmac_test_sha_vectors.155707842 Jun 13 01:09:39 PM PDT 24 Jun 13 01:16:51 PM PDT 24 41340881838 ps
T30 /workspace/coverage/default/2.hmac_sec_cm.1578113646 Jun 13 01:09:52 PM PDT 24 Jun 13 01:09:55 PM PDT 24 758730411 ps
T541 /workspace/coverage/default/41.hmac_smoke.2943496303 Jun 13 01:10:58 PM PDT 24 Jun 13 01:11:06 PM PDT 24 106950747 ps
T542 /workspace/coverage/default/23.hmac_back_pressure.38598961 Jun 13 01:10:16 PM PDT 24 Jun 13 01:10:27 PM PDT 24 381904739 ps
T543 /workspace/coverage/default/11.hmac_test_hmac_vectors.3186799561 Jun 13 01:09:57 PM PDT 24 Jun 13 01:10:00 PM PDT 24 76113542 ps
T87 /workspace/coverage/default/33.hmac_long_msg.1783560742 Jun 13 01:11:03 PM PDT 24 Jun 13 01:13:13 PM PDT 24 2040153860 ps
T544 /workspace/coverage/default/4.hmac_test_hmac_vectors.3984317612 Jun 13 01:09:31 PM PDT 24 Jun 13 01:09:33 PM PDT 24 167979732 ps
T545 /workspace/coverage/default/42.hmac_smoke.3110851555 Jun 13 01:10:59 PM PDT 24 Jun 13 01:11:05 PM PDT 24 117071401 ps
T546 /workspace/coverage/default/32.hmac_error.3412699631 Jun 13 01:11:06 PM PDT 24 Jun 13 01:12:27 PM PDT 24 16953380920 ps
T547 /workspace/coverage/default/7.hmac_smoke.766955335 Jun 13 01:09:50 PM PDT 24 Jun 13 01:09:58 PM PDT 24 360596190 ps
T548 /workspace/coverage/default/26.hmac_burst_wr.891858756 Jun 13 01:10:53 PM PDT 24 Jun 13 01:11:48 PM PDT 24 48529387514 ps
T549 /workspace/coverage/default/0.hmac_test_sha_vectors.3813650321 Jun 13 01:09:24 PM PDT 24 Jun 13 01:16:46 PM PDT 24 7842288098 ps
T550 /workspace/coverage/default/47.hmac_burst_wr.782427093 Jun 13 01:44:02 PM PDT 24 Jun 13 01:44:48 PM PDT 24 8336410544 ps
T551 /workspace/coverage/default/4.hmac_wipe_secret.1726084470 Jun 13 01:09:46 PM PDT 24 Jun 13 01:10:53 PM PDT 24 3607155017 ps
T552 /workspace/coverage/default/32.hmac_test_sha_vectors.1943948863 Jun 13 01:10:59 PM PDT 24 Jun 13 01:19:13 PM PDT 24 155684843781 ps
T553 /workspace/coverage/default/17.hmac_wipe_secret.2521431762 Jun 13 01:09:55 PM PDT 24 Jun 13 01:10:34 PM PDT 24 2036923225 ps
T554 /workspace/coverage/default/31.hmac_smoke.4272693705 Jun 13 01:10:57 PM PDT 24 Jun 13 01:11:06 PM PDT 24 510311933 ps
T555 /workspace/coverage/default/44.hmac_long_msg.154077394 Jun 13 01:11:01 PM PDT 24 Jun 13 01:12:01 PM PDT 24 965467805 ps
T556 /workspace/coverage/default/35.hmac_stress_all.889247719 Jun 13 01:10:56 PM PDT 24 Jun 13 01:16:10 PM PDT 24 22453940978 ps
T557 /workspace/coverage/default/4.hmac_long_msg.1469965920 Jun 13 01:09:37 PM PDT 24 Jun 13 01:10:35 PM PDT 24 928280162 ps
T558 /workspace/coverage/default/21.hmac_test_hmac_vectors.1134569415 Jun 13 01:10:02 PM PDT 24 Jun 13 01:10:04 PM PDT 24 530144760 ps
T559 /workspace/coverage/default/22.hmac_test_hmac_vectors.3253983641 Jun 13 01:10:16 PM PDT 24 Jun 13 01:10:18 PM PDT 24 41514556 ps
T560 /workspace/coverage/default/28.hmac_smoke.3444063238 Jun 13 01:10:50 PM PDT 24 Jun 13 01:11:00 PM PDT 24 1254026723 ps
T561 /workspace/coverage/default/8.hmac_stress_all.2668214667 Jun 13 01:09:40 PM PDT 24 Jun 13 01:21:42 PM PDT 24 51273655354 ps
T562 /workspace/coverage/default/46.hmac_back_pressure.1216334405 Jun 13 02:30:04 PM PDT 24 Jun 13 02:30:48 PM PDT 24 4212052779 ps
T563 /workspace/coverage/default/32.hmac_test_hmac_vectors.297305074 Jun 13 01:11:00 PM PDT 24 Jun 13 01:11:07 PM PDT 24 56778785 ps
T564 /workspace/coverage/default/32.hmac_alert_test.3258935846 Jun 13 01:11:03 PM PDT 24 Jun 13 01:11:08 PM PDT 24 36483719 ps
T565 /workspace/coverage/default/34.hmac_wipe_secret.3696025653 Jun 13 01:10:55 PM PDT 24 Jun 13 01:12:32 PM PDT 24 11304866243 ps
T566 /workspace/coverage/default/33.hmac_burst_wr.1587559620 Jun 13 01:11:03 PM PDT 24 Jun 13 01:11:55 PM PDT 24 4151546088 ps
T567 /workspace/coverage/default/35.hmac_back_pressure.2533421652 Jun 13 01:10:57 PM PDT 24 Jun 13 01:11:17 PM PDT 24 1731094231 ps
T568 /workspace/coverage/default/41.hmac_test_sha_vectors.526267100 Jun 13 01:10:58 PM PDT 24 Jun 13 01:18:13 PM PDT 24 15733388356 ps
T569 /workspace/coverage/default/1.hmac_back_pressure.807961515 Jun 13 01:09:27 PM PDT 24 Jun 13 01:10:16 PM PDT 24 6699974333 ps
T570 /workspace/coverage/default/38.hmac_test_sha_vectors.2926657473 Jun 13 01:10:47 PM PDT 24 Jun 13 01:17:37 PM PDT 24 7157640812 ps
T571 /workspace/coverage/default/21.hmac_alert_test.4157493674 Jun 13 01:10:03 PM PDT 24 Jun 13 01:10:04 PM PDT 24 12291176 ps
T572 /workspace/coverage/default/22.hmac_smoke.89894537 Jun 13 01:09:53 PM PDT 24 Jun 13 01:09:57 PM PDT 24 137645457 ps
T573 /workspace/coverage/default/41.hmac_error.2315690324 Jun 13 01:11:01 PM PDT 24 Jun 13 01:11:51 PM PDT 24 1583868237 ps
T574 /workspace/coverage/default/0.hmac_alert_test.2435294415 Jun 13 01:09:27 PM PDT 24 Jun 13 01:09:28 PM PDT 24 13903778 ps
T575 /workspace/coverage/default/17.hmac_back_pressure.3015612474 Jun 13 01:09:54 PM PDT 24 Jun 13 01:10:43 PM PDT 24 1063043246 ps
T576 /workspace/coverage/default/18.hmac_error.4086791987 Jun 13 01:10:05 PM PDT 24 Jun 13 01:11:30 PM PDT 24 26636027218 ps
T577 /workspace/coverage/default/13.hmac_test_sha_vectors.3311042056 Jun 13 01:09:54 PM PDT 24 Jun 13 01:18:19 PM PDT 24 35821658201 ps
T578 /workspace/coverage/default/15.hmac_stress_all.1429563876 Jun 13 01:09:46 PM PDT 24 Jun 13 01:24:19 PM PDT 24 30563126155 ps
T579 /workspace/coverage/default/10.hmac_stress_all.1369971600 Jun 13 01:09:40 PM PDT 24 Jun 13 01:44:27 PM PDT 24 75229194292 ps
T580 /workspace/coverage/default/42.hmac_long_msg.2562629480 Jun 13 01:11:00 PM PDT 24 Jun 13 01:11:54 PM PDT 24 1559435540 ps
T581 /workspace/coverage/default/11.hmac_smoke.2267431061 Jun 13 01:09:44 PM PDT 24 Jun 13 01:09:57 PM PDT 24 2680470588 ps
T582 /workspace/coverage/default/39.hmac_burst_wr.2414360848 Jun 13 01:10:52 PM PDT 24 Jun 13 01:12:46 PM PDT 24 112726669032 ps
T583 /workspace/coverage/default/28.hmac_long_msg.351322441 Jun 13 01:10:50 PM PDT 24 Jun 13 01:12:32 PM PDT 24 1693108995 ps
T584 /workspace/coverage/default/28.hmac_test_hmac_vectors.3936355389 Jun 13 01:10:49 PM PDT 24 Jun 13 01:10:53 PM PDT 24 270464264 ps
T585 /workspace/coverage/default/27.hmac_burst_wr.344068893 Jun 13 01:10:50 PM PDT 24 Jun 13 01:10:56 PM PDT 24 160304758 ps
T586 /workspace/coverage/default/9.hmac_datapath_stress.510253604 Jun 13 01:09:40 PM PDT 24 Jun 13 01:09:50 PM PDT 24 486364607 ps
T587 /workspace/coverage/default/42.hmac_alert_test.2681126432 Jun 13 01:11:01 PM PDT 24 Jun 13 01:11:07 PM PDT 24 17910609 ps
T588 /workspace/coverage/default/10.hmac_test_hmac_vectors.3417589715 Jun 13 01:09:38 PM PDT 24 Jun 13 01:09:41 PM PDT 24 133705147 ps
T589 /workspace/coverage/default/29.hmac_burst_wr.531024147 Jun 13 01:10:53 PM PDT 24 Jun 13 01:11:15 PM PDT 24 1400543299 ps
T590 /workspace/coverage/default/24.hmac_burst_wr.4020159327 Jun 13 01:10:17 PM PDT 24 Jun 13 01:10:49 PM PDT 24 9296213428 ps
T591 /workspace/coverage/default/18.hmac_test_hmac_vectors.4224275583 Jun 13 01:10:01 PM PDT 24 Jun 13 01:10:04 PM PDT 24 103228253 ps
T592 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2115899768 Jun 13 01:03:56 PM PDT 24 Jun 13 01:03:57 PM PDT 24 13625470 ps
T47 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2000373729 Jun 13 01:03:21 PM PDT 24 Jun 13 01:03:24 PM PDT 24 209180395 ps
T48 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3222764612 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:53 PM PDT 24 489035715 ps
T593 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2910944759 Jun 13 01:03:29 PM PDT 24 Jun 13 01:03:30 PM PDT 24 24086078 ps
T38 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.957246943 Jun 13 01:03:50 PM PDT 24 Jun 13 01:03:55 PM PDT 24 641246954 ps
T594 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1664509685 Jun 13 01:03:28 PM PDT 24 Jun 13 01:03:31 PM PDT 24 122735594 ps
T595 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2287013861 Jun 13 01:03:20 PM PDT 24 Jun 13 01:03:22 PM PDT 24 24332638 ps
T596 /workspace/coverage/cover_reg_top/45.hmac_intr_test.3173124056 Jun 13 01:03:57 PM PDT 24 Jun 13 01:04:00 PM PDT 24 48365205 ps
T597 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.751510679 Jun 13 01:03:50 PM PDT 24 Jun 13 01:03:52 PM PDT 24 78901983 ps
T74 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.672771976 Jun 13 01:03:36 PM PDT 24 Jun 13 01:03:38 PM PDT 24 89443174 ps
T598 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1881738152 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:53 PM PDT 24 279493787 ps
T599 /workspace/coverage/cover_reg_top/39.hmac_intr_test.663662 Jun 13 01:03:57 PM PDT 24 Jun 13 01:04:00 PM PDT 24 41346350 ps
T600 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3059053578 Jun 13 01:03:03 PM PDT 24 Jun 13 01:03:04 PM PDT 24 155598913 ps
T601 /workspace/coverage/cover_reg_top/17.hmac_intr_test.3752083320 Jun 13 01:03:50 PM PDT 24 Jun 13 01:03:52 PM PDT 24 13401074 ps
T602 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1829178344 Jun 13 01:03:15 PM PDT 24 Jun 13 01:03:17 PM PDT 24 24905881 ps
T603 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2327004324 Jun 13 01:03:28 PM PDT 24 Jun 13 01:03:29 PM PDT 24 113284185 ps
T604 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3876073171 Jun 13 01:03:48 PM PDT 24 Jun 13 01:13:46 PM PDT 24 237513935705 ps
T75 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1799171661 Jun 13 01:03:24 PM PDT 24 Jun 13 01:03:27 PM PDT 24 29568601 ps
T76 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3739646214 Jun 13 01:03:51 PM PDT 24 Jun 13 01:03:53 PM PDT 24 183005084 ps
T605 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.4018399912 Jun 13 01:03:51 PM PDT 24 Jun 13 01:03:53 PM PDT 24 48014283 ps
T39 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3000141838 Jun 13 01:03:02 PM PDT 24 Jun 13 01:03:07 PM PDT 24 205610726 ps
T606 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2496537377 Jun 13 01:03:08 PM PDT 24 Jun 13 01:03:10 PM PDT 24 299189417 ps
T607 /workspace/coverage/cover_reg_top/15.hmac_intr_test.639668155 Jun 13 01:03:42 PM PDT 24 Jun 13 01:03:43 PM PDT 24 11973582 ps
T608 /workspace/coverage/cover_reg_top/33.hmac_intr_test.55906041 Jun 13 01:03:54 PM PDT 24 Jun 13 01:03:55 PM PDT 24 12507122 ps
T609 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2111567348 Jun 13 01:03:21 PM PDT 24 Jun 13 01:03:23 PM PDT 24 23188328 ps
T610 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1887857916 Jun 13 01:03:26 PM PDT 24 Jun 13 01:03:28 PM PDT 24 184788046 ps
T611 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2021958872 Jun 13 01:03:28 PM PDT 24 Jun 13 01:03:30 PM PDT 24 220632447 ps
T612 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2813774194 Jun 13 01:03:36 PM PDT 24 Jun 13 01:03:41 PM PDT 24 294921652 ps
T613 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.122178638 Jun 13 01:03:11 PM PDT 24 Jun 13 01:03:15 PM PDT 24 235925110 ps
T614 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3593360228 Jun 13 01:03:28 PM PDT 24 Jun 13 01:03:29 PM PDT 24 13373802 ps
T615 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4126750502 Jun 13 01:03:22 PM PDT 24 Jun 13 01:03:24 PM PDT 24 63641944 ps
T40 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.825104772 Jun 13 01:03:41 PM PDT 24 Jun 13 01:03:45 PM PDT 24 204302376 ps
T616 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1346056863 Jun 13 01:03:53 PM PDT 24 Jun 13 01:03:54 PM PDT 24 14232290 ps
T617 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.326835748 Jun 13 01:03:34 PM PDT 24 Jun 13 01:03:36 PM PDT 24 417929435 ps
T618 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1908651909 Jun 13 01:03:44 PM PDT 24 Jun 13 01:03:46 PM PDT 24 583775639 ps
T619 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1459078672 Jun 13 01:03:22 PM PDT 24 Jun 13 01:03:27 PM PDT 24 184907533 ps
T77 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.492308602 Jun 13 01:03:08 PM PDT 24 Jun 13 01:03:17 PM PDT 24 454449635 ps
T620 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3910963812 Jun 13 01:03:09 PM PDT 24 Jun 13 01:03:11 PM PDT 24 166773461 ps
T621 /workspace/coverage/cover_reg_top/37.hmac_intr_test.197390243 Jun 13 01:03:55 PM PDT 24 Jun 13 01:03:56 PM PDT 24 44164606 ps
T622 /workspace/coverage/cover_reg_top/6.hmac_intr_test.3565946821 Jun 13 01:03:21 PM PDT 24 Jun 13 01:03:22 PM PDT 24 46543142 ps
T623 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.464879099 Jun 13 01:03:21 PM PDT 24 Jun 13 01:03:25 PM PDT 24 90586603 ps
T78 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.771571415 Jun 13 01:03:50 PM PDT 24 Jun 13 01:03:52 PM PDT 24 29107684 ps
T109 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.747872159 Jun 13 01:03:25 PM PDT 24 Jun 13 01:03:28 PM PDT 24 84963666 ps
T624 /workspace/coverage/cover_reg_top/43.hmac_intr_test.3987503850 Jun 13 01:03:57 PM PDT 24 Jun 13 01:03:59 PM PDT 24 60344807 ps
T104 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.931204265 Jun 13 01:03:33 PM PDT 24 Jun 13 01:03:36 PM PDT 24 104576758 ps
T625 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3581314996 Jun 13 01:03:16 PM PDT 24 Jun 13 01:03:18 PM PDT 24 18087870 ps
T79 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.158559491 Jun 13 01:03:06 PM PDT 24 Jun 13 01:03:12 PM PDT 24 764946848 ps
T626 /workspace/coverage/cover_reg_top/2.hmac_intr_test.1004926253 Jun 13 01:03:08 PM PDT 24 Jun 13 01:03:09 PM PDT 24 14456968 ps
T627 /workspace/coverage/cover_reg_top/48.hmac_intr_test.2306580349 Jun 13 01:03:56 PM PDT 24 Jun 13 01:03:59 PM PDT 24 30746007 ps
T100 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2624372294 Jun 13 01:03:36 PM PDT 24 Jun 13 01:03:42 PM PDT 24 1143755618 ps
T101 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3738899538 Jun 13 01:03:08 PM PDT 24 Jun 13 01:03:13 PM PDT 24 538715383 ps
T628 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.767329499 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:54 PM PDT 24 74462806 ps
T629 /workspace/coverage/cover_reg_top/23.hmac_intr_test.3779475359 Jun 13 01:03:50 PM PDT 24 Jun 13 01:03:52 PM PDT 24 15729648 ps
T630 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2621224825 Jun 13 01:03:52 PM PDT 24 Jun 13 01:03:54 PM PDT 24 389358416 ps
T631 /workspace/coverage/cover_reg_top/38.hmac_intr_test.3464756975 Jun 13 01:03:57 PM PDT 24 Jun 13 01:04:00 PM PDT 24 12809948 ps
T80 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3333543586 Jun 13 01:03:21 PM PDT 24 Jun 13 01:03:33 PM PDT 24 1097249896 ps
T81 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3505480941 Jun 13 01:03:53 PM PDT 24 Jun 13 01:03:55 PM PDT 24 132822302 ps
T632 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1396827351 Jun 13 01:03:42 PM PDT 24 Jun 13 01:03:44 PM PDT 24 57460005 ps
T105 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3668937759 Jun 13 01:03:40 PM PDT 24 Jun 13 01:03:44 PM PDT 24 2430545676 ps
T633 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.147471763 Jun 13 01:03:53 PM PDT 24 Jun 13 01:03:57 PM PDT 24 993385108 ps
T106 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.323046150 Jun 13 01:03:28 PM PDT 24 Jun 13 01:03:32 PM PDT 24 176285118 ps
T634 /workspace/coverage/cover_reg_top/42.hmac_intr_test.1980247819 Jun 13 01:03:57 PM PDT 24 Jun 13 01:04:00 PM PDT 24 72697406 ps
T82 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2942031730 Jun 13 01:03:42 PM PDT 24 Jun 13 01:03:44 PM PDT 24 33766537 ps
T635 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4294778836 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:53 PM PDT 24 105017560 ps
T636 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2854911474 Jun 13 01:03:40 PM PDT 24 Jun 13 01:03:42 PM PDT 24 164876232 ps
T83 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2134331637 Jun 13 01:03:14 PM PDT 24 Jun 13 01:03:32 PM PDT 24 3280512041 ps
T637 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1546154455 Jun 13 01:03:28 PM PDT 24 Jun 13 01:03:30 PM PDT 24 67446054 ps
T638 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2556427658 Jun 13 01:03:42 PM PDT 24 Jun 13 01:03:44 PM PDT 24 69293725 ps
T639 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2825584403 Jun 13 01:03:31 PM PDT 24 Jun 13 01:03:34 PM PDT 24 254766984 ps
T640 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.761836349 Jun 13 01:03:15 PM PDT 24 Jun 13 01:03:18 PM PDT 24 74106043 ps
T641 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3195914348 Jun 13 01:03:35 PM PDT 24 Jun 13 01:03:38 PM PDT 24 58256905 ps
T642 /workspace/coverage/cover_reg_top/47.hmac_intr_test.1894786584 Jun 13 01:03:57 PM PDT 24 Jun 13 01:03:59 PM PDT 24 30129429 ps
T643 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.9381567 Jun 13 01:03:15 PM PDT 24 Jun 13 01:03:17 PM PDT 24 18457508 ps
T84 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3267383996 Jun 13 01:03:08 PM PDT 24 Jun 13 01:03:24 PM PDT 24 1117377828 ps
T644 /workspace/coverage/cover_reg_top/44.hmac_intr_test.2105771389 Jun 13 01:03:57 PM PDT 24 Jun 13 01:03:59 PM PDT 24 14390085 ps
T645 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1776467563 Jun 13 01:03:02 PM PDT 24 Jun 13 01:03:03 PM PDT 24 153269943 ps
T646 /workspace/coverage/cover_reg_top/40.hmac_intr_test.3129105063 Jun 13 01:03:55 PM PDT 24 Jun 13 01:03:56 PM PDT 24 44808651 ps
T647 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.838122516 Jun 13 01:03:15 PM PDT 24 Jun 13 01:03:18 PM PDT 24 93160745 ps
T107 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2154720238 Jun 13 01:03:20 PM PDT 24 Jun 13 01:03:25 PM PDT 24 464121294 ps
T648 /workspace/coverage/cover_reg_top/32.hmac_intr_test.2179285058 Jun 13 01:03:58 PM PDT 24 Jun 13 01:04:00 PM PDT 24 25049430 ps
T649 /workspace/coverage/cover_reg_top/11.hmac_intr_test.2063760010 Jun 13 01:03:46 PM PDT 24 Jun 13 01:03:47 PM PDT 24 48659576 ps
T650 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1192637241 Jun 13 01:03:15 PM PDT 24 Jun 13 01:03:21 PM PDT 24 206090245 ps
T651 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2090010691 Jun 13 01:03:22 PM PDT 24 Jun 13 01:03:26 PM PDT 24 110941916 ps
T652 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3400964297 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:51 PM PDT 24 44989449 ps
T102 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.149728117 Jun 13 01:03:14 PM PDT 24 Jun 13 01:03:18 PM PDT 24 121589858 ps
T653 /workspace/coverage/cover_reg_top/19.hmac_intr_test.2571712837 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:51 PM PDT 24 13698774 ps
T654 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3576902823 Jun 13 01:03:50 PM PDT 24 Jun 13 01:03:52 PM PDT 24 98999415 ps
T655 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4187587123 Jun 13 01:03:30 PM PDT 24 Jun 13 01:03:32 PM PDT 24 115589674 ps
T656 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3007393394 Jun 13 01:03:20 PM PDT 24 Jun 13 01:03:22 PM PDT 24 101748256 ps
T657 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.661619128 Jun 13 01:03:10 PM PDT 24 Jun 13 01:03:11 PM PDT 24 61732425 ps
T85 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3345158840 Jun 13 01:03:02 PM PDT 24 Jun 13 01:03:03 PM PDT 24 43984737 ps
T658 /workspace/coverage/cover_reg_top/31.hmac_intr_test.1111272114 Jun 13 01:03:56 PM PDT 24 Jun 13 01:03:57 PM PDT 24 12475574 ps
T659 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2315457837 Jun 13 01:03:21 PM PDT 24 Jun 13 01:03:23 PM PDT 24 274703612 ps
T660 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4050399468 Jun 13 01:03:42 PM PDT 24 Jun 13 01:03:46 PM PDT 24 215912923 ps
T661 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3984083110 Jun 13 01:03:07 PM PDT 24 Jun 13 01:03:09 PM PDT 24 105319941 ps
T662 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3280215899 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:51 PM PDT 24 22167115 ps
T663 /workspace/coverage/cover_reg_top/34.hmac_intr_test.1788281822 Jun 13 01:03:56 PM PDT 24 Jun 13 01:03:57 PM PDT 24 17183609 ps
T664 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3013546540 Jun 13 01:03:08 PM PDT 24 Jun 13 01:03:11 PM PDT 24 150618571 ps
T665 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2538479226 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:52 PM PDT 24 75083052 ps
T666 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3280740955 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:55 PM PDT 24 321388844 ps
T667 /workspace/coverage/cover_reg_top/28.hmac_intr_test.880807314 Jun 13 01:03:57 PM PDT 24 Jun 13 01:03:59 PM PDT 24 114292169 ps
T668 /workspace/coverage/cover_reg_top/36.hmac_intr_test.1000196774 Jun 13 01:03:57 PM PDT 24 Jun 13 01:04:00 PM PDT 24 13284376 ps
T669 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.386009738 Jun 13 01:03:34 PM PDT 24 Jun 13 01:03:39 PM PDT 24 689151822 ps
T670 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2766742687 Jun 13 01:03:35 PM PDT 24 Jun 13 01:03:37 PM PDT 24 45989884 ps
T671 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3978085643 Jun 13 01:03:20 PM PDT 24 Jun 13 01:16:23 PM PDT 24 646846436326 ps
T672 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1369406085 Jun 13 01:03:07 PM PDT 24 Jun 13 01:03:09 PM PDT 24 73365529 ps
T673 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2733819207 Jun 13 01:03:27 PM PDT 24 Jun 13 01:03:29 PM PDT 24 37587312 ps
T674 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1846370326 Jun 13 01:03:14 PM PDT 24 Jun 13 01:03:25 PM PDT 24 218496135 ps
T675 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3475191559 Jun 13 01:03:21 PM PDT 24 Jun 13 01:03:23 PM PDT 24 126602778 ps
T676 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1541038425 Jun 13 01:03:29 PM PDT 24 Jun 13 01:03:32 PM PDT 24 287309050 ps
T677 /workspace/coverage/cover_reg_top/13.hmac_intr_test.3608927070 Jun 13 01:03:43 PM PDT 24 Jun 13 01:03:44 PM PDT 24 22695999 ps
T678 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3033891842 Jun 13 01:03:28 PM PDT 24 Jun 13 01:03:30 PM PDT 24 89862910 ps
T679 /workspace/coverage/cover_reg_top/41.hmac_intr_test.851621479 Jun 13 01:03:57 PM PDT 24 Jun 13 01:03:59 PM PDT 24 13047566 ps
T680 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3133864487 Jun 13 01:03:20 PM PDT 24 Jun 13 01:03:21 PM PDT 24 18680100 ps
T681 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1355082065 Jun 13 01:03:50 PM PDT 24 Jun 13 01:03:53 PM PDT 24 406116031 ps
T682 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2571679442 Jun 13 01:03:22 PM PDT 24 Jun 13 01:03:25 PM PDT 24 123255739 ps
T683 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3061625999 Jun 13 01:03:57 PM PDT 24 Jun 13 01:04:00 PM PDT 24 65294063 ps
T684 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3582534226 Jun 13 01:03:48 PM PDT 24 Jun 13 01:03:51 PM PDT 24 111103149 ps
T685 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.879045344 Jun 13 01:03:42 PM PDT 24 Jun 13 01:03:45 PM PDT 24 133702447 ps
T686 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3432371239 Jun 13 01:03:28 PM PDT 24 Jun 13 01:03:32 PM PDT 24 589070145 ps
T687 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4274501222 Jun 13 01:03:08 PM PDT 24 Jun 13 01:03:10 PM PDT 24 72069426 ps
T688 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1333616665 Jun 13 01:03:02 PM PDT 24 Jun 13 01:03:05 PM PDT 24 42557537 ps
T689 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.764735188 Jun 13 01:03:08 PM PDT 24 Jun 13 01:03:10 PM PDT 24 403249234 ps
T690 /workspace/coverage/cover_reg_top/10.hmac_intr_test.861786181 Jun 13 01:03:29 PM PDT 24 Jun 13 01:03:30 PM PDT 24 14981325 ps
T691 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1376344319 Jun 13 01:03:29 PM PDT 24 Jun 13 01:03:31 PM PDT 24 61775553 ps
T692 /workspace/coverage/cover_reg_top/3.hmac_intr_test.2222578035 Jun 13 01:03:16 PM PDT 24 Jun 13 01:03:17 PM PDT 24 18804076 ps
T693 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3488124837 Jun 13 01:03:54 PM PDT 24 Jun 13 01:03:58 PM PDT 24 90845534 ps
T694 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3133606002 Jun 13 01:03:27 PM PDT 24 Jun 13 01:03:30 PM PDT 24 568650454 ps
T695 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3734883979 Jun 13 01:03:35 PM PDT 24 Jun 13 01:03:38 PM PDT 24 227878057 ps
T696 /workspace/coverage/cover_reg_top/35.hmac_intr_test.1805192263 Jun 13 01:03:56 PM PDT 24 Jun 13 01:03:59 PM PDT 24 25106649 ps
T697 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2849377845 Jun 13 01:03:09 PM PDT 24 Jun 13 01:03:11 PM PDT 24 50695279 ps
T698 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3933843465 Jun 13 01:03:53 PM PDT 24 Jun 13 01:03:54 PM PDT 24 11763782 ps
T699 /workspace/coverage/cover_reg_top/30.hmac_intr_test.2808325635 Jun 13 01:03:57 PM PDT 24 Jun 13 01:04:00 PM PDT 24 14438145 ps
T700 /workspace/coverage/cover_reg_top/14.hmac_intr_test.3744654192 Jun 13 01:03:43 PM PDT 24 Jun 13 01:03:44 PM PDT 24 12600029 ps
T103 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2139480176 Jun 13 01:03:22 PM PDT 24 Jun 13 01:03:29 PM PDT 24 273128115 ps
T701 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2564137158 Jun 13 01:03:36 PM PDT 24 Jun 13 01:05:25 PM PDT 24 7629318487 ps
T702 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2704414696 Jun 13 01:03:27 PM PDT 24 Jun 13 01:03:32 PM PDT 24 900825329 ps
T703 /workspace/coverage/cover_reg_top/27.hmac_intr_test.567817861 Jun 13 01:03:59 PM PDT 24 Jun 13 01:04:01 PM PDT 24 32097583 ps
T704 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3980503107 Jun 13 01:03:52 PM PDT 24 Jun 13 01:03:53 PM PDT 24 46359125 ps
T705 /workspace/coverage/cover_reg_top/7.hmac_intr_test.2317825606 Jun 13 01:03:23 PM PDT 24 Jun 13 01:03:26 PM PDT 24 17416592 ps
T706 /workspace/coverage/cover_reg_top/5.hmac_intr_test.3366082530 Jun 13 01:03:21 PM PDT 24 Jun 13 01:03:23 PM PDT 24 12264583 ps
T707 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1868121254 Jun 13 01:03:37 PM PDT 24 Jun 13 01:03:39 PM PDT 24 53681280 ps
T708 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.490462529 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:51 PM PDT 24 55801724 ps
T709 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.626274421 Jun 13 01:03:34 PM PDT 24 Jun 13 01:09:56 PM PDT 24 27653368902 ps
T710 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2518360381 Jun 13 01:03:14 PM PDT 24 Jun 13 01:03:17 PM PDT 24 40408529 ps
T711 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3774248142 Jun 13 01:03:21 PM PDT 24 Jun 13 01:03:26 PM PDT 24 459340870 ps
T108 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2101615387 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:54 PM PDT 24 2219942074 ps
T712 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4209948293 Jun 13 01:03:14 PM PDT 24 Jun 13 01:03:16 PM PDT 24 139646490 ps
T713 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2317672048 Jun 13 01:03:36 PM PDT 24 Jun 13 01:03:41 PM PDT 24 234561485 ps
T714 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1727783632 Jun 13 01:03:27 PM PDT 24 Jun 13 01:03:29 PM PDT 24 12267886 ps
T715 /workspace/coverage/cover_reg_top/1.hmac_intr_test.2974334512 Jun 13 01:03:09 PM PDT 24 Jun 13 01:03:10 PM PDT 24 21608546 ps
T716 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2899779488 Jun 13 01:03:52 PM PDT 24 Jun 13 01:03:55 PM PDT 24 45352434 ps
T717 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3522371026 Jun 13 01:03:52 PM PDT 24 Jun 13 01:03:53 PM PDT 24 13813298 ps
T718 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2594207800 Jun 13 01:03:29 PM PDT 24 Jun 13 01:03:31 PM PDT 24 38511445 ps
T719 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2150100761 Jun 13 01:03:15 PM PDT 24 Jun 13 01:03:19 PM PDT 24 192622674 ps
T720 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2246679975 Jun 13 01:03:23 PM PDT 24 Jun 13 01:03:34 PM PDT 24 447162934 ps
T721 /workspace/coverage/cover_reg_top/24.hmac_intr_test.4240565129 Jun 13 01:03:52 PM PDT 24 Jun 13 01:03:53 PM PDT 24 15032960 ps
T722 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1291793928 Jun 13 01:03:42 PM PDT 24 Jun 13 01:03:45 PM PDT 24 175155357 ps
T723 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2198543810 Jun 13 01:03:16 PM PDT 24 Jun 13 01:03:19 PM PDT 24 46200147 ps
T724 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4210118592 Jun 13 01:03:16 PM PDT 24 Jun 13 01:03:19 PM PDT 24 40026459 ps
T725 /workspace/coverage/cover_reg_top/18.hmac_intr_test.2736049177 Jun 13 01:03:51 PM PDT 24 Jun 13 01:03:52 PM PDT 24 115346060 ps
T726 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2412207737 Jun 13 01:03:22 PM PDT 24 Jun 13 01:03:26 PM PDT 24 46460409 ps
T727 /workspace/coverage/cover_reg_top/46.hmac_intr_test.648543249 Jun 13 01:03:58 PM PDT 24 Jun 13 01:04:00 PM PDT 24 13739486 ps
T110 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.431662747 Jun 13 01:03:49 PM PDT 24 Jun 13 01:03:53 PM PDT 24 359672465 ps
T728 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.8776844 Jun 13 01:03:09 PM PDT 24 Jun 13 01:03:16 PM PDT 24 2409209553 ps

Test location /workspace/coverage/default/9.hmac_error.2798493930
Short name T2
Test name
Test status
Simulation time 38267850342 ps
CPU time 85.5 seconds
Started Jun 13 01:09:39 PM PDT 24
Finished Jun 13 01:11:06 PM PDT 24
Peak memory 199844 kb
Host smart-2e4003af-e54c-4f2f-8de1-6831bbc08eae
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798493930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2798493930
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/165.hmac_stress_all_with_rand_reset.1165555582
Short name T7
Test name
Test status
Simulation time 248170582485 ps
CPU time 5244.28 seconds
Started Jun 13 01:11:22 PM PDT 24
Finished Jun 13 02:38:48 PM PDT 24
Peak memory 890816 kb
Host smart-859f8b04-3066-4f8e-bbe1-dd21bc01ebff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1165555582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 165.hmac_stress_all_with_rand_reset.1165555582
Directory /workspace/165.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.hmac_stress_all.3590293253
Short name T3
Test name
Test status
Simulation time 3563090691 ps
CPU time 173.96 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:14:03 PM PDT 24
Peak memory 232036 kb
Host smart-39f7a378-f0f3-4bca-b0df-635d5f96b94d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590293253 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.3590293253
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.341812979
Short name T23
Test name
Test status
Simulation time 334773936 ps
CPU time 0.83 seconds
Started Jun 13 01:09:37 PM PDT 24
Finished Jun 13 01:09:38 PM PDT 24
Peak memory 218080 kb
Host smart-9f584345-669e-4155-998d-5837a773c094
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341812979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.341812979
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/45.hmac_stress_all.1839253463
Short name T46
Test name
Test status
Simulation time 97924552031 ps
CPU time 1342.56 seconds
Started Jun 13 01:26:01 PM PDT 24
Finished Jun 13 01:48:26 PM PDT 24
Peak memory 681596 kb
Host smart-bb33f161-cd74-43d6-b201-5045350b0464
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839253463 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.1839253463
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.957246943
Short name T38
Test name
Test status
Simulation time 641246954 ps
CPU time 4.05 seconds
Started Jun 13 01:03:50 PM PDT 24
Finished Jun 13 01:03:55 PM PDT 24
Peak memory 199692 kb
Host smart-974bbe01-2c18-4527-b2d9-9543002d70d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957246943 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.957246943
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/193.hmac_stress_all_with_rand_reset.852201771
Short name T12
Test name
Test status
Simulation time 125038051763 ps
CPU time 3089.91 seconds
Started Jun 13 01:11:30 PM PDT 24
Finished Jun 13 02:03:02 PM PDT 24
Peak memory 690912 kb
Host smart-bf25cf14-b833-4c96-bd9d-bd2b7cd6b353
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852201771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 193.hmac_stress_all_with_rand_reset.852201771
Directory /workspace/193.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.hmac_stress_all_with_rand_reset.3326853267
Short name T10
Test name
Test status
Simulation time 75062019405 ps
CPU time 1961.8 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:43:39 PM PDT 24
Peak memory 313344 kb
Host smart-8feefa27-d541-4cdc-bdcd-3e3cab827329
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3326853267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all_with_rand_reset.3326853267
Directory /workspace/34.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.672771976
Short name T74
Test name
Test status
Simulation time 89443174 ps
CPU time 0.87 seconds
Started Jun 13 01:03:36 PM PDT 24
Finished Jun 13 01:03:38 PM PDT 24
Peak memory 199040 kb
Host smart-9ffb7a7c-e940-4d58-966e-f2ce7f35c4ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672771976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.672771976
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.3738899538
Short name T101
Test name
Test status
Simulation time 538715383 ps
CPU time 3.98 seconds
Started Jun 13 01:03:08 PM PDT 24
Finished Jun 13 01:03:13 PM PDT 24
Peak memory 199676 kb
Host smart-34775ac8-0fa1-4d4c-9761-b3cd58a6d3e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738899538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.3738899538
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/25.hmac_stress_all.2882099443
Short name T66
Test name
Test status
Simulation time 118247370604 ps
CPU time 3043.85 seconds
Started Jun 13 01:10:19 PM PDT 24
Finished Jun 13 02:01:04 PM PDT 24
Peak memory 835680 kb
Host smart-7953d586-eaee-40a1-8e10-c7381f7fbf3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882099443 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.2882099443
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_alert_test.2531446839
Short name T178
Test name
Test status
Simulation time 13598685 ps
CPU time 0.6 seconds
Started Jun 13 01:09:28 PM PDT 24
Finished Jun 13 01:09:30 PM PDT 24
Peak memory 195988 kb
Host smart-90157b29-cf98-4059-b541-f2c9d514b041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531446839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.2531446839
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_stress_all.3356158071
Short name T95
Test name
Test status
Simulation time 7725708074 ps
CPU time 841.05 seconds
Started Jun 13 01:09:43 PM PDT 24
Finished Jun 13 01:23:45 PM PDT 24
Peak memory 751652 kb
Host smart-9b1532fa-782f-4b21-95e3-5355f1cb472e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356158071 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.3356158071
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_long_msg.1450310611
Short name T91
Test name
Test status
Simulation time 3291351835 ps
CPU time 99.94 seconds
Started Jun 13 01:10:06 PM PDT 24
Finished Jun 13 01:11:47 PM PDT 24
Peak memory 199732 kb
Host smart-a808c7f3-d8e4-4da0-8a1a-821426b5fc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450310611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.1450310611
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1783560742
Short name T87
Test name
Test status
Simulation time 2040153860 ps
CPU time 124.75 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:13:13 PM PDT 24
Peak memory 199664 kb
Host smart-80e3feff-82b5-4c84-aeb7-355a60f0e606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783560742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1783560742
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.323046150
Short name T106
Test name
Test status
Simulation time 176285118 ps
CPU time 3.14 seconds
Started Jun 13 01:03:28 PM PDT 24
Finished Jun 13 01:03:32 PM PDT 24
Peak memory 199708 kb
Host smart-f7ece2d7-9948-4fc3-b95c-cd872eae383a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323046150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.323046150
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2624372294
Short name T100
Test name
Test status
Simulation time 1143755618 ps
CPU time 4.63 seconds
Started Jun 13 01:03:36 PM PDT 24
Finished Jun 13 01:03:42 PM PDT 24
Peak memory 199644 kb
Host smart-9e75461f-a83a-49dd-9c7d-4d2477d5ae78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624372294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2624372294
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_stress_all.796485537
Short name T34
Test name
Test status
Simulation time 44751993844 ps
CPU time 592.47 seconds
Started Jun 13 01:09:23 PM PDT 24
Finished Jun 13 01:19:16 PM PDT 24
Peak memory 232424 kb
Host smart-8ee18d78-cbdf-4ad3-b228-8a550503dc84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796485537 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.796485537
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.189902136
Short name T92
Test name
Test status
Simulation time 2401905837 ps
CPU time 35.27 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:10:23 PM PDT 24
Peak memory 199848 kb
Host smart-290894d0-6d75-43b4-8879-29c0bf9cda03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189902136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.189902136
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_long_msg.479426263
Short name T90
Test name
Test status
Simulation time 1289776157 ps
CPU time 57.73 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:11:53 PM PDT 24
Peak memory 199840 kb
Host smart-0f53d230-7d52-4890-ac0b-bf97de375440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479426263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.479426263
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_stress_all.2248424689
Short name T86
Test name
Test status
Simulation time 19919301413 ps
CPU time 1950.54 seconds
Started Jun 13 01:09:32 PM PDT 24
Finished Jun 13 01:42:04 PM PDT 24
Peak memory 559052 kb
Host smart-cf03b8c2-3e92-4b00-97d1-15344f2dd5f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248424689 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.2248424689
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_stress_all.258835131
Short name T94
Test name
Test status
Simulation time 76163242034 ps
CPU time 1398.38 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:34:29 PM PDT 24
Peak memory 241816 kb
Host smart-f2cb4335-72fb-4d1a-a511-9248ef6882e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258835131 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.258835131
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1431356171
Short name T96
Test name
Test status
Simulation time 9209091909 ps
CPU time 34.46 seconds
Started Jun 13 01:09:37 PM PDT 24
Finished Jun 13 01:10:12 PM PDT 24
Peak memory 199916 kb
Host smart-6cb97646-7cca-4a51-8a6b-491b13bda482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431356171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1431356171
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.492308602
Short name T77
Test name
Test status
Simulation time 454449635 ps
CPU time 8.92 seconds
Started Jun 13 01:03:08 PM PDT 24
Finished Jun 13 01:03:17 PM PDT 24
Peak memory 199628 kb
Host smart-ea24245d-ec6b-4271-a531-697e79370ddf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492308602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.492308602
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.3267383996
Short name T84
Test name
Test status
Simulation time 1117377828 ps
CPU time 14.7 seconds
Started Jun 13 01:03:08 PM PDT 24
Finished Jun 13 01:03:24 PM PDT 24
Peak memory 199608 kb
Host smart-b3573178-e810-455b-9565-db7b809b7361
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267383996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.3267383996
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.3345158840
Short name T85
Test name
Test status
Simulation time 43984737 ps
CPU time 0.99 seconds
Started Jun 13 01:03:02 PM PDT 24
Finished Jun 13 01:03:03 PM PDT 24
Peak memory 199156 kb
Host smart-f777edc7-2933-4bad-9b90-c2edca8ae527
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345158840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.3345158840
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3910963812
Short name T620
Test name
Test status
Simulation time 166773461 ps
CPU time 1.15 seconds
Started Jun 13 01:03:09 PM PDT 24
Finished Jun 13 01:03:11 PM PDT 24
Peak memory 199512 kb
Host smart-68263e8e-e374-47cc-b397-f3c31c908bd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910963812 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3910963812
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3059053578
Short name T600
Test name
Test status
Simulation time 155598913 ps
CPU time 0.72 seconds
Started Jun 13 01:03:03 PM PDT 24
Finished Jun 13 01:03:04 PM PDT 24
Peak memory 197704 kb
Host smart-13c0f7c9-5ba4-4d38-a830-455e9a81f773
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059053578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3059053578
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1776467563
Short name T645
Test name
Test status
Simulation time 153269943 ps
CPU time 0.61 seconds
Started Jun 13 01:03:02 PM PDT 24
Finished Jun 13 01:03:03 PM PDT 24
Peak memory 194548 kb
Host smart-6f8b539a-63ca-447a-bed6-6e307e2a98b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776467563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1776467563
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.4274501222
Short name T687
Test name
Test status
Simulation time 72069426 ps
CPU time 1.16 seconds
Started Jun 13 01:03:08 PM PDT 24
Finished Jun 13 01:03:10 PM PDT 24
Peak memory 199524 kb
Host smart-0ee1ac55-0b8e-4bd0-b6a5-085ba518ac32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274501222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.4274501222
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.1333616665
Short name T688
Test name
Test status
Simulation time 42557537 ps
CPU time 2.28 seconds
Started Jun 13 01:03:02 PM PDT 24
Finished Jun 13 01:03:05 PM PDT 24
Peak memory 199720 kb
Host smart-a16c8330-743a-4ff6-9a41-feb07986863c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333616665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.1333616665
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3000141838
Short name T39
Test name
Test status
Simulation time 205610726 ps
CPU time 4.13 seconds
Started Jun 13 01:03:02 PM PDT 24
Finished Jun 13 01:03:07 PM PDT 24
Peak memory 199608 kb
Host smart-f1b34c33-9de1-4c28-b61e-7b055c2a3a6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000141838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3000141838
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.158559491
Short name T79
Test name
Test status
Simulation time 764946848 ps
CPU time 5.77 seconds
Started Jun 13 01:03:06 PM PDT 24
Finished Jun 13 01:03:12 PM PDT 24
Peak memory 199388 kb
Host smart-435f889a-b006-428e-9a5d-4a745744305a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158559491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.158559491
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.8776844
Short name T728
Test name
Test status
Simulation time 2409209553 ps
CPU time 6.34 seconds
Started Jun 13 01:03:09 PM PDT 24
Finished Jun 13 01:03:16 PM PDT 24
Peak memory 199704 kb
Host smart-ae1b08ee-7656-4223-9633-d6e50daf7cca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8776844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.8776844
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.1369406085
Short name T672
Test name
Test status
Simulation time 73365529 ps
CPU time 0.98 seconds
Started Jun 13 01:03:07 PM PDT 24
Finished Jun 13 01:03:09 PM PDT 24
Peak memory 199452 kb
Host smart-750fa269-f1a2-4426-8c1f-8adc18ff6ef3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369406085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.1369406085
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.764735188
Short name T689
Test name
Test status
Simulation time 403249234 ps
CPU time 1.39 seconds
Started Jun 13 01:03:08 PM PDT 24
Finished Jun 13 01:03:10 PM PDT 24
Peak memory 199736 kb
Host smart-b640edf5-def8-4082-9fd4-28d51db6701c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764735188 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.764735188
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.661619128
Short name T657
Test name
Test status
Simulation time 61732425 ps
CPU time 0.71 seconds
Started Jun 13 01:03:10 PM PDT 24
Finished Jun 13 01:03:11 PM PDT 24
Peak memory 197608 kb
Host smart-873778d7-1ec5-493e-ae37-d8a6aba9211e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661619128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.661619128
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.2974334512
Short name T715
Test name
Test status
Simulation time 21608546 ps
CPU time 0.59 seconds
Started Jun 13 01:03:09 PM PDT 24
Finished Jun 13 01:03:10 PM PDT 24
Peak memory 194580 kb
Host smart-9340bf78-fb82-4337-883f-4b3c8a305a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974334512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.2974334512
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.2849377845
Short name T697
Test name
Test status
Simulation time 50695279 ps
CPU time 1.09 seconds
Started Jun 13 01:03:09 PM PDT 24
Finished Jun 13 01:03:11 PM PDT 24
Peak memory 199612 kb
Host smart-4b04897e-50eb-4dfe-b8a9-307717289889
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849377845 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr
_outstanding.2849377845
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.122178638
Short name T613
Test name
Test status
Simulation time 235925110 ps
CPU time 3.38 seconds
Started Jun 13 01:03:11 PM PDT 24
Finished Jun 13 01:03:15 PM PDT 24
Peak memory 199776 kb
Host smart-38164b9a-0cfc-43be-bff4-b4e2d2c89e59
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122178638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.122178638
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.2594207800
Short name T718
Test name
Test status
Simulation time 38511445 ps
CPU time 1.23 seconds
Started Jun 13 01:03:29 PM PDT 24
Finished Jun 13 01:03:31 PM PDT 24
Peak memory 199536 kb
Host smart-91833844-2bdf-4e0a-8f0e-57ab3dc57552
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594207800 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.2594207800
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.1727783632
Short name T714
Test name
Test status
Simulation time 12267886 ps
CPU time 0.67 seconds
Started Jun 13 01:03:27 PM PDT 24
Finished Jun 13 01:03:29 PM PDT 24
Peak memory 197520 kb
Host smart-5b9a30c1-1f32-4386-a875-5d28674f03dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727783632 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.1727783632
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.861786181
Short name T690
Test name
Test status
Simulation time 14981325 ps
CPU time 0.59 seconds
Started Jun 13 01:03:29 PM PDT 24
Finished Jun 13 01:03:30 PM PDT 24
Peak memory 194560 kb
Host smart-6d0221d3-8e84-4a5e-a6dd-b4ccfb0809da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861786181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.861786181
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.3432371239
Short name T686
Test name
Test status
Simulation time 589070145 ps
CPU time 2.39 seconds
Started Jun 13 01:03:28 PM PDT 24
Finished Jun 13 01:03:32 PM PDT 24
Peak memory 199640 kb
Host smart-83b58715-07f7-43c8-9519-23e2f1301e2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432371239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.3432371239
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.1664509685
Short name T594
Test name
Test status
Simulation time 122735594 ps
CPU time 2.5 seconds
Started Jun 13 01:03:28 PM PDT 24
Finished Jun 13 01:03:31 PM PDT 24
Peak memory 199724 kb
Host smart-25c0f7a2-9ca8-46aa-8b15-acca1d33dda0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664509685 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.1664509685
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.626274421
Short name T709
Test name
Test status
Simulation time 27653368902 ps
CPU time 381.4 seconds
Started Jun 13 01:03:34 PM PDT 24
Finished Jun 13 01:09:56 PM PDT 24
Peak memory 215312 kb
Host smart-168e4e7d-01b4-4f64-8030-cde604b6c0ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626274421 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.626274421
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.2063760010
Short name T649
Test name
Test status
Simulation time 48659576 ps
CPU time 0.63 seconds
Started Jun 13 01:03:46 PM PDT 24
Finished Jun 13 01:03:47 PM PDT 24
Peak memory 194612 kb
Host smart-4eb33762-0146-43d0-a48c-51139265f3d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063760010 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.2063760010
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.3734883979
Short name T695
Test name
Test status
Simulation time 227878057 ps
CPU time 1.19 seconds
Started Jun 13 01:03:35 PM PDT 24
Finished Jun 13 01:03:38 PM PDT 24
Peak memory 199704 kb
Host smart-66bbdf09-dacf-49a6-be10-566fdd4e7e0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734883979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.3734883979
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.2813774194
Short name T612
Test name
Test status
Simulation time 294921652 ps
CPU time 3.87 seconds
Started Jun 13 01:03:36 PM PDT 24
Finished Jun 13 01:03:41 PM PDT 24
Peak memory 199752 kb
Host smart-10633ea2-bb8d-4b09-8fc8-64dabaf98615
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813774194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.2813774194
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.931204265
Short name T104
Test name
Test status
Simulation time 104576758 ps
CPU time 1.82 seconds
Started Jun 13 01:03:33 PM PDT 24
Finished Jun 13 01:03:36 PM PDT 24
Peak memory 199688 kb
Host smart-04ac0914-c567-455d-96f8-9b8f8e0776ef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931204265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.931204265
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.2564137158
Short name T701
Test name
Test status
Simulation time 7629318487 ps
CPU time 107.76 seconds
Started Jun 13 01:03:36 PM PDT 24
Finished Jun 13 01:05:25 PM PDT 24
Peak memory 215664 kb
Host smart-3ff74a41-57f1-41b0-9d16-64707c02b7f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564137158 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.2564137158
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.1868121254
Short name T707
Test name
Test status
Simulation time 53681280 ps
CPU time 0.72 seconds
Started Jun 13 01:03:37 PM PDT 24
Finished Jun 13 01:03:39 PM PDT 24
Peak memory 197668 kb
Host smart-5857eaed-67c2-4021-8e0b-fd47eaae2974
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868121254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.1868121254
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2766742687
Short name T670
Test name
Test status
Simulation time 45989884 ps
CPU time 0.62 seconds
Started Jun 13 01:03:35 PM PDT 24
Finished Jun 13 01:03:37 PM PDT 24
Peak memory 194548 kb
Host smart-75c019dd-c547-40c5-be34-c0528d0f9e71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766742687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2766742687
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.326835748
Short name T617
Test name
Test status
Simulation time 417929435 ps
CPU time 1.86 seconds
Started Jun 13 01:03:34 PM PDT 24
Finished Jun 13 01:03:36 PM PDT 24
Peak memory 199668 kb
Host smart-b70c4762-8e7e-43ff-88fb-3ee66bcbdca6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326835748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_csr
_outstanding.326835748
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.3195914348
Short name T641
Test name
Test status
Simulation time 58256905 ps
CPU time 1.72 seconds
Started Jun 13 01:03:35 PM PDT 24
Finished Jun 13 01:03:38 PM PDT 24
Peak memory 199648 kb
Host smart-54cf181a-f686-4c83-ab33-20a1f4e9d219
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195914348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.3195914348
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4050399468
Short name T660
Test name
Test status
Simulation time 215912923 ps
CPU time 2.62 seconds
Started Jun 13 01:03:42 PM PDT 24
Finished Jun 13 01:03:46 PM PDT 24
Peak memory 207928 kb
Host smart-1d72df15-6ae1-4324-9dce-2aa160859e9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050399468 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.4050399468
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2942031730
Short name T82
Test name
Test status
Simulation time 33766537 ps
CPU time 0.94 seconds
Started Jun 13 01:03:42 PM PDT 24
Finished Jun 13 01:03:44 PM PDT 24
Peak memory 199312 kb
Host smart-ea89a892-df79-477c-96b7-5b2bf421ed0e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942031730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2942031730
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.3608927070
Short name T677
Test name
Test status
Simulation time 22695999 ps
CPU time 0.61 seconds
Started Jun 13 01:03:43 PM PDT 24
Finished Jun 13 01:03:44 PM PDT 24
Peak memory 194636 kb
Host smart-ea9c40ff-0cb6-49f1-9edc-b59e8969dbf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608927070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.3608927070
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.879045344
Short name T685
Test name
Test status
Simulation time 133702447 ps
CPU time 2.26 seconds
Started Jun 13 01:03:42 PM PDT 24
Finished Jun 13 01:03:45 PM PDT 24
Peak memory 199676 kb
Host smart-03ed4f66-fef2-4725-a377-94bb850c36af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879045344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_csr
_outstanding.879045344
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2317672048
Short name T713
Test name
Test status
Simulation time 234561485 ps
CPU time 4.33 seconds
Started Jun 13 01:03:36 PM PDT 24
Finished Jun 13 01:03:41 PM PDT 24
Peak memory 199784 kb
Host smart-96511647-7af9-4c95-aa8d-2825366bd425
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317672048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2317672048
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.386009738
Short name T669
Test name
Test status
Simulation time 689151822 ps
CPU time 4.04 seconds
Started Jun 13 01:03:34 PM PDT 24
Finished Jun 13 01:03:39 PM PDT 24
Peak memory 199708 kb
Host smart-f8548a97-8a91-4f67-86c9-0a7e94099589
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386009738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.386009738
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.1291793928
Short name T722
Test name
Test status
Simulation time 175155357 ps
CPU time 1.27 seconds
Started Jun 13 01:03:42 PM PDT 24
Finished Jun 13 01:03:45 PM PDT 24
Peak memory 199784 kb
Host smart-6fba2339-d48f-4dd6-9d8d-c91b52acc26e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291793928 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.1291793928
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2556427658
Short name T638
Test name
Test status
Simulation time 69293725 ps
CPU time 0.84 seconds
Started Jun 13 01:03:42 PM PDT 24
Finished Jun 13 01:03:44 PM PDT 24
Peak memory 198784 kb
Host smart-15c25264-b8f8-4284-a589-2aa6e91abbf6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556427658 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2556427658
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3744654192
Short name T700
Test name
Test status
Simulation time 12600029 ps
CPU time 0.64 seconds
Started Jun 13 01:03:43 PM PDT 24
Finished Jun 13 01:03:44 PM PDT 24
Peak memory 194520 kb
Host smart-c973fea8-c70d-4261-ae17-4f6d978cf19b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744654192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3744654192
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.1396827351
Short name T632
Test name
Test status
Simulation time 57460005 ps
CPU time 1.24 seconds
Started Jun 13 01:03:42 PM PDT 24
Finished Jun 13 01:03:44 PM PDT 24
Peak memory 199724 kb
Host smart-88bd2230-deac-4c56-a33e-97f11b713573
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396827351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.1396827351
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1908651909
Short name T618
Test name
Test status
Simulation time 583775639 ps
CPU time 2.06 seconds
Started Jun 13 01:03:44 PM PDT 24
Finished Jun 13 01:03:46 PM PDT 24
Peak memory 199744 kb
Host smart-62fa8af4-9e51-4125-9b6d-9f1444845220
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908651909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1908651909
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3668937759
Short name T105
Test name
Test status
Simulation time 2430545676 ps
CPU time 3.13 seconds
Started Jun 13 01:03:40 PM PDT 24
Finished Jun 13 01:03:44 PM PDT 24
Peak memory 199796 kb
Host smart-2abc0020-6aa8-418e-830c-f3906a9fb27c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668937759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3668937759
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.3488124837
Short name T693
Test name
Test status
Simulation time 90845534 ps
CPU time 2.29 seconds
Started Jun 13 01:03:54 PM PDT 24
Finished Jun 13 01:03:58 PM PDT 24
Peak memory 199760 kb
Host smart-768b35af-96c9-4a91-b659-dd80f036809e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488124837 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.3488124837
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3505480941
Short name T81
Test name
Test status
Simulation time 132822302 ps
CPU time 0.99 seconds
Started Jun 13 01:03:53 PM PDT 24
Finished Jun 13 01:03:55 PM PDT 24
Peak memory 199284 kb
Host smart-157cce5b-9bc5-47ad-a1b3-55795c82deb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505480941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3505480941
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.639668155
Short name T607
Test name
Test status
Simulation time 11973582 ps
CPU time 0.59 seconds
Started Jun 13 01:03:42 PM PDT 24
Finished Jun 13 01:03:43 PM PDT 24
Peak memory 194532 kb
Host smart-43b029c6-39bd-43aa-bbe9-3db8a6208a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639668155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.639668155
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.2621224825
Short name T630
Test name
Test status
Simulation time 389358416 ps
CPU time 1.7 seconds
Started Jun 13 01:03:52 PM PDT 24
Finished Jun 13 01:03:54 PM PDT 24
Peak memory 199392 kb
Host smart-57095970-4441-43d3-a4d3-99a5eea284e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621224825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.2621224825
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.2854911474
Short name T636
Test name
Test status
Simulation time 164876232 ps
CPU time 1.75 seconds
Started Jun 13 01:03:40 PM PDT 24
Finished Jun 13 01:03:42 PM PDT 24
Peak memory 199700 kb
Host smart-3e2e0b45-905f-4bf9-bde7-8304b5805d7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854911474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.2854911474
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.825104772
Short name T40
Test name
Test status
Simulation time 204302376 ps
CPU time 3.3 seconds
Started Jun 13 01:03:41 PM PDT 24
Finished Jun 13 01:03:45 PM PDT 24
Peak memory 199744 kb
Host smart-8ac6127d-d4dd-4eda-88a7-96c2230f42bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825104772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.825104772
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3582534226
Short name T684
Test name
Test status
Simulation time 111103149 ps
CPU time 1.61 seconds
Started Jun 13 01:03:48 PM PDT 24
Finished Jun 13 01:03:51 PM PDT 24
Peak memory 199676 kb
Host smart-e2ec6ae2-9432-4039-8d32-8208ca0648da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582534226 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3582534226
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.490462529
Short name T708
Test name
Test status
Simulation time 55801724 ps
CPU time 0.71 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:51 PM PDT 24
Peak memory 197644 kb
Host smart-d52597b7-8fe1-4f16-9855-37d81d709a4a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490462529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.490462529
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3280215899
Short name T662
Test name
Test status
Simulation time 22167115 ps
CPU time 0.55 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:51 PM PDT 24
Peak memory 194556 kb
Host smart-4f668e13-be09-4eca-8f15-92a0c965c298
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280215899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3280215899
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.751510679
Short name T597
Test name
Test status
Simulation time 78901983 ps
CPU time 1.09 seconds
Started Jun 13 01:03:50 PM PDT 24
Finished Jun 13 01:03:52 PM PDT 24
Peak memory 199300 kb
Host smart-8cf2ba91-77d0-4298-8983-48d932e3a776
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751510679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_csr
_outstanding.751510679
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1881738152
Short name T598
Test name
Test status
Simulation time 279493787 ps
CPU time 2.59 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 199804 kb
Host smart-588ebe13-56ff-48ef-bb11-0f629ef4ecaf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881738152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1881738152
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.431662747
Short name T110
Test name
Test status
Simulation time 359672465 ps
CPU time 3.21 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 199648 kb
Host smart-0762df3d-bdfa-445f-b6b2-48caf9d3055c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431662747 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.431662747
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3876073171
Short name T604
Test name
Test status
Simulation time 237513935705 ps
CPU time 597.63 seconds
Started Jun 13 01:03:48 PM PDT 24
Finished Jun 13 01:13:46 PM PDT 24
Peak memory 224412 kb
Host smart-02112dd5-85ab-4539-b3cd-1739e57e2371
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876073171 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3876073171
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.771571415
Short name T78
Test name
Test status
Simulation time 29107684 ps
CPU time 0.83 seconds
Started Jun 13 01:03:50 PM PDT 24
Finished Jun 13 01:03:52 PM PDT 24
Peak memory 199444 kb
Host smart-e51bc68e-42d9-4651-88d7-06ac15e21f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771571415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.771571415
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3752083320
Short name T601
Test name
Test status
Simulation time 13401074 ps
CPU time 0.57 seconds
Started Jun 13 01:03:50 PM PDT 24
Finished Jun 13 01:03:52 PM PDT 24
Peak memory 194568 kb
Host smart-acf6de94-5d3f-4e47-a411-c3573296192c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752083320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3752083320
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.2899779488
Short name T716
Test name
Test status
Simulation time 45352434 ps
CPU time 2.18 seconds
Started Jun 13 01:03:52 PM PDT 24
Finished Jun 13 01:03:55 PM PDT 24
Peak memory 199676 kb
Host smart-6435a028-b668-4446-a9f5-6360fd716fc8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899779488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.2899779488
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.147471763
Short name T633
Test name
Test status
Simulation time 993385108 ps
CPU time 3.39 seconds
Started Jun 13 01:03:53 PM PDT 24
Finished Jun 13 01:03:57 PM PDT 24
Peak memory 199228 kb
Host smart-804afb9b-38c5-45f4-8554-8041e1da7736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147471763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.147471763
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.1355082065
Short name T681
Test name
Test status
Simulation time 406116031 ps
CPU time 1.89 seconds
Started Jun 13 01:03:50 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 199736 kb
Host smart-10db0b20-96fe-44f8-8cc2-0d85ff9bc091
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355082065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.1355082065
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.3222764612
Short name T48
Test name
Test status
Simulation time 489035715 ps
CPU time 2.53 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 199756 kb
Host smart-bb9fc9e2-d2e2-4bae-9030-7cc1c7dfef0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222764612 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.3222764612
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.3576902823
Short name T654
Test name
Test status
Simulation time 98999415 ps
CPU time 0.95 seconds
Started Jun 13 01:03:50 PM PDT 24
Finished Jun 13 01:03:52 PM PDT 24
Peak memory 199380 kb
Host smart-3e6a7473-0320-4e77-a863-43a47d04cb6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576902823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.3576902823
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.2736049177
Short name T725
Test name
Test status
Simulation time 115346060 ps
CPU time 0.61 seconds
Started Jun 13 01:03:51 PM PDT 24
Finished Jun 13 01:03:52 PM PDT 24
Peak memory 194524 kb
Host smart-ce87da86-bd92-41ea-8082-5134242b779d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736049177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.2736049177
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.4018399912
Short name T605
Test name
Test status
Simulation time 48014283 ps
CPU time 1.14 seconds
Started Jun 13 01:03:51 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 199588 kb
Host smart-140720ea-8eea-4b14-8fec-a74bc83da68e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018399912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.4018399912
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.767329499
Short name T628
Test name
Test status
Simulation time 74462806 ps
CPU time 3.53 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:54 PM PDT 24
Peak memory 199588 kb
Host smart-8e96dd13-d9be-44b6-b45e-db305878e3db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767329499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.767329499
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.2538479226
Short name T665
Test name
Test status
Simulation time 75083052 ps
CPU time 1.81 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:52 PM PDT 24
Peak memory 199700 kb
Host smart-b547809a-f242-4245-97bd-d142fdd12cf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538479226 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.2538479226
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3739646214
Short name T76
Test name
Test status
Simulation time 183005084 ps
CPU time 0.72 seconds
Started Jun 13 01:03:51 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 197800 kb
Host smart-baad452c-bc8f-4e6d-ad7b-b315791afadf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739646214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3739646214
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.2571712837
Short name T653
Test name
Test status
Simulation time 13698774 ps
CPU time 0.58 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:51 PM PDT 24
Peak memory 194796 kb
Host smart-84aef041-4032-4f3e-b2d0-8bd60cb17ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571712837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.2571712837
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.4294778836
Short name T635
Test name
Test status
Simulation time 105017560 ps
CPU time 2.17 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 199736 kb
Host smart-0b2407cf-2cfc-4820-9125-67919761cc59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294778836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.4294778836
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.3280740955
Short name T666
Test name
Test status
Simulation time 321388844 ps
CPU time 4.57 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:55 PM PDT 24
Peak memory 199684 kb
Host smart-5ec78769-9b6b-43ee-b3be-c5a1feb5d14b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280740955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.3280740955
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2101615387
Short name T108
Test name
Test status
Simulation time 2219942074 ps
CPU time 3.9 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:54 PM PDT 24
Peak memory 199764 kb
Host smart-e56791f9-c038-421a-bceb-0a8e1b7e57a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101615387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2101615387
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1192637241
Short name T650
Test name
Test status
Simulation time 206090245 ps
CPU time 5.15 seconds
Started Jun 13 01:03:15 PM PDT 24
Finished Jun 13 01:03:21 PM PDT 24
Peak memory 199744 kb
Host smart-335911b0-4f11-4877-b161-e5d11e231bd8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192637241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1192637241
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.2134331637
Short name T83
Test name
Test status
Simulation time 3280512041 ps
CPU time 17.86 seconds
Started Jun 13 01:03:14 PM PDT 24
Finished Jun 13 01:03:32 PM PDT 24
Peak memory 199704 kb
Host smart-ba4f23bb-8a83-4d9e-833a-137380c5ecbb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134331637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.2134331637
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.3984083110
Short name T661
Test name
Test status
Simulation time 105319941 ps
CPU time 0.73 seconds
Started Jun 13 01:03:07 PM PDT 24
Finished Jun 13 01:03:09 PM PDT 24
Peak memory 197528 kb
Host smart-c515c7b2-4d5e-4af6-b3b4-0891f2fbe966
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984083110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.3984083110
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.761836349
Short name T640
Test name
Test status
Simulation time 74106043 ps
CPU time 1.86 seconds
Started Jun 13 01:03:15 PM PDT 24
Finished Jun 13 01:03:18 PM PDT 24
Peak memory 199728 kb
Host smart-279b244a-6003-46ce-8841-219a118a917b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761836349 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.761836349
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1829178344
Short name T602
Test name
Test status
Simulation time 24905881 ps
CPU time 0.82 seconds
Started Jun 13 01:03:15 PM PDT 24
Finished Jun 13 01:03:17 PM PDT 24
Peak memory 199224 kb
Host smart-81916622-eb65-42be-a42a-8d7491382474
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829178344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1829178344
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1004926253
Short name T626
Test name
Test status
Simulation time 14456968 ps
CPU time 0.61 seconds
Started Jun 13 01:03:08 PM PDT 24
Finished Jun 13 01:03:09 PM PDT 24
Peak memory 194392 kb
Host smart-b81facff-7560-4c5d-a08e-f9d62034c668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004926253 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1004926253
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2198543810
Short name T723
Test name
Test status
Simulation time 46200147 ps
CPU time 2 seconds
Started Jun 13 01:03:16 PM PDT 24
Finished Jun 13 01:03:19 PM PDT 24
Peak memory 199580 kb
Host smart-c96cc0fa-d8b6-4d22-a1c9-db2ea2965516
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198543810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2198543810
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2496537377
Short name T606
Test name
Test status
Simulation time 299189417 ps
CPU time 1.78 seconds
Started Jun 13 01:03:08 PM PDT 24
Finished Jun 13 01:03:10 PM PDT 24
Peak memory 199992 kb
Host smart-d556c36f-96e3-47db-a8c7-3a5e03a6e115
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496537377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2496537377
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.3013546540
Short name T664
Test name
Test status
Simulation time 150618571 ps
CPU time 1.75 seconds
Started Jun 13 01:03:08 PM PDT 24
Finished Jun 13 01:03:11 PM PDT 24
Peak memory 199620 kb
Host smart-6178071f-c15c-44b3-8b44-78746a1d1a91
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013546540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.3013546540
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1346056863
Short name T616
Test name
Test status
Simulation time 14232290 ps
CPU time 0.58 seconds
Started Jun 13 01:03:53 PM PDT 24
Finished Jun 13 01:03:54 PM PDT 24
Peak memory 194168 kb
Host smart-c212c2c6-4dbc-42e1-b2c7-64af5a395852
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346056863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1346056863
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3522371026
Short name T717
Test name
Test status
Simulation time 13813298 ps
CPU time 0.59 seconds
Started Jun 13 01:03:52 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 194476 kb
Host smart-8e526650-6cf6-4d7a-93e6-4af72e63c855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522371026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3522371026
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3933843465
Short name T698
Test name
Test status
Simulation time 11763782 ps
CPU time 0.6 seconds
Started Jun 13 01:03:53 PM PDT 24
Finished Jun 13 01:03:54 PM PDT 24
Peak memory 194520 kb
Host smart-8830b418-0d3a-439c-966a-309d6500ccec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933843465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3933843465
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.3779475359
Short name T629
Test name
Test status
Simulation time 15729648 ps
CPU time 0.61 seconds
Started Jun 13 01:03:50 PM PDT 24
Finished Jun 13 01:03:52 PM PDT 24
Peak memory 194580 kb
Host smart-1cfbe428-823a-499b-bbca-a57a1883b27a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779475359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.3779475359
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.4240565129
Short name T721
Test name
Test status
Simulation time 15032960 ps
CPU time 0.59 seconds
Started Jun 13 01:03:52 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 194536 kb
Host smart-774343bb-0696-47b4-accf-e96418c2ea27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240565129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.4240565129
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3400964297
Short name T652
Test name
Test status
Simulation time 44989449 ps
CPU time 0.58 seconds
Started Jun 13 01:03:49 PM PDT 24
Finished Jun 13 01:03:51 PM PDT 24
Peak memory 194676 kb
Host smart-1cb4f0a3-b6cb-449b-bcdd-37c9c2634c46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400964297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3400964297
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3980503107
Short name T704
Test name
Test status
Simulation time 46359125 ps
CPU time 0.63 seconds
Started Jun 13 01:03:52 PM PDT 24
Finished Jun 13 01:03:53 PM PDT 24
Peak memory 194532 kb
Host smart-3cb2d78f-103d-4c9d-8460-a6c4287cbb06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980503107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3980503107
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.567817861
Short name T703
Test name
Test status
Simulation time 32097583 ps
CPU time 0.59 seconds
Started Jun 13 01:03:59 PM PDT 24
Finished Jun 13 01:04:01 PM PDT 24
Peak memory 194612 kb
Host smart-07406d98-c65d-47fe-b9d8-a6b6cbc178b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567817861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.567817861
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.880807314
Short name T667
Test name
Test status
Simulation time 114292169 ps
CPU time 0.58 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:03:59 PM PDT 24
Peak memory 194572 kb
Host smart-b4318cd0-5baa-4de4-b516-d3816a49b70d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880807314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.880807314
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2115899768
Short name T592
Test name
Test status
Simulation time 13625470 ps
CPU time 0.6 seconds
Started Jun 13 01:03:56 PM PDT 24
Finished Jun 13 01:03:57 PM PDT 24
Peak memory 194484 kb
Host smart-e4224625-a074-4662-9912-de98a53c0b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115899768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2115899768
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.2150100761
Short name T719
Test name
Test status
Simulation time 192622674 ps
CPU time 3.37 seconds
Started Jun 13 01:03:15 PM PDT 24
Finished Jun 13 01:03:19 PM PDT 24
Peak memory 199652 kb
Host smart-f993a4f3-ea01-4619-999e-9baf34c9f53d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150100761 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.2150100761
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.1846370326
Short name T674
Test name
Test status
Simulation time 218496135 ps
CPU time 10.03 seconds
Started Jun 13 01:03:14 PM PDT 24
Finished Jun 13 01:03:25 PM PDT 24
Peak memory 199656 kb
Host smart-c0a43a2c-137f-4a79-9b4e-a9a87389c00d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846370326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.1846370326
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.3581314996
Short name T625
Test name
Test status
Simulation time 18087870 ps
CPU time 0.85 seconds
Started Jun 13 01:03:16 PM PDT 24
Finished Jun 13 01:03:18 PM PDT 24
Peak memory 199396 kb
Host smart-a2434b82-4591-4926-beab-b4dda4b6fc5c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581314996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.3581314996
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.4210118592
Short name T724
Test name
Test status
Simulation time 40026459 ps
CPU time 1.26 seconds
Started Jun 13 01:03:16 PM PDT 24
Finished Jun 13 01:03:19 PM PDT 24
Peak memory 199608 kb
Host smart-c248c256-811a-467a-9ee0-d4f1531694d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210118592 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.4210118592
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.9381567
Short name T643
Test name
Test status
Simulation time 18457508 ps
CPU time 0.93 seconds
Started Jun 13 01:03:15 PM PDT 24
Finished Jun 13 01:03:17 PM PDT 24
Peak memory 199572 kb
Host smart-f3bff0da-c5d6-49ad-b40d-b448cc2fdac7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9381567 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.9381567
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2222578035
Short name T692
Test name
Test status
Simulation time 18804076 ps
CPU time 0.61 seconds
Started Jun 13 01:03:16 PM PDT 24
Finished Jun 13 01:03:17 PM PDT 24
Peak memory 194576 kb
Host smart-1d584881-2b4b-4656-ad1d-bb4b4bf6e994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222578035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2222578035
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.838122516
Short name T647
Test name
Test status
Simulation time 93160745 ps
CPU time 1.72 seconds
Started Jun 13 01:03:15 PM PDT 24
Finished Jun 13 01:03:18 PM PDT 24
Peak memory 199692 kb
Host smart-d9a3e367-b023-4935-8e45-13a25e53feb4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838122516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr_
outstanding.838122516
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4209948293
Short name T712
Test name
Test status
Simulation time 139646490 ps
CPU time 1.82 seconds
Started Jun 13 01:03:14 PM PDT 24
Finished Jun 13 01:03:16 PM PDT 24
Peak memory 199736 kb
Host smart-03299bac-2203-46d1-a769-764ad776428a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209948293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4209948293
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.149728117
Short name T102
Test name
Test status
Simulation time 121589858 ps
CPU time 3.96 seconds
Started Jun 13 01:03:14 PM PDT 24
Finished Jun 13 01:03:18 PM PDT 24
Peak memory 199600 kb
Host smart-6f0d2f7d-871b-4c8d-a9dd-712dd1be3d6a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149728117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.149728117
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2808325635
Short name T699
Test name
Test status
Simulation time 14438145 ps
CPU time 0.6 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 194508 kb
Host smart-d53e057c-77ef-4553-ac3c-e5afdbb6486a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808325635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2808325635
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.1111272114
Short name T658
Test name
Test status
Simulation time 12475574 ps
CPU time 0.6 seconds
Started Jun 13 01:03:56 PM PDT 24
Finished Jun 13 01:03:57 PM PDT 24
Peak memory 194644 kb
Host smart-194d162d-22e7-45a3-8b3a-65a1fa67e35c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111272114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.1111272114
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.2179285058
Short name T648
Test name
Test status
Simulation time 25049430 ps
CPU time 0.67 seconds
Started Jun 13 01:03:58 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 194596 kb
Host smart-f9e0570a-071d-413f-b697-c7a4ca4b9eb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179285058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.2179285058
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.55906041
Short name T608
Test name
Test status
Simulation time 12507122 ps
CPU time 0.6 seconds
Started Jun 13 01:03:54 PM PDT 24
Finished Jun 13 01:03:55 PM PDT 24
Peak memory 194608 kb
Host smart-df45aba8-a438-4205-b173-f247d47a8e4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55906041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.55906041
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1788281822
Short name T663
Test name
Test status
Simulation time 17183609 ps
CPU time 0.59 seconds
Started Jun 13 01:03:56 PM PDT 24
Finished Jun 13 01:03:57 PM PDT 24
Peak memory 194484 kb
Host smart-b45db5bc-48a7-4a52-85bb-3ab3c8249737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788281822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1788281822
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.1805192263
Short name T696
Test name
Test status
Simulation time 25106649 ps
CPU time 0.64 seconds
Started Jun 13 01:03:56 PM PDT 24
Finished Jun 13 01:03:59 PM PDT 24
Peak memory 194584 kb
Host smart-4b9a0e38-5c74-431c-a493-c4793755fadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805192263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.1805192263
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.1000196774
Short name T668
Test name
Test status
Simulation time 13284376 ps
CPU time 0.57 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 194548 kb
Host smart-10763643-065c-4787-9304-3ad621b9b15a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000196774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.1000196774
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.197390243
Short name T621
Test name
Test status
Simulation time 44164606 ps
CPU time 0.58 seconds
Started Jun 13 01:03:55 PM PDT 24
Finished Jun 13 01:03:56 PM PDT 24
Peak memory 194556 kb
Host smart-b13a6972-1cee-40e7-8be4-52d313399bf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197390243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.197390243
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.3464756975
Short name T631
Test name
Test status
Simulation time 12809948 ps
CPU time 0.59 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 194532 kb
Host smart-d3ea41dd-cf64-48a9-9f29-b4f559903c53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464756975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.3464756975
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.663662
Short name T599
Test name
Test status
Simulation time 41346350 ps
CPU time 0.59 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 194480 kb
Host smart-60b86867-048b-4e48-8a73-b1795922b6ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.663662
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2246679975
Short name T720
Test name
Test status
Simulation time 447162934 ps
CPU time 8.29 seconds
Started Jun 13 01:03:23 PM PDT 24
Finished Jun 13 01:03:34 PM PDT 24
Peak memory 199472 kb
Host smart-7a80c822-b76f-42e0-ba92-6d040230650b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246679975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2246679975
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3333543586
Short name T80
Test name
Test status
Simulation time 1097249896 ps
CPU time 11.13 seconds
Started Jun 13 01:03:21 PM PDT 24
Finished Jun 13 01:03:33 PM PDT 24
Peak memory 199640 kb
Host smart-23dc7fad-b1e2-406d-b803-c65c203d93f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333543586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3333543586
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2315457837
Short name T659
Test name
Test status
Simulation time 274703612 ps
CPU time 0.86 seconds
Started Jun 13 01:03:21 PM PDT 24
Finished Jun 13 01:03:23 PM PDT 24
Peak memory 199376 kb
Host smart-516df088-c454-4cc3-a7fc-f87ec23de4ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315457837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2315457837
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.3978085643
Short name T671
Test name
Test status
Simulation time 646846436326 ps
CPU time 782.92 seconds
Started Jun 13 01:03:20 PM PDT 24
Finished Jun 13 01:16:23 PM PDT 24
Peak memory 216300 kb
Host smart-8d6ab751-4591-4596-89f8-877f9a7a4eda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978085643 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.3978085643
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2571679442
Short name T682
Test name
Test status
Simulation time 123255739 ps
CPU time 0.91 seconds
Started Jun 13 01:03:22 PM PDT 24
Finished Jun 13 01:03:25 PM PDT 24
Peak memory 199120 kb
Host smart-80a80d4e-9703-49ba-bd9a-9268b6f30589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571679442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2571679442
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1887857916
Short name T610
Test name
Test status
Simulation time 184788046 ps
CPU time 0.57 seconds
Started Jun 13 01:03:26 PM PDT 24
Finished Jun 13 01:03:28 PM PDT 24
Peak memory 194588 kb
Host smart-2bd29e62-f6f9-408e-9b59-16b34717953d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887857916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1887857916
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.2287013861
Short name T595
Test name
Test status
Simulation time 24332638 ps
CPU time 1.09 seconds
Started Jun 13 01:03:20 PM PDT 24
Finished Jun 13 01:03:22 PM PDT 24
Peak memory 198284 kb
Host smart-2f6f2895-8686-4a44-814a-3fc00e44c018
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287013861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.2287013861
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.2518360381
Short name T710
Test name
Test status
Simulation time 40408529 ps
CPU time 2.14 seconds
Started Jun 13 01:03:14 PM PDT 24
Finished Jun 13 01:03:17 PM PDT 24
Peak memory 199744 kb
Host smart-70cead82-377d-4788-a7b8-0397c4da0112
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518360381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.2518360381
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2154720238
Short name T107
Test name
Test status
Simulation time 464121294 ps
CPU time 4.2 seconds
Started Jun 13 01:03:20 PM PDT 24
Finished Jun 13 01:03:25 PM PDT 24
Peak memory 199696 kb
Host smart-7ad2bb67-c5d1-4353-b802-5cfe434aff93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154720238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2154720238
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.3129105063
Short name T646
Test name
Test status
Simulation time 44808651 ps
CPU time 0.58 seconds
Started Jun 13 01:03:55 PM PDT 24
Finished Jun 13 01:03:56 PM PDT 24
Peak memory 194596 kb
Host smart-9f0b68b7-2548-4b44-b7ce-04f64631aa04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129105063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.3129105063
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.851621479
Short name T679
Test name
Test status
Simulation time 13047566 ps
CPU time 0.56 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:03:59 PM PDT 24
Peak memory 194432 kb
Host smart-99b0566e-7462-41a6-9741-f4bc9be13205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851621479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.851621479
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1980247819
Short name T634
Test name
Test status
Simulation time 72697406 ps
CPU time 0.67 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 194532 kb
Host smart-b541cb04-bd55-4e37-9395-82f0b3d8102f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980247819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1980247819
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.3987503850
Short name T624
Test name
Test status
Simulation time 60344807 ps
CPU time 0.6 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:03:59 PM PDT 24
Peak memory 194556 kb
Host smart-f4344ff3-32a5-4365-ae47-2d3d23639f45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987503850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.3987503850
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2105771389
Short name T644
Test name
Test status
Simulation time 14390085 ps
CPU time 0.62 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:03:59 PM PDT 24
Peak memory 194620 kb
Host smart-0f97766a-e2a2-46c0-9054-c5ba794aae6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105771389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2105771389
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.3173124056
Short name T596
Test name
Test status
Simulation time 48365205 ps
CPU time 0.62 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 194600 kb
Host smart-3b3e3ab0-1eea-40fc-a67a-7c40df3b4aa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173124056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.3173124056
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.648543249
Short name T727
Test name
Test status
Simulation time 13739486 ps
CPU time 0.6 seconds
Started Jun 13 01:03:58 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 194540 kb
Host smart-934bfafe-9bdc-4cae-b8b0-ab5eaaafa6e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648543249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.648543249
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.1894786584
Short name T642
Test name
Test status
Simulation time 30129429 ps
CPU time 0.66 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:03:59 PM PDT 24
Peak memory 194592 kb
Host smart-28026dfe-45a3-48d4-98b8-79ac57411d64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894786584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.1894786584
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2306580349
Short name T627
Test name
Test status
Simulation time 30746007 ps
CPU time 0.6 seconds
Started Jun 13 01:03:56 PM PDT 24
Finished Jun 13 01:03:59 PM PDT 24
Peak memory 194552 kb
Host smart-0e7c2406-6404-41ce-b654-f9c62a0e18b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306580349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2306580349
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3061625999
Short name T683
Test name
Test status
Simulation time 65294063 ps
CPU time 0.63 seconds
Started Jun 13 01:03:57 PM PDT 24
Finished Jun 13 01:04:00 PM PDT 24
Peak memory 194620 kb
Host smart-19becc39-52cf-4865-a39f-fe2c32077a56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061625999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3061625999
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.3475191559
Short name T675
Test name
Test status
Simulation time 126602778 ps
CPU time 1.85 seconds
Started Jun 13 01:03:21 PM PDT 24
Finished Jun 13 01:03:23 PM PDT 24
Peak memory 199776 kb
Host smart-2223c1c3-b8ac-4399-b0b8-82f3b9f1b58f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475191559 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.3475191559
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1799171661
Short name T75
Test name
Test status
Simulation time 29568601 ps
CPU time 0.88 seconds
Started Jun 13 01:03:24 PM PDT 24
Finished Jun 13 01:03:27 PM PDT 24
Peak memory 199516 kb
Host smart-808fa0a7-ca49-422d-b5b4-4d2e8ab41511
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799171661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1799171661
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.3366082530
Short name T706
Test name
Test status
Simulation time 12264583 ps
CPU time 0.56 seconds
Started Jun 13 01:03:21 PM PDT 24
Finished Jun 13 01:03:23 PM PDT 24
Peak memory 194576 kb
Host smart-a02aba6c-e185-4fa3-88b2-ef5984a2ecd8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366082530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.3366082530
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.1459078672
Short name T619
Test name
Test status
Simulation time 184907533 ps
CPU time 2.06 seconds
Started Jun 13 01:03:22 PM PDT 24
Finished Jun 13 01:03:27 PM PDT 24
Peak memory 199108 kb
Host smart-05bb9c34-531d-48b3-a8fd-93521f2f1da2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459078672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.1459078672
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.4126750502
Short name T615
Test name
Test status
Simulation time 63641944 ps
CPU time 1.48 seconds
Started Jun 13 01:03:22 PM PDT 24
Finished Jun 13 01:03:24 PM PDT 24
Peak memory 199720 kb
Host smart-458be4c3-dd51-44e9-a815-138bc6dffb80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126750502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.4126750502
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.2139480176
Short name T103
Test name
Test status
Simulation time 273128115 ps
CPU time 4.61 seconds
Started Jun 13 01:03:22 PM PDT 24
Finished Jun 13 01:03:29 PM PDT 24
Peak memory 199652 kb
Host smart-2db62e4f-6903-488e-ba3e-9ff62e940f3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139480176 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.2139480176
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.2412207737
Short name T726
Test name
Test status
Simulation time 46460409 ps
CPU time 1.41 seconds
Started Jun 13 01:03:22 PM PDT 24
Finished Jun 13 01:03:26 PM PDT 24
Peak memory 199700 kb
Host smart-aca295ff-a382-428e-96d9-881cd4a5892e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412207737 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.2412207737
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.2111567348
Short name T609
Test name
Test status
Simulation time 23188328 ps
CPU time 0.81 seconds
Started Jun 13 01:03:21 PM PDT 24
Finished Jun 13 01:03:23 PM PDT 24
Peak memory 199144 kb
Host smart-eade1d9a-85d9-401b-9191-98c53d23cbe8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111567348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.2111567348
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.3565946821
Short name T622
Test name
Test status
Simulation time 46543142 ps
CPU time 0.61 seconds
Started Jun 13 01:03:21 PM PDT 24
Finished Jun 13 01:03:22 PM PDT 24
Peak memory 194524 kb
Host smart-eb561043-14c4-4f0c-9509-990a06ba4409
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565946821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.3565946821
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.3007393394
Short name T656
Test name
Test status
Simulation time 101748256 ps
CPU time 1.8 seconds
Started Jun 13 01:03:20 PM PDT 24
Finished Jun 13 01:03:22 PM PDT 24
Peak memory 199628 kb
Host smart-67847d6e-c5ea-4270-86c4-70fe027819e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007393394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.3007393394
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.2090010691
Short name T651
Test name
Test status
Simulation time 110941916 ps
CPU time 1.54 seconds
Started Jun 13 01:03:22 PM PDT 24
Finished Jun 13 01:03:26 PM PDT 24
Peak memory 199732 kb
Host smart-82a36197-6da8-4f5f-ad85-743f8754edb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090010691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.2090010691
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.747872159
Short name T109
Test name
Test status
Simulation time 84963666 ps
CPU time 1.8 seconds
Started Jun 13 01:03:25 PM PDT 24
Finished Jun 13 01:03:28 PM PDT 24
Peak memory 199712 kb
Host smart-3b99bb5f-d917-41f5-9535-10429f0d96c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747872159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.747872159
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.2021958872
Short name T611
Test name
Test status
Simulation time 220632447 ps
CPU time 1.2 seconds
Started Jun 13 01:03:28 PM PDT 24
Finished Jun 13 01:03:30 PM PDT 24
Peak memory 199560 kb
Host smart-c36767c8-a4d9-4dcb-9be9-b95b07bb7f12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021958872 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.2021958872
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3133864487
Short name T680
Test name
Test status
Simulation time 18680100 ps
CPU time 0.91 seconds
Started Jun 13 01:03:20 PM PDT 24
Finished Jun 13 01:03:21 PM PDT 24
Peak memory 199716 kb
Host smart-a9008c64-c5e7-49d7-9b7f-77bc230a8c96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133864487 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3133864487
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.2317825606
Short name T705
Test name
Test status
Simulation time 17416592 ps
CPU time 0.65 seconds
Started Jun 13 01:03:23 PM PDT 24
Finished Jun 13 01:03:26 PM PDT 24
Peak memory 194544 kb
Host smart-0f53f3ce-9098-4685-996c-803668ed8ad6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317825606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.2317825606
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.2000373729
Short name T47
Test name
Test status
Simulation time 209180395 ps
CPU time 2.16 seconds
Started Jun 13 01:03:21 PM PDT 24
Finished Jun 13 01:03:24 PM PDT 24
Peak memory 199664 kb
Host smart-6745dfbe-9f69-4ac3-bd94-7b4a89eab07d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000373729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.2000373729
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.464879099
Short name T623
Test name
Test status
Simulation time 90586603 ps
CPU time 3.83 seconds
Started Jun 13 01:03:21 PM PDT 24
Finished Jun 13 01:03:25 PM PDT 24
Peak memory 199720 kb
Host smart-e1aa00bd-abfa-45e0-b740-fd361e03369b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464879099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.464879099
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.3774248142
Short name T711
Test name
Test status
Simulation time 459340870 ps
CPU time 3.97 seconds
Started Jun 13 01:03:21 PM PDT 24
Finished Jun 13 01:03:26 PM PDT 24
Peak memory 199716 kb
Host smart-493f48ee-a066-4580-a1b0-bad5f3ddc3cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774248142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.3774248142
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2825584403
Short name T639
Test name
Test status
Simulation time 254766984 ps
CPU time 1.75 seconds
Started Jun 13 01:03:31 PM PDT 24
Finished Jun 13 01:03:34 PM PDT 24
Peak memory 199740 kb
Host smart-d1c7b0d7-0d48-4d75-aeef-0a358a470654
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825584403 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2825584403
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2327004324
Short name T603
Test name
Test status
Simulation time 113284185 ps
CPU time 0.67 seconds
Started Jun 13 01:03:28 PM PDT 24
Finished Jun 13 01:03:29 PM PDT 24
Peak memory 197116 kb
Host smart-744564f3-8a81-40c7-9586-e004ce90b617
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327004324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2327004324
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3593360228
Short name T614
Test name
Test status
Simulation time 13373802 ps
CPU time 0.64 seconds
Started Jun 13 01:03:28 PM PDT 24
Finished Jun 13 01:03:29 PM PDT 24
Peak memory 194496 kb
Host smart-affefb9e-15ab-45c9-8c8e-52122d1c5389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593360228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3593360228
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.3033891842
Short name T678
Test name
Test status
Simulation time 89862910 ps
CPU time 1.12 seconds
Started Jun 13 01:03:28 PM PDT 24
Finished Jun 13 01:03:30 PM PDT 24
Peak memory 199564 kb
Host smart-24a34016-d24d-4a4c-be59-eafedcb2223c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033891842 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.3033891842
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.1376344319
Short name T691
Test name
Test status
Simulation time 61775553 ps
CPU time 1.48 seconds
Started Jun 13 01:03:29 PM PDT 24
Finished Jun 13 01:03:31 PM PDT 24
Peak memory 199704 kb
Host smart-910e1ab3-d660-4d42-b40b-348f70a8b043
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376344319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.1376344319
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.1541038425
Short name T676
Test name
Test status
Simulation time 287309050 ps
CPU time 1.8 seconds
Started Jun 13 01:03:29 PM PDT 24
Finished Jun 13 01:03:32 PM PDT 24
Peak memory 199744 kb
Host smart-502e1e3b-f55d-41b5-871d-6936db1c413b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541038425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.1541038425
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.1546154455
Short name T637
Test name
Test status
Simulation time 67446054 ps
CPU time 1.09 seconds
Started Jun 13 01:03:28 PM PDT 24
Finished Jun 13 01:03:30 PM PDT 24
Peak memory 199544 kb
Host smart-854b8c47-a03d-4375-a315-942a49aa582f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546154455 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.1546154455
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.2733819207
Short name T673
Test name
Test status
Simulation time 37587312 ps
CPU time 0.98 seconds
Started Jun 13 01:03:27 PM PDT 24
Finished Jun 13 01:03:29 PM PDT 24
Peak memory 198972 kb
Host smart-3599818f-3375-4537-8656-bcb2cd7cf057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733819207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.2733819207
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2910944759
Short name T593
Test name
Test status
Simulation time 24086078 ps
CPU time 0.59 seconds
Started Jun 13 01:03:29 PM PDT 24
Finished Jun 13 01:03:30 PM PDT 24
Peak memory 194456 kb
Host smart-61453bf5-b172-47ec-88ba-64dc45a3fa4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910944759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2910944759
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.4187587123
Short name T655
Test name
Test status
Simulation time 115589674 ps
CPU time 2 seconds
Started Jun 13 01:03:30 PM PDT 24
Finished Jun 13 01:03:32 PM PDT 24
Peak memory 199704 kb
Host smart-cf6966fd-2a39-414e-b7b8-51b7bb798116
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187587123 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.4187587123
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.2704414696
Short name T702
Test name
Test status
Simulation time 900825329 ps
CPU time 4.26 seconds
Started Jun 13 01:03:27 PM PDT 24
Finished Jun 13 01:03:32 PM PDT 24
Peak memory 199696 kb
Host smart-6c3ff289-3990-4eb9-8413-73bed2ea48af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704414696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.2704414696
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.3133606002
Short name T694
Test name
Test status
Simulation time 568650454 ps
CPU time 1.86 seconds
Started Jun 13 01:03:27 PM PDT 24
Finished Jun 13 01:03:30 PM PDT 24
Peak memory 199704 kb
Host smart-46787924-e1b3-4096-b527-07a5d512b4c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133606002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.3133606002
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.2435294415
Short name T574
Test name
Test status
Simulation time 13903778 ps
CPU time 0.59 seconds
Started Jun 13 01:09:27 PM PDT 24
Finished Jun 13 01:09:28 PM PDT 24
Peak memory 194840 kb
Host smart-b1880327-41c1-43d2-8bb5-2a51edb9d763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435294415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.2435294415
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.2849336716
Short name T6
Test name
Test status
Simulation time 1913474865 ps
CPU time 39.57 seconds
Started Jun 13 01:09:23 PM PDT 24
Finished Jun 13 01:10:04 PM PDT 24
Peak memory 216152 kb
Host smart-827fc18f-7e2f-4490-a6e0-c431b7ec4dac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2849336716 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.2849336716
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.3056980932
Short name T181
Test name
Test status
Simulation time 9287175070 ps
CPU time 48.28 seconds
Started Jun 13 01:09:32 PM PDT 24
Finished Jun 13 01:10:22 PM PDT 24
Peak memory 199828 kb
Host smart-b135d55f-05bc-42c4-a9a6-57e9aa355ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056980932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.3056980932
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2676119721
Short name T72
Test name
Test status
Simulation time 506546669 ps
CPU time 122.07 seconds
Started Jun 13 01:09:26 PM PDT 24
Finished Jun 13 01:11:29 PM PDT 24
Peak memory 616840 kb
Host smart-e17f8923-8725-4e7a-9a43-c335d2d4b57a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2676119721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2676119721
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.1729256674
Short name T316
Test name
Test status
Simulation time 8975766315 ps
CPU time 162.88 seconds
Started Jun 13 01:09:24 PM PDT 24
Finished Jun 13 01:12:09 PM PDT 24
Peak memory 199844 kb
Host smart-767dba05-a681-4050-abd8-c20fea816537
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729256674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.1729256674
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.618439375
Short name T395
Test name
Test status
Simulation time 1203695478 ps
CPU time 34.02 seconds
Started Jun 13 01:09:21 PM PDT 24
Finished Jun 13 01:09:56 PM PDT 24
Peak memory 199824 kb
Host smart-8fec6a2f-3be8-40e7-ac1b-d86e7b336c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618439375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.618439375
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.242737451
Short name T29
Test name
Test status
Simulation time 181733337 ps
CPU time 0.98 seconds
Started Jun 13 01:09:27 PM PDT 24
Finished Jun 13 01:09:29 PM PDT 24
Peak memory 218372 kb
Host smart-2c26ec7f-aca5-4e23-b914-b87a8172316e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242737451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.242737451
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.1033282723
Short name T362
Test name
Test status
Simulation time 155920854 ps
CPU time 5.33 seconds
Started Jun 13 01:09:24 PM PDT 24
Finished Jun 13 01:09:31 PM PDT 24
Peak memory 199852 kb
Host smart-4ad9236e-d381-4a1a-a216-fb84621b80b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033282723 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.1033282723
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.3845670495
Short name T325
Test name
Test status
Simulation time 58616684 ps
CPU time 1.07 seconds
Started Jun 13 01:09:25 PM PDT 24
Finished Jun 13 01:09:27 PM PDT 24
Peak memory 199596 kb
Host smart-f1eeb24a-5343-47e0-957d-955c4c51b4f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845670495 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.hmac_test_hmac_vectors.3845670495
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha_vectors.3813650321
Short name T549
Test name
Test status
Simulation time 7842288098 ps
CPU time 439.88 seconds
Started Jun 13 01:09:24 PM PDT 24
Finished Jun 13 01:16:46 PM PDT 24
Peak memory 199904 kb
Host smart-f746a36d-5e5f-4f5e-a369-d31f14b4c2bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813650321 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha_vectors.3813650321
Directory /workspace/0.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.2625217340
Short name T162
Test name
Test status
Simulation time 553839933 ps
CPU time 9.7 seconds
Started Jun 13 01:09:20 PM PDT 24
Finished Jun 13 01:09:31 PM PDT 24
Peak memory 199776 kb
Host smart-f3a21e61-6d53-4539-b3de-b16125f34f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625217340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.2625217340
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.807961515
Short name T569
Test name
Test status
Simulation time 6699974333 ps
CPU time 48.53 seconds
Started Jun 13 01:09:27 PM PDT 24
Finished Jun 13 01:10:16 PM PDT 24
Peak memory 233696 kb
Host smart-86e0107a-dc6d-47a7-8016-9d10d5a378f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=807961515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.807961515
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.2185828881
Short name T443
Test name
Test status
Simulation time 547160137 ps
CPU time 27.53 seconds
Started Jun 13 01:09:27 PM PDT 24
Finished Jun 13 01:09:55 PM PDT 24
Peak memory 199748 kb
Host smart-8c7b7bc1-6976-4754-b0ee-ff993866de93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185828881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.2185828881
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1921088690
Short name T255
Test name
Test status
Simulation time 11044984013 ps
CPU time 535.17 seconds
Started Jun 13 01:09:21 PM PDT 24
Finished Jun 13 01:18:18 PM PDT 24
Peak memory 685476 kb
Host smart-762f7329-e095-4793-8046-64516e740099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1921088690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1921088690
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3636278311
Short name T128
Test name
Test status
Simulation time 1032934738 ps
CPU time 10.18 seconds
Started Jun 13 01:09:24 PM PDT 24
Finished Jun 13 01:09:36 PM PDT 24
Peak memory 199816 kb
Host smart-05d95149-9c44-4052-9f76-961462767ce9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636278311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3636278311
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.3393006806
Short name T351
Test name
Test status
Simulation time 7431876615 ps
CPU time 97.68 seconds
Started Jun 13 01:09:24 PM PDT 24
Finished Jun 13 01:11:02 PM PDT 24
Peak memory 199916 kb
Host smart-8be291ee-846c-4b22-8f8f-34d7af638d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393006806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.3393006806
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_smoke.3631864505
Short name T239
Test name
Test status
Simulation time 423649626 ps
CPU time 5.47 seconds
Started Jun 13 01:09:24 PM PDT 24
Finished Jun 13 01:09:31 PM PDT 24
Peak memory 199824 kb
Host smart-71a4acbd-0747-45ac-b951-dbd986396dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631864505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.3631864505
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_stress_all.999818866
Short name T409
Test name
Test status
Simulation time 1009213143208 ps
CPU time 2848.28 seconds
Started Jun 13 01:09:42 PM PDT 24
Finished Jun 13 01:57:12 PM PDT 24
Peak memory 778636 kb
Host smart-be998283-6a67-4cd0-839b-e7bf4e13caa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999818866 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.999818866
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/1.hmac_stress_all_with_rand_reset.3521036788
Short name T25
Test name
Test status
Simulation time 56199589586 ps
CPU time 1898.7 seconds
Started Jun 13 01:09:32 PM PDT 24
Finished Jun 13 01:41:12 PM PDT 24
Peak memory 726340 kb
Host smart-0f408fe4-8f58-445e-972e-40f13624c9e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3521036788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all_with_rand_reset.3521036788
Directory /workspace/1.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.3861464876
Short name T282
Test name
Test status
Simulation time 57364981 ps
CPU time 1.1 seconds
Started Jun 13 01:09:23 PM PDT 24
Finished Jun 13 01:09:25 PM PDT 24
Peak memory 199640 kb
Host smart-01482023-9946-4d95-8b2c-7fb7763c44a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861464876 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.hmac_test_hmac_vectors.3861464876
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha_vectors.1563581844
Short name T229
Test name
Test status
Simulation time 29002526369 ps
CPU time 503.7 seconds
Started Jun 13 01:09:23 PM PDT 24
Finished Jun 13 01:17:48 PM PDT 24
Peak memory 199848 kb
Host smart-386968c1-a65c-478d-b182-bb85e37550d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563581844 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha_vectors.1563581844
Directory /workspace/1.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1633272303
Short name T366
Test name
Test status
Simulation time 1184881107 ps
CPU time 57.88 seconds
Started Jun 13 01:09:24 PM PDT 24
Finished Jun 13 01:10:23 PM PDT 24
Peak memory 199780 kb
Host smart-e4011b10-b7ad-4a92-8cc9-c2e8eb0b62f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633272303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1633272303
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3171748973
Short name T330
Test name
Test status
Simulation time 41763492 ps
CPU time 0.59 seconds
Started Jun 13 01:09:39 PM PDT 24
Finished Jun 13 01:09:41 PM PDT 24
Peak memory 195772 kb
Host smart-6f3d77e4-f797-4f00-a91f-572bec0ee95b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171748973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3171748973
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.144274505
Short name T17
Test name
Test status
Simulation time 610714474 ps
CPU time 18.34 seconds
Started Jun 13 01:09:41 PM PDT 24
Finished Jun 13 01:10:00 PM PDT 24
Peak memory 208020 kb
Host smart-de013240-82b8-4132-b007-ed7ec4914e78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=144274505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.144274505
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.654871612
Short name T419
Test name
Test status
Simulation time 2672839872 ps
CPU time 46.83 seconds
Started Jun 13 01:09:42 PM PDT 24
Finished Jun 13 01:10:30 PM PDT 24
Peak memory 199784 kb
Host smart-5b0eb053-f080-469d-9eb6-63fe9628dc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654871612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.654871612
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.322895927
Short name T377
Test name
Test status
Simulation time 4338869253 ps
CPU time 289.92 seconds
Started Jun 13 01:09:46 PM PDT 24
Finished Jun 13 01:14:37 PM PDT 24
Peak memory 481596 kb
Host smart-0aabab63-1b39-4029-8e05-cc0787127f9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=322895927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.322895927
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1052772691
Short name T147
Test name
Test status
Simulation time 5053884577 ps
CPU time 93.05 seconds
Started Jun 13 01:09:45 PM PDT 24
Finished Jun 13 01:11:19 PM PDT 24
Peak memory 199888 kb
Host smart-1ec409af-721a-41a8-83b7-2177c928fae2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052772691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1052772691
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.2080703330
Short name T311
Test name
Test status
Simulation time 1598836072 ps
CPU time 48.44 seconds
Started Jun 13 01:09:40 PM PDT 24
Finished Jun 13 01:10:30 PM PDT 24
Peak memory 199780 kb
Host smart-c5894011-3d95-4fd4-9725-5efe92cf7e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080703330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.2080703330
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.343314343
Short name T429
Test name
Test status
Simulation time 351937609 ps
CPU time 5.77 seconds
Started Jun 13 01:09:42 PM PDT 24
Finished Jun 13 01:09:49 PM PDT 24
Peak memory 199780 kb
Host smart-73a540fc-4560-4278-8573-b005eb7c6e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343314343 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.343314343
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.1369971600
Short name T579
Test name
Test status
Simulation time 75229194292 ps
CPU time 2084.64 seconds
Started Jun 13 01:09:40 PM PDT 24
Finished Jun 13 01:44:27 PM PDT 24
Peak memory 837368 kb
Host smart-3280a3ae-eb40-4d85-9d70-b32471cf4949
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369971600 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.1369971600
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.3417589715
Short name T588
Test name
Test status
Simulation time 133705147 ps
CPU time 1.09 seconds
Started Jun 13 01:09:38 PM PDT 24
Finished Jun 13 01:09:41 PM PDT 24
Peak memory 199828 kb
Host smart-ca1cc163-ba60-49eb-beb4-c4f1ed1b448f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417589715 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.hmac_test_hmac_vectors.3417589715
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha_vectors.1435913519
Short name T233
Test name
Test status
Simulation time 75036695092 ps
CPU time 478.76 seconds
Started Jun 13 01:09:44 PM PDT 24
Finished Jun 13 01:17:43 PM PDT 24
Peak memory 199900 kb
Host smart-88f2122c-8f7d-4da4-87d3-e5ff583de7da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435913519 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha_vectors.1435913519
Directory /workspace/10.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.1020815574
Short name T520
Test name
Test status
Simulation time 1891642635 ps
CPU time 89.32 seconds
Started Jun 13 01:09:42 PM PDT 24
Finished Jun 13 01:11:12 PM PDT 24
Peak memory 199804 kb
Host smart-52c1fbda-1e04-4a35-b3d7-c9f7460d7e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020815574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.1020815574
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.1979302093
Short name T201
Test name
Test status
Simulation time 11630983 ps
CPU time 0.56 seconds
Started Jun 13 01:09:43 PM PDT 24
Finished Jun 13 01:09:44 PM PDT 24
Peak memory 194964 kb
Host smart-3715b7a8-fa69-480b-bb86-e1aa2a78ddba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979302093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.1979302093
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.2419943346
Short name T439
Test name
Test status
Simulation time 291587533 ps
CPU time 12.48 seconds
Started Jun 13 01:09:45 PM PDT 24
Finished Jun 13 01:09:58 PM PDT 24
Peak memory 199812 kb
Host smart-07893a63-addb-4fa8-af00-320d5e41e2cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419943346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.2419943346
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.4031938959
Short name T215
Test name
Test status
Simulation time 1671457892 ps
CPU time 335.11 seconds
Started Jun 13 01:09:43 PM PDT 24
Finished Jun 13 01:15:19 PM PDT 24
Peak memory 624980 kb
Host smart-53dffee4-dc58-4bce-846f-308b01056839
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031938959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.4031938959
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1703348765
Short name T369
Test name
Test status
Simulation time 3268809787 ps
CPU time 188.54 seconds
Started Jun 13 01:09:54 PM PDT 24
Finished Jun 13 01:13:05 PM PDT 24
Peak memory 199932 kb
Host smart-b5abffbf-b95f-4bb8-a1ed-23a0e58590ff
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703348765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1703348765
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.952160223
Short name T385
Test name
Test status
Simulation time 1142606380 ps
CPU time 17.99 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:10:13 PM PDT 24
Peak memory 199724 kb
Host smart-f7556108-1c12-4a44-81f9-1fd595ac6f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952160223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.952160223
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.2267431061
Short name T581
Test name
Test status
Simulation time 2680470588 ps
CPU time 12.4 seconds
Started Jun 13 01:09:44 PM PDT 24
Finished Jun 13 01:09:57 PM PDT 24
Peak memory 199840 kb
Host smart-6a5d372b-6c41-4944-8c5b-ccaf3b451966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267431061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.2267431061
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.3186799561
Short name T543
Test name
Test status
Simulation time 76113542 ps
CPU time 1.45 seconds
Started Jun 13 01:09:57 PM PDT 24
Finished Jun 13 01:10:00 PM PDT 24
Peak memory 199744 kb
Host smart-4ee2f590-5248-448e-bbc5-60c9b530afbe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186799561 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.hmac_test_hmac_vectors.3186799561
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha_vectors.2232058319
Short name T529
Test name
Test status
Simulation time 13727116880 ps
CPU time 406.69 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:16:44 PM PDT 24
Peak memory 199864 kb
Host smart-b3d2096c-0032-4ce3-bdb3-ac9ac630b163
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232058319 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha_vectors.2232058319
Directory /workspace/11.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.151651977
Short name T225
Test name
Test status
Simulation time 3474540351 ps
CPU time 15.86 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:10:12 PM PDT 24
Peak memory 199736 kb
Host smart-46f4ddd4-e692-4692-abe2-f7e8eec5bd56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151651977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.151651977
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.2436643735
Short name T297
Test name
Test status
Simulation time 36236645 ps
CPU time 0.6 seconds
Started Jun 13 01:09:45 PM PDT 24
Finished Jun 13 01:09:46 PM PDT 24
Peak memory 195852 kb
Host smart-2b82843c-b7fa-474f-b817-f842a197e21f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436643735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.2436643735
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.137679960
Short name T242
Test name
Test status
Simulation time 3373320055 ps
CPU time 11.28 seconds
Started Jun 13 01:09:57 PM PDT 24
Finished Jun 13 01:10:09 PM PDT 24
Peak memory 208044 kb
Host smart-dcdb6170-9f9f-4903-820c-9f763827f592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=137679960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.137679960
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.2560250820
Short name T433
Test name
Test status
Simulation time 6798685357 ps
CPU time 26.39 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:10:22 PM PDT 24
Peak memory 199776 kb
Host smart-dccae42f-53d8-40ac-b73a-89dfa6268d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560250820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.2560250820
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.2998358966
Short name T313
Test name
Test status
Simulation time 1167602195 ps
CPU time 53.76 seconds
Started Jun 13 01:09:56 PM PDT 24
Finished Jun 13 01:10:51 PM PDT 24
Peak memory 331140 kb
Host smart-1481843d-2130-4709-b503-6e499107ec84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2998358966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.2998358966
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3523548793
Short name T50
Test name
Test status
Simulation time 15840180625 ps
CPU time 139.73 seconds
Started Jun 13 01:09:42 PM PDT 24
Finished Jun 13 01:12:03 PM PDT 24
Peak memory 199888 kb
Host smart-2925c821-79f9-42c8-a707-182ab9c396a6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523548793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3523548793
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.975021542
Short name T137
Test name
Test status
Simulation time 448099110 ps
CPU time 7.51 seconds
Started Jun 13 01:09:59 PM PDT 24
Finished Jun 13 01:10:07 PM PDT 24
Peak memory 199732 kb
Host smart-fd9e61c1-e003-410f-8991-3e7ef0475cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975021542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.975021542
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.658999333
Short name T192
Test name
Test status
Simulation time 800501971 ps
CPU time 7.49 seconds
Started Jun 13 01:09:54 PM PDT 24
Finished Jun 13 01:10:03 PM PDT 24
Peak memory 199820 kb
Host smart-a22115e8-5207-46c7-9e8e-36c1bf3675c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658999333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.658999333
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.2279108099
Short name T319
Test name
Test status
Simulation time 256899126702 ps
CPU time 1164.03 seconds
Started Jun 13 01:09:46 PM PDT 24
Finished Jun 13 01:29:11 PM PDT 24
Peak memory 231856 kb
Host smart-dda347fe-e4df-4fdf-bef0-3f311fcc3817
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279108099 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.2279108099
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.216338035
Short name T70
Test name
Test status
Simulation time 168032904 ps
CPU time 1.02 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:09:56 PM PDT 24
Peak memory 199504 kb
Host smart-b74018d2-1c0e-4cc8-9d93-57bcb77a0c5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216338035 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.hmac_test_hmac_vectors.216338035
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha_vectors.4147779165
Short name T347
Test name
Test status
Simulation time 7881165043 ps
CPU time 429.53 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:16:57 PM PDT 24
Peak memory 199772 kb
Host smart-c94e4a2f-08fb-4313-856f-8cc3ef41cdfc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147779165 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha_vectors.4147779165
Directory /workspace/12.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.3587253046
Short name T528
Test name
Test status
Simulation time 3956817805 ps
CPU time 64.65 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:11:01 PM PDT 24
Peak memory 199812 kb
Host smart-fc03eb79-705e-4b47-bc00-50f6a682f1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587253046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.3587253046
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1460474141
Short name T175
Test name
Test status
Simulation time 19448394 ps
CPU time 0.57 seconds
Started Jun 13 01:09:50 PM PDT 24
Finished Jun 13 01:09:51 PM PDT 24
Peak memory 195816 kb
Host smart-757aa81d-63bf-4718-8a6b-3d0e7eaa11ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460474141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1460474141
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.3613117826
Short name T373
Test name
Test status
Simulation time 344541826 ps
CPU time 4.16 seconds
Started Jun 13 01:09:45 PM PDT 24
Finished Jun 13 01:09:50 PM PDT 24
Peak memory 199772 kb
Host smart-edd178a3-60b0-4cbe-b8f1-d965e2fb1ec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3613117826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.3613117826
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.2850328912
Short name T299
Test name
Test status
Simulation time 7094491092 ps
CPU time 73.86 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:11:09 PM PDT 24
Peak memory 199904 kb
Host smart-83b3a54a-48b1-41b7-832d-d1ac21872575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850328912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.2850328912
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.2282478293
Short name T491
Test name
Test status
Simulation time 49048215370 ps
CPU time 1070.93 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:27:39 PM PDT 24
Peak memory 750392 kb
Host smart-83460fee-1ed8-48ef-a447-55366e7fb468
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2282478293 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.2282478293
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1564206164
Short name T231
Test name
Test status
Simulation time 614417816 ps
CPU time 32.94 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:10:30 PM PDT 24
Peak memory 199720 kb
Host smart-226f01ba-85f4-4923-a91b-efbd5bf6be5d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564206164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1564206164
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.2048893615
Short name T446
Test name
Test status
Simulation time 768006337 ps
CPU time 45.21 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:10:40 PM PDT 24
Peak memory 199724 kb
Host smart-5513b2e0-de28-496e-ba88-4991a065756e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048893615 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.2048893615
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3888274368
Short name T387
Test name
Test status
Simulation time 844738040 ps
CPU time 4.52 seconds
Started Jun 13 01:09:45 PM PDT 24
Finished Jun 13 01:09:50 PM PDT 24
Peak memory 199784 kb
Host smart-b9079d10-da4f-4333-bc07-d2e9547ee680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888274368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3888274368
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.697443690
Short name T206
Test name
Test status
Simulation time 59035350385 ps
CPU time 152.75 seconds
Started Jun 13 01:09:46 PM PDT 24
Finished Jun 13 01:12:19 PM PDT 24
Peak memory 199900 kb
Host smart-011931e3-a3ee-44eb-8196-9cb5d36944cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697443690 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.697443690
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.3224181041
Short name T473
Test name
Test status
Simulation time 45405269 ps
CPU time 1.03 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:09:49 PM PDT 24
Peak memory 199296 kb
Host smart-33822c46-d6f2-4a68-b8ef-f0831caa94de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224181041 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.hmac_test_hmac_vectors.3224181041
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha_vectors.3311042056
Short name T577
Test name
Test status
Simulation time 35821658201 ps
CPU time 502.89 seconds
Started Jun 13 01:09:54 PM PDT 24
Finished Jun 13 01:18:19 PM PDT 24
Peak memory 199900 kb
Host smart-add885ef-9c21-4e1c-a725-e741c22935bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311042056 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha_vectors.3311042056
Directory /workspace/13.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2142013201
Short name T284
Test name
Test status
Simulation time 5553100778 ps
CPU time 74.54 seconds
Started Jun 13 01:10:00 PM PDT 24
Finished Jun 13 01:11:15 PM PDT 24
Peak memory 199860 kb
Host smart-4f8e1dec-e43c-4234-b195-2ff9ef08b069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142013201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2142013201
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.3665672198
Short name T51
Test name
Test status
Simulation time 36289781 ps
CPU time 0.53 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:09:57 PM PDT 24
Peak memory 195508 kb
Host smart-72c7b333-cdd3-44ec-96da-9fb9f911ec59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665672198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.3665672198
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.2121796215
Short name T157
Test name
Test status
Simulation time 8067207102 ps
CPU time 57.93 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:10:46 PM PDT 24
Peak memory 224384 kb
Host smart-38f1ec17-40e2-4ba4-ac2d-80147467f226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2121796215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.2121796215
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.627468243
Short name T307
Test name
Test status
Simulation time 55477850885 ps
CPU time 68.38 seconds
Started Jun 13 01:09:45 PM PDT 24
Finished Jun 13 01:10:54 PM PDT 24
Peak memory 199880 kb
Host smart-1d1e7d13-b093-4709-b426-f4214ccc03b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627468243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.627468243
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.2746148418
Short name T176
Test name
Test status
Simulation time 4480291120 ps
CPU time 1155.74 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:29:03 PM PDT 24
Peak memory 730968 kb
Host smart-b4d4c8a8-45d3-4ee8-8b9c-84abec490b33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746148418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.2746148418
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.725256131
Short name T474
Test name
Test status
Simulation time 24159261 ps
CPU time 0.73 seconds
Started Jun 13 01:09:48 PM PDT 24
Finished Jun 13 01:09:50 PM PDT 24
Peak memory 196440 kb
Host smart-d5635e52-8c64-4e6d-ab60-8fc24b5b5a4b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725256131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.725256131
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1876377047
Short name T317
Test name
Test status
Simulation time 13383011609 ps
CPU time 47.17 seconds
Started Jun 13 01:09:43 PM PDT 24
Finished Jun 13 01:10:31 PM PDT 24
Peak memory 199868 kb
Host smart-9bc5dc99-0607-497d-ac51-41904bec965a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876377047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1876377047
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.2139027643
Short name T190
Test name
Test status
Simulation time 78328988 ps
CPU time 1.66 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:09:58 PM PDT 24
Peak memory 199740 kb
Host smart-2fa19545-5b70-4256-a98b-4fd898d70ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139027643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.2139027643
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_stress_all.4130331649
Short name T370
Test name
Test status
Simulation time 165883068514 ps
CPU time 183.77 seconds
Started Jun 13 01:09:59 PM PDT 24
Finished Jun 13 01:13:03 PM PDT 24
Peak memory 215792 kb
Host smart-5b116d24-999c-4af9-b1fb-dd075819a88e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130331649 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.hmac_stress_all.4130331649
Directory /workspace/14.hmac_stress_all/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.1338866479
Short name T438
Test name
Test status
Simulation time 132446172 ps
CPU time 1.23 seconds
Started Jun 13 01:09:57 PM PDT 24
Finished Jun 13 01:10:00 PM PDT 24
Peak memory 199736 kb
Host smart-86f18d58-2516-4295-beb0-d40da9e11396
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338866479 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.hmac_test_hmac_vectors.1338866479
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha_vectors.3991458271
Short name T144
Test name
Test status
Simulation time 25894367957 ps
CPU time 442.82 seconds
Started Jun 13 01:09:43 PM PDT 24
Finished Jun 13 01:17:07 PM PDT 24
Peak memory 199836 kb
Host smart-511c6f0f-329b-4ad2-a1e8-c11c575d7657
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991458271 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha_vectors.3991458271
Directory /workspace/14.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.2749059993
Short name T521
Test name
Test status
Simulation time 274211337 ps
CPU time 5.47 seconds
Started Jun 13 01:09:51 PM PDT 24
Finished Jun 13 01:09:58 PM PDT 24
Peak memory 199772 kb
Host smart-5d33ef68-0850-482c-99d9-e11c27de9dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749059993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.2749059993
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/147.hmac_stress_all_with_rand_reset.1686136386
Short name T8
Test name
Test status
Simulation time 16331708979 ps
CPU time 191.11 seconds
Started Jun 13 02:05:21 PM PDT 24
Finished Jun 13 02:08:34 PM PDT 24
Peak memory 237764 kb
Host smart-ac31e8ee-2e8c-4635-b0b6-baed3c09ef8d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686136386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 147.hmac_stress_all_with_rand_reset.1686136386
Directory /workspace/147.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.hmac_alert_test.3337065157
Short name T300
Test name
Test status
Simulation time 10591793 ps
CPU time 0.63 seconds
Started Jun 13 01:09:49 PM PDT 24
Finished Jun 13 01:09:51 PM PDT 24
Peak memory 194836 kb
Host smart-ba5af0e4-1506-44e9-bd22-cf49e2207126
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337065157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.3337065157
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3432260226
Short name T530
Test name
Test status
Simulation time 419681118 ps
CPU time 20.4 seconds
Started Jun 13 01:09:57 PM PDT 24
Finished Jun 13 01:10:19 PM PDT 24
Peak memory 208004 kb
Host smart-90351898-e3dd-4a6e-b367-f57bbc28c581
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3432260226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3432260226
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.3068093073
Short name T337
Test name
Test status
Simulation time 4359486987 ps
CPU time 53.06 seconds
Started Jun 13 01:09:44 PM PDT 24
Finished Jun 13 01:10:38 PM PDT 24
Peak memory 199908 kb
Host smart-fe70d662-6646-402f-b704-5d624cf152de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068093073 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.3068093073
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3834321851
Short name T273
Test name
Test status
Simulation time 2346010633 ps
CPU time 122.85 seconds
Started Jun 13 01:09:51 PM PDT 24
Finished Jun 13 01:11:55 PM PDT 24
Peak memory 354104 kb
Host smart-99a04759-9b2d-487f-aa4d-77a020ba5789
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3834321851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3834321851
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.276927724
Short name T53
Test name
Test status
Simulation time 10003527670 ps
CPU time 167.43 seconds
Started Jun 13 01:09:50 PM PDT 24
Finished Jun 13 01:12:39 PM PDT 24
Peak memory 199892 kb
Host smart-6ebf6b92-1d95-4813-a7ee-3fbd401f2298
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276927724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.276927724
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.332409850
Short name T127
Test name
Test status
Simulation time 169419000 ps
CPU time 9.06 seconds
Started Jun 13 01:09:46 PM PDT 24
Finished Jun 13 01:09:55 PM PDT 24
Peak memory 199820 kb
Host smart-1fc2aa6f-09a2-4b51-8126-eacc9bc1c601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332409850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.332409850
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1052508880
Short name T264
Test name
Test status
Simulation time 336441126 ps
CPU time 4.88 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:09:53 PM PDT 24
Peak memory 199684 kb
Host smart-34c2ab48-651a-4935-bf56-74811f00ece9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052508880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1052508880
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.1429563876
Short name T578
Test name
Test status
Simulation time 30563126155 ps
CPU time 872.13 seconds
Started Jun 13 01:09:46 PM PDT 24
Finished Jun 13 01:24:19 PM PDT 24
Peak memory 707716 kb
Host smart-aeba0ad6-e733-4cc1-91fe-af82bb9563e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429563876 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.1429563876
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.1950945168
Short name T143
Test name
Test status
Simulation time 214408960 ps
CPU time 1.09 seconds
Started Jun 13 01:09:59 PM PDT 24
Finished Jun 13 01:10:01 PM PDT 24
Peak memory 199788 kb
Host smart-d3a89795-61bd-48a7-8740-89d30ef6ee01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950945168 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.hmac_test_hmac_vectors.1950945168
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha_vectors.3695675601
Short name T207
Test name
Test status
Simulation time 100245580482 ps
CPU time 481.39 seconds
Started Jun 13 01:09:50 PM PDT 24
Finished Jun 13 01:17:53 PM PDT 24
Peak memory 199920 kb
Host smart-e65febdc-9c54-4502-8796-85bd14ed7f23
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695675601 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha_vectors.3695675601
Directory /workspace/15.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.1600981820
Short name T195
Test name
Test status
Simulation time 4325678865 ps
CPU time 30.57 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:10:27 PM PDT 24
Peak memory 199872 kb
Host smart-e3ff20f1-14c9-449d-8972-d9ca238178bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600981820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.1600981820
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1829773411
Short name T406
Test name
Test status
Simulation time 52774486 ps
CPU time 0.59 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:09:58 PM PDT 24
Peak memory 195488 kb
Host smart-31594e87-294b-4f44-b340-4d5a94ac9fea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829773411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1829773411
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.4089445516
Short name T173
Test name
Test status
Simulation time 993194143 ps
CPU time 13.1 seconds
Started Jun 13 01:09:46 PM PDT 24
Finished Jun 13 01:10:00 PM PDT 24
Peak memory 215596 kb
Host smart-6cb08a5c-e1d4-4ece-970c-e5ee76596341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089445516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.4089445516
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2562801958
Short name T363
Test name
Test status
Simulation time 10460187400 ps
CPU time 40.62 seconds
Started Jun 13 01:09:51 PM PDT 24
Finished Jun 13 01:10:33 PM PDT 24
Peak memory 199912 kb
Host smart-c646df8c-b465-4d14-b70f-f815c53b3ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562801958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2562801958
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.4013251272
Short name T169
Test name
Test status
Simulation time 1876137827 ps
CPU time 466.68 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:17:42 PM PDT 24
Peak memory 608996 kb
Host smart-c03abcc1-879b-4aa5-9b6c-b829f3f715f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4013251272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.4013251272
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.432168475
Short name T306
Test name
Test status
Simulation time 28154251378 ps
CPU time 106.86 seconds
Started Jun 13 01:09:50 PM PDT 24
Finished Jun 13 01:11:39 PM PDT 24
Peak memory 199848 kb
Host smart-ba1a3585-1cc1-497c-a0ef-96c0f35b50eb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432168475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.432168475
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.1263966505
Short name T145
Test name
Test status
Simulation time 9824654627 ps
CPU time 130.68 seconds
Started Jun 13 01:09:51 PM PDT 24
Finished Jun 13 01:12:03 PM PDT 24
Peak memory 199736 kb
Host smart-d33296b0-4666-438f-8a8f-d448a61b9684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263966505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.1263966505
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.2053199037
Short name T466
Test name
Test status
Simulation time 758229061 ps
CPU time 7.35 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:01 PM PDT 24
Peak memory 199812 kb
Host smart-84215a05-f58b-4ded-9d9a-c2bb07c7b1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053199037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.2053199037
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.3489458468
Short name T65
Test name
Test status
Simulation time 129836648196 ps
CPU time 2004.25 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:43:19 PM PDT 24
Peak memory 676084 kb
Host smart-ff2e97be-545b-4f96-b55f-9e74dab0d1f8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489458468 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.3489458468
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.1228918335
Short name T283
Test name
Test status
Simulation time 324793220 ps
CPU time 1.38 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:09:56 PM PDT 24
Peak memory 199620 kb
Host smart-c2dde7b5-070b-4892-9104-f50e20d12d69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228918335 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.hmac_test_hmac_vectors.1228918335
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha_vectors.3586693385
Short name T266
Test name
Test status
Simulation time 7483767975 ps
CPU time 414.24 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:16:50 PM PDT 24
Peak memory 199844 kb
Host smart-9caf13bd-7a76-4df8-89a0-ccfafd2ec65a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586693385 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha_vectors.3586693385
Directory /workspace/16.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3268054984
Short name T465
Test name
Test status
Simulation time 1335223775 ps
CPU time 76.42 seconds
Started Jun 13 01:09:51 PM PDT 24
Finished Jun 13 01:11:08 PM PDT 24
Peak memory 199692 kb
Host smart-3c26ea36-4cf1-494a-8f67-46e5dee93fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268054984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3268054984
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.2490880985
Short name T390
Test name
Test status
Simulation time 44241952 ps
CPU time 0.58 seconds
Started Jun 13 01:10:01 PM PDT 24
Finished Jun 13 01:10:02 PM PDT 24
Peak memory 194820 kb
Host smart-b4578f44-37fb-4f51-bc4d-03ed4fdd97cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490880985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.2490880985
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.3015612474
Short name T575
Test name
Test status
Simulation time 1063043246 ps
CPU time 47.06 seconds
Started Jun 13 01:09:54 PM PDT 24
Finished Jun 13 01:10:43 PM PDT 24
Peak memory 216172 kb
Host smart-6820aff6-fe3d-45ec-8eb4-5e9408842dcb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3015612474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.3015612474
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3566268245
Short name T458
Test name
Test status
Simulation time 740403888 ps
CPU time 14.51 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:08 PM PDT 24
Peak memory 199840 kb
Host smart-28a31991-3883-4ed4-afb6-bbc9f1730332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566268245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3566268245
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.584645129
Short name T301
Test name
Test status
Simulation time 47027095030 ps
CPU time 563.87 seconds
Started Jun 13 01:09:58 PM PDT 24
Finished Jun 13 01:19:23 PM PDT 24
Peak memory 681376 kb
Host smart-be894158-52be-456b-b297-06831ec40b13
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584645129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.584645129
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.1244886964
Short name T510
Test name
Test status
Simulation time 7678412008 ps
CPU time 46.8 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:10:44 PM PDT 24
Peak memory 199840 kb
Host smart-8ba3ae50-2154-4492-b004-63453279098e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244886964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.1244886964
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.2282848064
Short name T460
Test name
Test status
Simulation time 9560635382 ps
CPU time 71.36 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:11:07 PM PDT 24
Peak memory 199796 kb
Host smart-4aa0e7f0-1703-4fcb-ab25-3659daeb122c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282848064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.2282848064
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2467088018
Short name T499
Test name
Test status
Simulation time 661338279 ps
CPU time 9.63 seconds
Started Jun 13 01:09:56 PM PDT 24
Finished Jun 13 01:10:07 PM PDT 24
Peak memory 199832 kb
Host smart-c2321759-7f58-43f2-a40b-dc588e4c8e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467088018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2467088018
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_stress_all.184206652
Short name T205
Test name
Test status
Simulation time 52275222247 ps
CPU time 1373.59 seconds
Started Jun 13 01:10:01 PM PDT 24
Finished Jun 13 01:32:56 PM PDT 24
Peak memory 738712 kb
Host smart-3b106045-fbc2-4574-94cf-e1b32463a884
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184206652 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.184206652
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.3846621168
Short name T333
Test name
Test status
Simulation time 45185273 ps
CPU time 1.04 seconds
Started Jun 13 01:09:51 PM PDT 24
Finished Jun 13 01:09:52 PM PDT 24
Peak memory 199572 kb
Host smart-0e733e50-5b39-4994-9ee3-91c93205e63d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846621168 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.hmac_test_hmac_vectors.3846621168
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha_vectors.1035262787
Short name T497
Test name
Test status
Simulation time 16886814153 ps
CPU time 465.7 seconds
Started Jun 13 01:09:59 PM PDT 24
Finished Jun 13 01:17:45 PM PDT 24
Peak memory 199808 kb
Host smart-6e30824a-0a8e-4631-a0fe-c9febf3244e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035262787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha_vectors.1035262787
Directory /workspace/17.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.2521431762
Short name T553
Test name
Test status
Simulation time 2036923225 ps
CPU time 37.46 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:10:34 PM PDT 24
Peak memory 199812 kb
Host smart-8bddc9d5-92c3-403d-bd9f-657a8aab9472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521431762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.2521431762
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.94038681
Short name T236
Test name
Test status
Simulation time 13574598 ps
CPU time 0.61 seconds
Started Jun 13 01:09:59 PM PDT 24
Finished Jun 13 01:10:01 PM PDT 24
Peak memory 196588 kb
Host smart-17d9ef97-9cb1-4542-b50a-69add32de7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94038681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.94038681
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.3042855120
Short name T35
Test name
Test status
Simulation time 626773015 ps
CPU time 34.57 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:29 PM PDT 24
Peak memory 211928 kb
Host smart-842cc0fb-bc35-4458-9cbf-7468bcc7434f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042855120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.3042855120
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3972942251
Short name T536
Test name
Test status
Simulation time 246922972 ps
CPU time 12.6 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:07 PM PDT 24
Peak memory 199808 kb
Host smart-902f6ba8-fe04-4a62-a987-7db7de4c0f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972942251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3972942251
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.1884695522
Short name T154
Test name
Test status
Simulation time 10524049478 ps
CPU time 899.52 seconds
Started Jun 13 01:09:49 PM PDT 24
Finished Jun 13 01:24:49 PM PDT 24
Peak memory 657248 kb
Host smart-0d8316cd-92be-4e2a-86c1-2d7f3ff7cfd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1884695522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.1884695522
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.4086791987
Short name T576
Test name
Test status
Simulation time 26636027218 ps
CPU time 84.02 seconds
Started Jun 13 01:10:05 PM PDT 24
Finished Jun 13 01:11:30 PM PDT 24
Peak memory 199836 kb
Host smart-3aa9a163-9128-4369-a9a5-8b41dff30886
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086791987 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.4086791987
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1423513550
Short name T285
Test name
Test status
Simulation time 75059401884 ps
CPU time 113.22 seconds
Started Jun 13 01:09:50 PM PDT 24
Finished Jun 13 01:11:45 PM PDT 24
Peak memory 199892 kb
Host smart-c85fdcc1-305e-4f43-a980-5efb271c13e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423513550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1423513550
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.501803332
Short name T533
Test name
Test status
Simulation time 55256617 ps
CPU time 1.92 seconds
Started Jun 13 01:10:10 PM PDT 24
Finished Jun 13 01:10:12 PM PDT 24
Peak memory 199764 kb
Host smart-14c1626c-1a51-4140-a9f9-6d913a0a25c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501803332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.501803332
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1988372100
Short name T364
Test name
Test status
Simulation time 87251151560 ps
CPU time 1990.27 seconds
Started Jun 13 01:10:01 PM PDT 24
Finished Jun 13 01:43:12 PM PDT 24
Peak memory 800676 kb
Host smart-b1465923-343c-438e-8904-47a9f45a46f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988372100 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1988372100
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.4224275583
Short name T591
Test name
Test status
Simulation time 103228253 ps
CPU time 1.04 seconds
Started Jun 13 01:10:01 PM PDT 24
Finished Jun 13 01:10:04 PM PDT 24
Peak memory 199480 kb
Host smart-3eab9afb-d154-42e4-a346-d255085bbd08
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224275583 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.hmac_test_hmac_vectors.4224275583
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha_vectors.3048492675
Short name T492
Test name
Test status
Simulation time 27229674545 ps
CPU time 474.33 seconds
Started Jun 13 01:09:54 PM PDT 24
Finished Jun 13 01:17:51 PM PDT 24
Peak memory 199880 kb
Host smart-e859b965-b45c-4cfd-994e-01b13c0b3ac1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048492675 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha_vectors.3048492675
Directory /workspace/18.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2244727781
Short name T422
Test name
Test status
Simulation time 1697784098 ps
CPU time 13.21 seconds
Started Jun 13 01:09:59 PM PDT 24
Finished Jun 13 01:10:13 PM PDT 24
Peak memory 199848 kb
Host smart-8393d4ce-d20e-462e-a2e7-9ab6c646f7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244727781 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2244727781
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2939367812
Short name T202
Test name
Test status
Simulation time 44565962 ps
CPU time 0.59 seconds
Started Jun 13 01:09:49 PM PDT 24
Finished Jun 13 01:09:51 PM PDT 24
Peak memory 195884 kb
Host smart-6b20f157-46ae-4a34-95a6-01c42ae1fcc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939367812 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2939367812
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.1863316791
Short name T219
Test name
Test status
Simulation time 16028440797 ps
CPU time 50.85 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:45 PM PDT 24
Peak memory 222436 kb
Host smart-6e106b22-6fdd-43fa-bacf-e57bf5bc41f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1863316791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.1863316791
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.3842820145
Short name T262
Test name
Test status
Simulation time 2877871831 ps
CPU time 49.72 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:43 PM PDT 24
Peak memory 199852 kb
Host smart-27db537c-f279-4e62-8786-600c39594c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842820145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.3842820145
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.4291626521
Short name T448
Test name
Test status
Simulation time 2262842931 ps
CPU time 548.17 seconds
Started Jun 13 01:09:57 PM PDT 24
Finished Jun 13 01:19:07 PM PDT 24
Peak memory 717300 kb
Host smart-5158cbfc-9a83-45d9-9ef3-d0b9b1a610e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4291626521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.4291626521
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.2723770038
Short name T263
Test name
Test status
Simulation time 554116376 ps
CPU time 13.65 seconds
Started Jun 13 01:10:01 PM PDT 24
Finished Jun 13 01:10:16 PM PDT 24
Peak memory 199652 kb
Host smart-2a1a5d73-9823-4cfc-9648-57ae8aa68579
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723770038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.2723770038
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.3867854140
Short name T435
Test name
Test status
Simulation time 8624059594 ps
CPU time 29.98 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:24 PM PDT 24
Peak memory 199876 kb
Host smart-332607fa-4fcb-427f-a6f7-e5f52ba22e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867854140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.3867854140
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.3373336418
Short name T13
Test name
Test status
Simulation time 132027643 ps
CPU time 4.71 seconds
Started Jun 13 01:09:56 PM PDT 24
Finished Jun 13 01:10:02 PM PDT 24
Peak memory 199860 kb
Host smart-f89082f4-3825-433e-9939-5f7d9fbbad72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373336418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.3373336418
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1541824575
Short name T289
Test name
Test status
Simulation time 72195017707 ps
CPU time 1716.31 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:38:31 PM PDT 24
Peak memory 700716 kb
Host smart-971d0f37-6d85-4d91-98a0-24bdc82fcda5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541824575 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1541824575
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.2960166162
Short name T464
Test name
Test status
Simulation time 85330911 ps
CPU time 1.51 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:09:56 PM PDT 24
Peak memory 199744 kb
Host smart-4d2bdc19-70e5-41bc-b82f-a496942d593c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960166162 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.hmac_test_hmac_vectors.2960166162
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha_vectors.392163742
Short name T248
Test name
Test status
Simulation time 118015512857 ps
CPU time 533.2 seconds
Started Jun 13 01:09:58 PM PDT 24
Finished Jun 13 01:18:52 PM PDT 24
Peak memory 199876 kb
Host smart-0a5d72b2-540a-4932-81c5-85216b4c8c49
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392163742 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha_vectors.392163742
Directory /workspace/19.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.35933817
Short name T288
Test name
Test status
Simulation time 7293707967 ps
CPU time 70.05 seconds
Started Jun 13 01:09:54 PM PDT 24
Finished Jun 13 01:11:06 PM PDT 24
Peak memory 199928 kb
Host smart-f71b4bd9-7dbb-4c98-ac28-a44dc99123ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35933817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.35933817
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1347584821
Short name T19
Test name
Test status
Simulation time 18776016 ps
CPU time 0.61 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:09:49 PM PDT 24
Peak memory 194796 kb
Host smart-41e055b1-2968-4217-ac84-0bd19bf30bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347584821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1347584821
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.2600970998
Short name T518
Test name
Test status
Simulation time 6191861768 ps
CPU time 45.74 seconds
Started Jun 13 01:09:36 PM PDT 24
Finished Jun 13 01:10:23 PM PDT 24
Peak memory 225668 kb
Host smart-80d34de1-2d70-4eda-b49a-30494ab310b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600970998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.2600970998
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2953911144
Short name T166
Test name
Test status
Simulation time 2375469382 ps
CPU time 46.83 seconds
Started Jun 13 01:09:30 PM PDT 24
Finished Jun 13 01:10:18 PM PDT 24
Peak memory 199892 kb
Host smart-133f5d97-3b3d-4a5f-b142-138f034ffd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953911144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2953911144
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.555771898
Short name T291
Test name
Test status
Simulation time 6957393157 ps
CPU time 836.54 seconds
Started Jun 13 01:09:41 PM PDT 24
Finished Jun 13 01:23:39 PM PDT 24
Peak memory 755608 kb
Host smart-cb9c0c79-3f85-4e37-8a2d-83343bbc5d56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=555771898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.555771898
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.1981014575
Short name T338
Test name
Test status
Simulation time 2178928797 ps
CPU time 126.78 seconds
Started Jun 13 01:09:29 PM PDT 24
Finished Jun 13 01:11:37 PM PDT 24
Peak memory 199872 kb
Host smart-9c30068e-6fa8-495d-9dd2-66f391a4d5e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981014575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.1981014575
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.224756565
Short name T280
Test name
Test status
Simulation time 4120713227 ps
CPU time 26.4 seconds
Started Jun 13 01:09:48 PM PDT 24
Finished Jun 13 01:10:15 PM PDT 24
Peak memory 199900 kb
Host smart-aec11e7a-37e7-475c-a61c-50ab47f57ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224756565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.224756565
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.1578113646
Short name T30
Test name
Test status
Simulation time 758730411 ps
CPU time 1 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:09:55 PM PDT 24
Peak memory 219328 kb
Host smart-307e4184-1728-4afc-8545-2bd572a06327
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578113646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.1578113646
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2760073164
Short name T312
Test name
Test status
Simulation time 268536268 ps
CPU time 2.89 seconds
Started Jun 13 01:09:29 PM PDT 24
Finished Jun 13 01:09:33 PM PDT 24
Peak memory 199844 kb
Host smart-6bd54f07-6daa-43a8-91f6-a4ba82f0e271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760073164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2760073164
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_stress_all.4232681340
Short name T164
Test name
Test status
Simulation time 8038829792 ps
CPU time 49.83 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:43 PM PDT 24
Peak memory 199892 kb
Host smart-12022be6-eccd-44b5-a30f-92eafe3e68dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232681340 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.hmac_stress_all.4232681340
Directory /workspace/2.hmac_stress_all/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.66181515
Short name T113
Test name
Test status
Simulation time 175614387 ps
CPU time 1.04 seconds
Started Jun 13 01:09:41 PM PDT 24
Finished Jun 13 01:09:43 PM PDT 24
Peak memory 199580 kb
Host smart-5cf34ade-06be-4cee-bb8b-359e8a418437
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66181515 -assert nopostproc +UVM_TESTNAME=hmac_base_t
est +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 2.hmac_test_hmac_vectors.66181515
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha_vectors.2086993244
Short name T158
Test name
Test status
Simulation time 108454201423 ps
CPU time 473.23 seconds
Started Jun 13 01:09:30 PM PDT 24
Finished Jun 13 01:17:24 PM PDT 24
Peak memory 199844 kb
Host smart-8e7de9c7-785f-4fae-9981-a9e1c1de91b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086993244 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha_vectors.2086993244
Directory /workspace/2.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.479228719
Short name T345
Test name
Test status
Simulation time 1290878593 ps
CPU time 36.31 seconds
Started Jun 13 01:09:34 PM PDT 24
Finished Jun 13 01:10:12 PM PDT 24
Peak memory 199796 kb
Host smart-bec3807a-763d-4d74-9d0d-7eb6f7319e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479228719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.479228719
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2890630305
Short name T534
Test name
Test status
Simulation time 19163390 ps
CPU time 0.63 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:09:56 PM PDT 24
Peak memory 196584 kb
Host smart-1da1db38-864a-41a4-a220-ef9b389a8511
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890630305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2890630305
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2055151969
Short name T445
Test name
Test status
Simulation time 4323387737 ps
CPU time 54.11 seconds
Started Jun 13 01:10:00 PM PDT 24
Finished Jun 13 01:10:55 PM PDT 24
Peak memory 216260 kb
Host smart-035d1c97-b93e-456c-acbf-6e4cfd6313c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055151969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2055151969
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.464640710
Short name T119
Test name
Test status
Simulation time 177792430 ps
CPU time 9.7 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:03 PM PDT 24
Peak memory 199812 kb
Host smart-009fa430-be3c-4927-9acb-19c538036090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464640710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.464640710
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2731378133
Short name T165
Test name
Test status
Simulation time 2062718447 ps
CPU time 545.43 seconds
Started Jun 13 01:09:58 PM PDT 24
Finished Jun 13 01:19:04 PM PDT 24
Peak memory 721592 kb
Host smart-4464b685-eb03-48cb-a530-5cd937ab52b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731378133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2731378133
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3991321869
Short name T223
Test name
Test status
Simulation time 40914548534 ps
CPU time 126.52 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:12:01 PM PDT 24
Peak memory 199860 kb
Host smart-701dca10-2d18-422c-bd9d-ac8e9a68003e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991321869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3991321869
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.984314737
Short name T310
Test name
Test status
Simulation time 650472171 ps
CPU time 35.24 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:29 PM PDT 24
Peak memory 199856 kb
Host smart-0e4ca62f-9c0b-4dd6-ad08-8dfc12291d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984314737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.984314737
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.1684990154
Short name T376
Test name
Test status
Simulation time 49922475 ps
CPU time 1.24 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:09:55 PM PDT 24
Peak memory 199792 kb
Host smart-fa0eaf7a-725d-4cc4-9dd7-77907e7bec4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684990154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.1684990154
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_stress_all.1214162769
Short name T99
Test name
Test status
Simulation time 16235380825 ps
CPU time 447.18 seconds
Started Jun 13 01:09:58 PM PDT 24
Finished Jun 13 01:17:26 PM PDT 24
Peak memory 215952 kb
Host smart-067aeba4-c834-4e27-801e-814005fe1f0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214162769 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.1214162769
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.964116321
Short name T298
Test name
Test status
Simulation time 103694224 ps
CPU time 0.99 seconds
Started Jun 13 01:09:54 PM PDT 24
Finished Jun 13 01:09:57 PM PDT 24
Peak memory 199492 kb
Host smart-8d77972f-66e8-4e2e-8437-e6ee4c9453ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964116321 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.hmac_test_hmac_vectors.964116321
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha_vectors.1315759278
Short name T468
Test name
Test status
Simulation time 25585969707 ps
CPU time 459.49 seconds
Started Jun 13 01:10:03 PM PDT 24
Finished Jun 13 01:17:43 PM PDT 24
Peak memory 199720 kb
Host smart-ee1b0dbb-5d72-47bf-9b8f-8dcd9e10312f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315759278 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha_vectors.1315759278
Directory /workspace/20.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.1613793902
Short name T334
Test name
Test status
Simulation time 22535779621 ps
CPU time 110.85 seconds
Started Jun 13 01:09:54 PM PDT 24
Finished Jun 13 01:11:47 PM PDT 24
Peak memory 199796 kb
Host smart-22ac8daf-0625-408d-b800-51003e8b6015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613793902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.1613793902
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.4157493674
Short name T571
Test name
Test status
Simulation time 12291176 ps
CPU time 0.56 seconds
Started Jun 13 01:10:03 PM PDT 24
Finished Jun 13 01:10:04 PM PDT 24
Peak memory 194564 kb
Host smart-2e174914-7713-44d5-800e-51b766fab045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157493674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.4157493674
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1363256815
Short name T393
Test name
Test status
Simulation time 748764961 ps
CPU time 36.89 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:31 PM PDT 24
Peak memory 225396 kb
Host smart-6d71d442-ef51-47d4-a823-93dbd14a1068
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1363256815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1363256815
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.4098241909
Short name T160
Test name
Test status
Simulation time 2972784107 ps
CPU time 46.26 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:10:43 PM PDT 24
Peak memory 199864 kb
Host smart-5cd6181f-5acf-42ef-bd9f-123cd7f0432a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098241909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.4098241909
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.1988636976
Short name T123
Test name
Test status
Simulation time 7295714911 ps
CPU time 1045.74 seconds
Started Jun 13 01:10:01 PM PDT 24
Finished Jun 13 01:27:28 PM PDT 24
Peak memory 759272 kb
Host smart-845eb63a-f94a-4411-a9ca-e8e2bd5fd2b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1988636976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.1988636976
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3461415867
Short name T224
Test name
Test status
Simulation time 5248658041 ps
CPU time 94.91 seconds
Started Jun 13 01:09:54 PM PDT 24
Finished Jun 13 01:11:31 PM PDT 24
Peak memory 199732 kb
Host smart-ffb5dd3a-b27f-4524-b10b-4e9a8fa04868
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461415867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3461415867
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1083455212
Short name T146
Test name
Test status
Simulation time 6374285709 ps
CPU time 127.15 seconds
Started Jun 13 01:09:58 PM PDT 24
Finished Jun 13 01:12:06 PM PDT 24
Peak memory 199780 kb
Host smart-edc96736-2ed2-47ea-855b-5f8dd48e6ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083455212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1083455212
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.3550607970
Short name T509
Test name
Test status
Simulation time 1670978484 ps
CPU time 7.61 seconds
Started Jun 13 01:09:55 PM PDT 24
Finished Jun 13 01:10:05 PM PDT 24
Peak memory 199800 kb
Host smart-26a80f1b-e48b-4564-9b14-9e5cbbbdd5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550607970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.3550607970
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.1604931145
Short name T350
Test name
Test status
Simulation time 7140215010 ps
CPU time 108.63 seconds
Started Jun 13 01:09:59 PM PDT 24
Finished Jun 13 01:11:48 PM PDT 24
Peak memory 199768 kb
Host smart-bcb44bcc-04f5-4a60-a6e5-c323fa5827a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604931145 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.1604931145
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1134569415
Short name T558
Test name
Test status
Simulation time 530144760 ps
CPU time 1.01 seconds
Started Jun 13 01:10:02 PM PDT 24
Finished Jun 13 01:10:04 PM PDT 24
Peak memory 199736 kb
Host smart-3972c517-1ca2-415a-a79a-907a059e68b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134569415 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.hmac_test_hmac_vectors.1134569415
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha_vectors.1573738357
Short name T388
Test name
Test status
Simulation time 8797516283 ps
CPU time 481.43 seconds
Started Jun 13 01:10:01 PM PDT 24
Finished Jun 13 01:18:03 PM PDT 24
Peak memory 199796 kb
Host smart-3d5627ad-288e-4965-8d47-5e5ef6510ada
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573738357 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha_vectors.1573738357
Directory /workspace/21.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.2986943072
Short name T486
Test name
Test status
Simulation time 7236812779 ps
CPU time 67.89 seconds
Started Jun 13 01:10:02 PM PDT 24
Finished Jun 13 01:11:11 PM PDT 24
Peak memory 199776 kb
Host smart-0fded103-1aa4-4e9c-87cd-f5f684ce3523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986943072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.2986943072
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.1827665042
Short name T249
Test name
Test status
Simulation time 14315389 ps
CPU time 0.56 seconds
Started Jun 13 01:10:19 PM PDT 24
Finished Jun 13 01:10:20 PM PDT 24
Peak memory 194820 kb
Host smart-cda4ff1e-06cd-4b79-a2db-5d95b731cbcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827665042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.1827665042
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.2309850338
Short name T32
Test name
Test status
Simulation time 4142034255 ps
CPU time 27.62 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:10:21 PM PDT 24
Peak memory 229072 kb
Host smart-cbb27af0-0cac-4fa0-afb7-438ab016ac75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2309850338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.2309850338
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2059878863
Short name T138
Test name
Test status
Simulation time 9349350307 ps
CPU time 40.1 seconds
Started Jun 13 01:10:23 PM PDT 24
Finished Jun 13 01:11:04 PM PDT 24
Peak memory 199876 kb
Host smart-183eb925-8512-497b-a07b-ff7c4dd5c0cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059878863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2059878863
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.3953271326
Short name T326
Test name
Test status
Simulation time 1509866450 ps
CPU time 370.74 seconds
Started Jun 13 01:10:19 PM PDT 24
Finished Jun 13 01:16:30 PM PDT 24
Peak memory 498800 kb
Host smart-faa5000d-ff59-47ae-8a0a-9ce1b0cac0d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3953271326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.3953271326
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.3575982977
Short name T372
Test name
Test status
Simulation time 1728800780 ps
CPU time 101.6 seconds
Started Jun 13 01:10:18 PM PDT 24
Finished Jun 13 01:12:00 PM PDT 24
Peak memory 199780 kb
Host smart-f07587d5-8b82-4187-ba54-447748915201
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575982977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.3575982977
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_smoke.89894537
Short name T572
Test name
Test status
Simulation time 137645457 ps
CPU time 2.02 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:09:57 PM PDT 24
Peak memory 199736 kb
Host smart-eb7761e5-62a7-4cb9-99ba-f39b5f46aa84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89894537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.89894537
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_stress_all.1311477527
Short name T64
Test name
Test status
Simulation time 155045442401 ps
CPU time 1425.46 seconds
Started Jun 13 01:10:21 PM PDT 24
Finished Jun 13 01:34:07 PM PDT 24
Peak memory 660528 kb
Host smart-036339ca-3205-4625-a298-04211b975566
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311477527 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.1311477527
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/22.hmac_stress_all_with_rand_reset.3773092203
Short name T9
Test name
Test status
Simulation time 70497562167 ps
CPU time 1063.66 seconds
Started Jun 13 01:10:23 PM PDT 24
Finished Jun 13 01:28:07 PM PDT 24
Peak memory 266828 kb
Host smart-bef65b68-6d55-4f59-96dc-57558e75e546
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3773092203 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all_with_rand_reset.3773092203
Directory /workspace/22.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.3253983641
Short name T559
Test name
Test status
Simulation time 41514556 ps
CPU time 0.97 seconds
Started Jun 13 01:10:16 PM PDT 24
Finished Jun 13 01:10:18 PM PDT 24
Peak memory 199608 kb
Host smart-1ba42cc7-f542-4639-b744-d71f63fba080
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253983641 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.hmac_test_hmac_vectors.3253983641
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha_vectors.3290632062
Short name T322
Test name
Test status
Simulation time 114872796202 ps
CPU time 461.11 seconds
Started Jun 13 01:10:17 PM PDT 24
Finished Jun 13 01:18:00 PM PDT 24
Peak memory 199800 kb
Host smart-8bed1843-a507-4d1c-b7f9-1a87ece71d00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290632062 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha_vectors.3290632062
Directory /workspace/22.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.4080335609
Short name T378
Test name
Test status
Simulation time 4822534023 ps
CPU time 67.46 seconds
Started Jun 13 01:10:16 PM PDT 24
Finished Jun 13 01:11:24 PM PDT 24
Peak memory 199840 kb
Host smart-222acdfc-3c44-411d-b238-7e608e2cab4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080335609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.4080335609
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.3803624358
Short name T414
Test name
Test status
Simulation time 22125134 ps
CPU time 0.62 seconds
Started Jun 13 01:10:18 PM PDT 24
Finished Jun 13 01:10:19 PM PDT 24
Peak memory 196572 kb
Host smart-18561ac8-da32-42fd-a4f1-4b9fc90a5da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803624358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.3803624358
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.38598961
Short name T542
Test name
Test status
Simulation time 381904739 ps
CPU time 10.25 seconds
Started Jun 13 01:10:16 PM PDT 24
Finished Jun 13 01:10:27 PM PDT 24
Peak memory 207972 kb
Host smart-f7190f4d-5b4c-4a86-895f-cb1d783811e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=38598961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.38598961
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.4019883321
Short name T382
Test name
Test status
Simulation time 9347582372 ps
CPU time 32.19 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:10:53 PM PDT 24
Peak memory 199932 kb
Host smart-8605a754-e970-4f42-8076-af86e0dd7381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019883321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.4019883321
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.12879744
Short name T404
Test name
Test status
Simulation time 4043274995 ps
CPU time 1168.82 seconds
Started Jun 13 01:10:17 PM PDT 24
Finished Jun 13 01:29:47 PM PDT 24
Peak memory 778176 kb
Host smart-84a6d345-1fea-4aed-9cf5-f7702cb0b552
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=12879744 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.12879744
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.953748187
Short name T269
Test name
Test status
Simulation time 13281947526 ps
CPU time 47.76 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:11:09 PM PDT 24
Peak memory 199732 kb
Host smart-a6703f53-682a-4e6a-bb2f-01f478607331
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953748187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.953748187
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.1805892530
Short name T258
Test name
Test status
Simulation time 14424414970 ps
CPU time 98.76 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:12:00 PM PDT 24
Peak memory 199860 kb
Host smart-43f31380-0937-4a69-9662-e0b329d7b3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805892530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.1805892530
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.1862338816
Short name T434
Test name
Test status
Simulation time 54577389 ps
CPU time 1.95 seconds
Started Jun 13 01:10:19 PM PDT 24
Finished Jun 13 01:10:22 PM PDT 24
Peak memory 199804 kb
Host smart-6a768896-2b29-4da3-832f-9cda5a1c624b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862338816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.1862338816
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.1748533862
Short name T97
Test name
Test status
Simulation time 101863739542 ps
CPU time 1469.95 seconds
Started Jun 13 01:10:19 PM PDT 24
Finished Jun 13 01:34:50 PM PDT 24
Peak memory 692996 kb
Host smart-a08e2dec-58a9-4f1b-be45-c42ec4f9c02b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748533862 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.1748533862
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.271474697
Short name T131
Test name
Test status
Simulation time 196254199 ps
CPU time 1.24 seconds
Started Jun 13 01:10:16 PM PDT 24
Finished Jun 13 01:10:18 PM PDT 24
Peak memory 199828 kb
Host smart-186d24ca-8ec0-4c1f-9408-1ab2867a0ac8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271474697 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 23.hmac_test_hmac_vectors.271474697
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha_vectors.691735585
Short name T44
Test name
Test status
Simulation time 246573957906 ps
CPU time 511.52 seconds
Started Jun 13 01:10:23 PM PDT 24
Finished Jun 13 01:18:55 PM PDT 24
Peak memory 199816 kb
Host smart-9a7fa59e-2702-4196-8c74-77a8f84d7d0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691735585 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha_vectors.691735585
Directory /workspace/23.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1639107547
Short name T527
Test name
Test status
Simulation time 909238538 ps
CPU time 15.54 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:10:37 PM PDT 24
Peak memory 199820 kb
Host smart-f9f68b01-68f5-4b06-a329-0d67da37a65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639107547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1639107547
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.3140698326
Short name T234
Test name
Test status
Simulation time 70593308 ps
CPU time 0.6 seconds
Started Jun 13 01:10:17 PM PDT 24
Finished Jun 13 01:10:18 PM PDT 24
Peak memory 195860 kb
Host smart-60a25e09-58bd-43fa-b4ee-1c682fdc4857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140698326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.3140698326
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.1918345595
Short name T203
Test name
Test status
Simulation time 684935070 ps
CPU time 4.7 seconds
Started Jun 13 01:10:16 PM PDT 24
Finished Jun 13 01:10:21 PM PDT 24
Peak memory 199680 kb
Host smart-1c4c7efd-4ff9-44bb-9032-ebe36d6c9ad6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918345595 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.1918345595
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.4020159327
Short name T590
Test name
Test status
Simulation time 9296213428 ps
CPU time 30.94 seconds
Started Jun 13 01:10:17 PM PDT 24
Finished Jun 13 01:10:49 PM PDT 24
Peak memory 199892 kb
Host smart-6b45fde1-5239-4750-8db0-fec38b8d0901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020159327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.4020159327
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2683905238
Short name T357
Test name
Test status
Simulation time 14186974983 ps
CPU time 827.54 seconds
Started Jun 13 01:10:21 PM PDT 24
Finished Jun 13 01:24:09 PM PDT 24
Peak memory 756248 kb
Host smart-cc48b728-777f-423b-8bce-cf866c61e2ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2683905238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2683905238
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.4153873102
Short name T275
Test name
Test status
Simulation time 378444410 ps
CPU time 22.17 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:10:43 PM PDT 24
Peak memory 199824 kb
Host smart-028ae58f-f5d4-4525-919a-5ad010aabd23
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153873102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.4153873102
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.2486838948
Short name T261
Test name
Test status
Simulation time 1107397265 ps
CPU time 62.99 seconds
Started Jun 13 01:10:17 PM PDT 24
Finished Jun 13 01:11:21 PM PDT 24
Peak memory 199768 kb
Host smart-fbbce6cd-ba8a-4aee-975a-116ebea0ed38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486838948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.2486838948
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.3466794100
Short name T391
Test name
Test status
Simulation time 392386338 ps
CPU time 3.03 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:10:24 PM PDT 24
Peak memory 199784 kb
Host smart-515d7f68-c38f-447f-9c65-14ead01cf989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466794100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.3466794100
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.4121444285
Short name T254
Test name
Test status
Simulation time 122620545466 ps
CPU time 363.33 seconds
Started Jun 13 01:10:18 PM PDT 24
Finished Jun 13 01:16:23 PM PDT 24
Peak memory 199864 kb
Host smart-15b02c50-004d-4072-8363-d6750f2bd683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121444285 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.4121444285
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.4228260268
Short name T134
Test name
Test status
Simulation time 44504694 ps
CPU time 1.1 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:10:22 PM PDT 24
Peak memory 199556 kb
Host smart-c85d84c9-d3fa-4288-994c-1ddf21b466e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228260268 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.hmac_test_hmac_vectors.4228260268
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha_vectors.3097643495
Short name T172
Test name
Test status
Simulation time 105824883876 ps
CPU time 367.39 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:16:28 PM PDT 24
Peak memory 199908 kb
Host smart-9320e691-088a-47cc-b518-ca0136388cbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097643495 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha_vectors.3097643495
Directory /workspace/24.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.2906027933
Short name T539
Test name
Test status
Simulation time 14383730747 ps
CPU time 72.29 seconds
Started Jun 13 01:10:18 PM PDT 24
Finished Jun 13 01:11:31 PM PDT 24
Peak memory 199844 kb
Host smart-ffb7c481-b8f2-46da-a824-f88501c81f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906027933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.2906027933
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.291904581
Short name T493
Test name
Test status
Simulation time 10203719 ps
CPU time 0.58 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:10:22 PM PDT 24
Peak memory 195544 kb
Host smart-0a90fecf-357a-44d9-931d-91d30be96e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291904581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.291904581
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2638744974
Short name T227
Test name
Test status
Simulation time 751389020 ps
CPU time 40.74 seconds
Started Jun 13 01:10:19 PM PDT 24
Finished Jun 13 01:11:01 PM PDT 24
Peak memory 229396 kb
Host smart-65016b17-55e6-40a0-9d8e-f59aa3f73405
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2638744974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2638744974
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3750879294
Short name T21
Test name
Test status
Simulation time 785066106 ps
CPU time 21.66 seconds
Started Jun 13 01:10:19 PM PDT 24
Finished Jun 13 01:10:41 PM PDT 24
Peak memory 199804 kb
Host smart-47c5c191-629d-41a1-8ce9-e5ece2169eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750879294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3750879294
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.2835483903
Short name T462
Test name
Test status
Simulation time 464469437 ps
CPU time 117.78 seconds
Started Jun 13 01:10:21 PM PDT 24
Finished Jun 13 01:12:19 PM PDT 24
Peak memory 612500 kb
Host smart-500fb115-a02a-434e-9712-e60c652033c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835483903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.2835483903
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.4030681502
Short name T276
Test name
Test status
Simulation time 12136217914 ps
CPU time 42.72 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:11:03 PM PDT 24
Peak memory 199848 kb
Host smart-7cb88461-5439-4031-93c9-14682206c2f5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030681502 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.4030681502
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.2204560384
Short name T436
Test name
Test status
Simulation time 1265288534 ps
CPU time 6.06 seconds
Started Jun 13 01:10:18 PM PDT 24
Finished Jun 13 01:10:25 PM PDT 24
Peak memory 199724 kb
Host smart-15d7f304-44c6-476d-85be-913932bf9798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204560384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.2204560384
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.1701091521
Short name T246
Test name
Test status
Simulation time 161181657 ps
CPU time 1.02 seconds
Started Jun 13 01:10:19 PM PDT 24
Finished Jun 13 01:10:21 PM PDT 24
Peak memory 199580 kb
Host smart-26531c42-e662-467a-9ec2-c6a74639ff5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701091521 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.1701091521
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.1912653355
Short name T501
Test name
Test status
Simulation time 69615382 ps
CPU time 1.27 seconds
Started Jun 13 01:10:18 PM PDT 24
Finished Jun 13 01:10:20 PM PDT 24
Peak memory 199792 kb
Host smart-5e1f0c78-d53f-4d4a-ab51-6e9080ab39f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912653355 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.hmac_test_hmac_vectors.1912653355
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha_vectors.4205444199
Short name T336
Test name
Test status
Simulation time 488308041196 ps
CPU time 457.57 seconds
Started Jun 13 01:10:20 PM PDT 24
Finished Jun 13 01:17:59 PM PDT 24
Peak memory 199848 kb
Host smart-f43aa5ac-a714-4884-953f-063b418b9b76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205444199 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha_vectors.4205444199
Directory /workspace/25.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2181752054
Short name T292
Test name
Test status
Simulation time 4966734801 ps
CPU time 68.18 seconds
Started Jun 13 01:10:18 PM PDT 24
Finished Jun 13 01:11:27 PM PDT 24
Peak memory 199860 kb
Host smart-7616455a-b9f8-45ed-99fe-4f8d2cc28262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181752054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2181752054
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.3143790289
Short name T244
Test name
Test status
Simulation time 22472417 ps
CPU time 0.6 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:10:56 PM PDT 24
Peak memory 195652 kb
Host smart-fc67f195-24c2-4320-9022-8c1b8d440c30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143790289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.3143790289
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2880471784
Short name T308
Test name
Test status
Simulation time 2393149919 ps
CPU time 43.69 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:11:35 PM PDT 24
Peak memory 208048 kb
Host smart-1e7bf2f5-4fff-42fb-af1b-eace82a9dfdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880471784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2880471784
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.891858756
Short name T548
Test name
Test status
Simulation time 48529387514 ps
CPU time 51.55 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:11:48 PM PDT 24
Peak memory 199844 kb
Host smart-b1d8a1f4-b505-4963-8a29-0b6ca3181886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891858756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.891858756
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.1318650274
Short name T399
Test name
Test status
Simulation time 417610082 ps
CPU time 30.38 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:11:24 PM PDT 24
Peak memory 252588 kb
Host smart-7d35425b-7bb0-4649-9483-a94b69068963
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1318650274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.1318650274
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.3046023116
Short name T73
Test name
Test status
Simulation time 6587714185 ps
CPU time 86.52 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:12:21 PM PDT 24
Peak memory 199840 kb
Host smart-044f5d51-6dfd-45a5-956a-0f50cb02c864
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046023116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.3046023116
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3300242669
Short name T279
Test name
Test status
Simulation time 1557117135 ps
CPU time 92.41 seconds
Started Jun 13 01:10:18 PM PDT 24
Finished Jun 13 01:11:51 PM PDT 24
Peak memory 199840 kb
Host smart-4dfe8341-cef6-4afb-9d86-d86b1d82974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300242669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3300242669
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1868107358
Short name T245
Test name
Test status
Simulation time 200401417 ps
CPU time 3.74 seconds
Started Jun 13 01:10:17 PM PDT 24
Finished Jun 13 01:10:22 PM PDT 24
Peak memory 199784 kb
Host smart-3485118b-99d9-44b1-a1b2-23a94f16a188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868107358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1868107358
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.2130728795
Short name T56
Test name
Test status
Simulation time 34285818072 ps
CPU time 1060.97 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:28:33 PM PDT 24
Peak memory 741852 kb
Host smart-d0fad8ae-ebe6-4e32-8726-13421ab91173
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130728795 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.2130728795
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.1152383283
Short name T374
Test name
Test status
Simulation time 52049269 ps
CPU time 1.03 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:10:55 PM PDT 24
Peak memory 199608 kb
Host smart-db6f4eee-2621-46bc-8e16-aef108f6dec9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152383283 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.hmac_test_hmac_vectors.1152383283
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha_vectors.702621762
Short name T191
Test name
Test status
Simulation time 168081655445 ps
CPU time 582.21 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:20:32 PM PDT 24
Peak memory 199848 kb
Host smart-5f50a6d2-57c6-45d8-a558-8232b40b52ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702621762 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha_vectors.702621762
Directory /workspace/26.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1988987227
Short name T367
Test name
Test status
Simulation time 20255686616 ps
CPU time 79.09 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:12:17 PM PDT 24
Peak memory 199780 kb
Host smart-facadd11-bf60-4dc0-8252-5b93b9cb5429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988987227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1988987227
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.530410821
Short name T159
Test name
Test status
Simulation time 48199814 ps
CPU time 0.61 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:10:59 PM PDT 24
Peak memory 195848 kb
Host smart-6fcbd03b-d538-4ce0-a53f-0f17254cdbf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530410821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.530410821
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.1490658311
Short name T142
Test name
Test status
Simulation time 1429108538 ps
CPU time 18.01 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:11:08 PM PDT 24
Peak memory 207948 kb
Host smart-981bdf69-ca2b-426c-872a-aab570dcd6e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490658311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.1490658311
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.344068893
Short name T585
Test name
Test status
Simulation time 160304758 ps
CPU time 3.54 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:10:56 PM PDT 24
Peak memory 199808 kb
Host smart-b30f28ea-a89e-4376-b670-f22215389181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344068893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.344068893
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.1737336612
Short name T213
Test name
Test status
Simulation time 39978789836 ps
CPU time 846.76 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:25:00 PM PDT 24
Peak memory 715012 kb
Host smart-184c360b-34a6-4023-b85e-6f676773a248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1737336612 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.1737336612
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.2650267323
Short name T58
Test name
Test status
Simulation time 1325025070 ps
CPU time 72.33 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:12:04 PM PDT 24
Peak memory 199812 kb
Host smart-6c6e2609-6775-47b9-8ec2-cb5c266cf5fd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650267323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.2650267323
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.2480929724
Short name T305
Test name
Test status
Simulation time 1625699311 ps
CPU time 24.85 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:11:17 PM PDT 24
Peak memory 199852 kb
Host smart-92601214-80df-41ac-a16b-f34bd3eda6f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480929724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.2480929724
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1419865925
Short name T152
Test name
Test status
Simulation time 225819905 ps
CPU time 2.06 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:10:59 PM PDT 24
Peak memory 199752 kb
Host smart-e8a0bf93-6254-47b6-861c-d57c0d860b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419865925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1419865925
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.1023129694
Short name T26
Test name
Test status
Simulation time 78273946 ps
CPU time 0.61 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:10:59 PM PDT 24
Peak memory 195480 kb
Host smart-e2e23a61-c822-4183-b105-02a96b99ff5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023129694 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.1023129694
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.866546814
Short name T260
Test name
Test status
Simulation time 151148262 ps
CPU time 1.44 seconds
Started Jun 13 01:10:48 PM PDT 24
Finished Jun 13 01:10:50 PM PDT 24
Peak memory 199760 kb
Host smart-2f700cbd-841d-4340-9178-f16913019b4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866546814 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.hmac_test_hmac_vectors.866546814
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha_vectors.694334236
Short name T71
Test name
Test status
Simulation time 142512700213 ps
CPU time 494.33 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:19:06 PM PDT 24
Peak memory 199856 kb
Host smart-6e468035-4c5c-4286-b134-784889cce3c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694334236 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha_vectors.694334236
Directory /workspace/27.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.3332275301
Short name T455
Test name
Test status
Simulation time 16380159219 ps
CPU time 106.42 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:12:39 PM PDT 24
Peak memory 199856 kb
Host smart-c33b4522-732d-4ea4-a64c-8a4795c3c542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332275301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.3332275301
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.670991115
Short name T150
Test name
Test status
Simulation time 110092391 ps
CPU time 0.6 seconds
Started Jun 13 01:10:47 PM PDT 24
Finished Jun 13 01:10:48 PM PDT 24
Peak memory 195544 kb
Host smart-265cf6c5-6ec6-468c-b2b6-9868f3c7c1a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670991115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.670991115
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.1024986168
Short name T437
Test name
Test status
Simulation time 4767687712 ps
CPU time 57.81 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:11:56 PM PDT 24
Peak memory 232508 kb
Host smart-ad6ae8fd-22c2-45a4-a3c9-37df8494f19b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1024986168 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.1024986168
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.1590159454
Short name T295
Test name
Test status
Simulation time 3073359229 ps
CPU time 58.86 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:11:51 PM PDT 24
Peak memory 199864 kb
Host smart-f7887306-c704-4c39-a306-1328510a4bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590159454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.1590159454
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1285658254
Short name T296
Test name
Test status
Simulation time 8673963686 ps
CPU time 540.93 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:19:51 PM PDT 24
Peak memory 668144 kb
Host smart-d46e3205-215f-4ff4-a98e-b9ea2389a189
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1285658254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1285658254
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.2998265582
Short name T485
Test name
Test status
Simulation time 25851046097 ps
CPU time 111.36 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:12:45 PM PDT 24
Peak memory 199756 kb
Host smart-8df45344-dc0f-444f-a271-35d9ede0974e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998265582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.2998265582
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.351322441
Short name T583
Test name
Test status
Simulation time 1693108995 ps
CPU time 99.33 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:12:32 PM PDT 24
Peak memory 199748 kb
Host smart-1016ca6f-bb71-4a31-8857-e766b3061ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351322441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.351322441
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.3444063238
Short name T560
Test name
Test status
Simulation time 1254026723 ps
CPU time 7.48 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:11:00 PM PDT 24
Peak memory 199784 kb
Host smart-e3492061-fcf0-442e-9008-a30d3a06c27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444063238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.3444063238
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.746685184
Short name T63
Test name
Test status
Simulation time 2246756084 ps
CPU time 37.03 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:11:35 PM PDT 24
Peak memory 216228 kb
Host smart-fb536459-a053-481d-b8ef-6a2ec4b3b284
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746685184 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.746685184
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.3936355389
Short name T584
Test name
Test status
Simulation time 270464264 ps
CPU time 1.37 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:10:53 PM PDT 24
Peak memory 199828 kb
Host smart-e56af381-64e4-4191-a658-ae6317a27f83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936355389 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.hmac_test_hmac_vectors.3936355389
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha_vectors.3136139810
Short name T427
Test name
Test status
Simulation time 16334627166 ps
CPU time 433.6 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:18:11 PM PDT 24
Peak memory 199864 kb
Host smart-24ce760a-8533-457f-8954-b926c9539d52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136139810 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha_vectors.3136139810
Directory /workspace/28.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.1731097975
Short name T270
Test name
Test status
Simulation time 12377102455 ps
CPU time 93.31 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:12:27 PM PDT 24
Peak memory 199860 kb
Host smart-981bdce0-19f0-4ecb-8bb0-37db26929639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731097975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.1731097975
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.2792098962
Short name T519
Test name
Test status
Simulation time 18425441 ps
CPU time 0.59 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:10:55 PM PDT 24
Peak memory 195400 kb
Host smart-16cd52e2-659f-4ff5-ba0d-93cb2a85a372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792098962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.2792098962
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.2903978988
Short name T470
Test name
Test status
Simulation time 608501602 ps
CPU time 10.35 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:11:02 PM PDT 24
Peak memory 229456 kb
Host smart-a7081378-b4ec-4897-9ca7-f68e5ce983fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2903978988 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.2903978988
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.531024147
Short name T589
Test name
Test status
Simulation time 1400543299 ps
CPU time 18.8 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:11:15 PM PDT 24
Peak memory 199856 kb
Host smart-ca3be127-2f37-455f-8aa6-11450cc03fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531024147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.531024147
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3505715697
Short name T1
Test name
Test status
Simulation time 4192155067 ps
CPU time 207.72 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:14:20 PM PDT 24
Peak memory 458568 kb
Host smart-51ae749c-8fe6-4f00-98f0-958bd6627611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3505715697 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3505715697
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.2172422663
Short name T182
Test name
Test status
Simulation time 1747288375 ps
CPU time 49.22 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:11:46 PM PDT 24
Peak memory 199828 kb
Host smart-04104c46-2290-44df-93a6-1c2fdd4c9e86
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172422663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.2172422663
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.1550993558
Short name T471
Test name
Test status
Simulation time 113627560297 ps
CPU time 166.87 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:13:38 PM PDT 24
Peak memory 199800 kb
Host smart-ea7edc9c-7f6c-4d63-85de-6a72973d023f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550993558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.1550993558
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.3763568542
Short name T230
Test name
Test status
Simulation time 61903446 ps
CPU time 1.52 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:10:57 PM PDT 24
Peak memory 199816 kb
Host smart-b983a178-68ec-4e24-a11c-40dec08aa2d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763568542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.3763568542
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.290932063
Short name T423
Test name
Test status
Simulation time 3926002976386 ps
CPU time 6122.83 seconds
Started Jun 13 01:10:48 PM PDT 24
Finished Jun 13 02:52:52 PM PDT 24
Peak memory 925156 kb
Host smart-429fc1e2-de67-4f6b-a36b-08481d70c373
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290932063 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.290932063
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1983665481
Short name T43
Test name
Test status
Simulation time 64398740 ps
CPU time 1.34 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:10:58 PM PDT 24
Peak memory 199716 kb
Host smart-451a6c1f-e737-4de1-94ee-d3b1e3ee9b06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983665481 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.hmac_test_hmac_vectors.1983665481
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha_vectors.1317060157
Short name T522
Test name
Test status
Simulation time 40457334647 ps
CPU time 514.71 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:19:32 PM PDT 24
Peak memory 199828 kb
Host smart-4b07b520-4a94-45aa-aaa7-b948ad22ec93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317060157 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha_vectors.1317060157
Directory /workspace/29.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.3738633936
Short name T487
Test name
Test status
Simulation time 2814319169 ps
CPU time 53.8 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:11:43 PM PDT 24
Peak memory 199920 kb
Host smart-70ae3873-4264-49a5-a4b7-d154d0a0adac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738633936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.3738633936
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2858582631
Short name T212
Test name
Test status
Simulation time 14837760 ps
CPU time 0.6 seconds
Started Jun 13 01:09:32 PM PDT 24
Finished Jun 13 01:09:33 PM PDT 24
Peak memory 196572 kb
Host smart-80ffa07e-24f2-4e2f-8f2f-667d3d1d93a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858582631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2858582631
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.3703168142
Short name T37
Test name
Test status
Simulation time 509374207 ps
CPU time 24.33 seconds
Started Jun 13 01:09:44 PM PDT 24
Finished Jun 13 01:10:09 PM PDT 24
Peak memory 212592 kb
Host smart-b2c7269c-6741-4d32-83a1-2cefd7eb8679
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3703168142 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.3703168142
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3377212555
Short name T394
Test name
Test status
Simulation time 2178929113 ps
CPU time 19.51 seconds
Started Jun 13 01:09:30 PM PDT 24
Finished Jun 13 01:09:51 PM PDT 24
Peak memory 199860 kb
Host smart-fb8f917d-a897-4f7c-8817-2921428b99f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377212555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3377212555
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1412280525
Short name T396
Test name
Test status
Simulation time 2960492534 ps
CPU time 881.06 seconds
Started Jun 13 01:09:43 PM PDT 24
Finished Jun 13 01:24:25 PM PDT 24
Peak memory 725024 kb
Host smart-6b31e026-6db3-41d9-ac6b-95e7ed6d8f8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1412280525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1412280525
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.1363958833
Short name T524
Test name
Test status
Simulation time 2833122289 ps
CPU time 153.83 seconds
Started Jun 13 01:09:35 PM PDT 24
Finished Jun 13 01:12:10 PM PDT 24
Peak memory 199836 kb
Host smart-6b030fb9-b696-4493-b9dd-e6354cacb5ed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363958833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.1363958833
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1602828692
Short name T398
Test name
Test status
Simulation time 663242553 ps
CPU time 39.03 seconds
Started Jun 13 01:09:32 PM PDT 24
Finished Jun 13 01:10:13 PM PDT 24
Peak memory 199808 kb
Host smart-2ac312d0-510e-4ea6-b091-399be0f0b7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602828692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1602828692
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.847660722
Short name T22
Test name
Test status
Simulation time 666451812 ps
CPU time 0.99 seconds
Started Jun 13 01:09:40 PM PDT 24
Finished Jun 13 01:09:43 PM PDT 24
Peak memory 218268 kb
Host smart-d8b2f234-cd12-4ca8-9f40-b12f6b015f3a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847660722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.847660722
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/3.hmac_smoke.2165613491
Short name T139
Test name
Test status
Simulation time 116456525 ps
CPU time 1.3 seconds
Started Jun 13 01:09:40 PM PDT 24
Finished Jun 13 01:09:43 PM PDT 24
Peak memory 199820 kb
Host smart-c9279777-cc7b-41e8-a6f7-1f5c4a285c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165613491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.2165613491
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.427837038
Short name T60
Test name
Test status
Simulation time 329261446612 ps
CPU time 3480.84 seconds
Started Jun 13 01:09:29 PM PDT 24
Finished Jun 13 02:07:32 PM PDT 24
Peak memory 806132 kb
Host smart-4b7f168f-bf73-4a08-be5d-208a677d6a8f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427837038 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.427837038
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.139213279
Short name T383
Test name
Test status
Simulation time 334943819 ps
CPU time 1.1 seconds
Started Jun 13 01:09:33 PM PDT 24
Finished Jun 13 01:09:36 PM PDT 24
Peak memory 199608 kb
Host smart-3db5847d-5629-4c3a-a343-9edacf68714e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139213279 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.hmac_test_hmac_vectors.139213279
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha_vectors.248793875
Short name T431
Test name
Test status
Simulation time 139724467171 ps
CPU time 500.68 seconds
Started Jun 13 01:09:37 PM PDT 24
Finished Jun 13 01:17:59 PM PDT 24
Peak memory 199852 kb
Host smart-df34c50c-c824-4b15-9045-1705eece6337
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248793875 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha_vectors.248793875
Directory /workspace/3.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1519025591
Short name T407
Test name
Test status
Simulation time 3692674526 ps
CPU time 36.35 seconds
Started Jun 13 01:09:50 PM PDT 24
Finished Jun 13 01:10:27 PM PDT 24
Peak memory 199908 kb
Host smart-5bd709de-b730-4311-be0c-bc6b24564c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519025591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1519025591
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.3278578462
Short name T472
Test name
Test status
Simulation time 27404499 ps
CPU time 0.59 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:10:59 PM PDT 24
Peak memory 195640 kb
Host smart-45cc1422-8045-434c-9fb6-0d9e62b86a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278578462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.3278578462
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.4063907144
Short name T392
Test name
Test status
Simulation time 291348213 ps
CPU time 4.5 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:10:56 PM PDT 24
Peak memory 199888 kb
Host smart-e46f4aeb-5396-4ff0-830a-ec01ade362dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4063907144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.4063907144
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1256731410
Short name T112
Test name
Test status
Simulation time 1294310312 ps
CPU time 27.14 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:11:23 PM PDT 24
Peak memory 199804 kb
Host smart-4efbc2c2-ca65-4a81-8490-a7b14a4a85bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256731410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1256731410
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.4091131281
Short name T277
Test name
Test status
Simulation time 3583235742 ps
CPU time 942.56 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:26:36 PM PDT 24
Peak memory 697412 kb
Host smart-7f04f77e-ff65-44c2-b44a-f7165e2ba74e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091131281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.4091131281
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.3819662941
Short name T514
Test name
Test status
Simulation time 8754572575 ps
CPU time 70.89 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:12:08 PM PDT 24
Peak memory 199840 kb
Host smart-99a50ae7-edb8-4beb-83fc-6d4959f1bccd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819662941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.3819662941
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1963066592
Short name T507
Test name
Test status
Simulation time 443018456 ps
CPU time 7.03 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:11:01 PM PDT 24
Peak memory 199780 kb
Host smart-39f7f9b7-3028-4aea-8dd2-1a2dfcc7669d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963066592 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1963066592
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.1076426636
Short name T69
Test name
Test status
Simulation time 170553882 ps
CPU time 5.61 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:10:58 PM PDT 24
Peak memory 199812 kb
Host smart-71cc2a2d-f9f9-41b4-8fae-dbf723658688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076426636 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.1076426636
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.964626948
Short name T59
Test name
Test status
Simulation time 308027481837 ps
CPU time 2527.78 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:53:07 PM PDT 24
Peak memory 671084 kb
Host smart-506b11a7-c47b-4877-8baa-28a35432a394
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964626948 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.964626948
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.3149675392
Short name T120
Test name
Test status
Simulation time 124925429 ps
CPU time 1.37 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:10:57 PM PDT 24
Peak memory 199788 kb
Host smart-306cb398-3eed-45ad-b108-b6737ec5fa7a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149675392 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.hmac_test_hmac_vectors.3149675392
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha_vectors.1342786077
Short name T342
Test name
Test status
Simulation time 46005569880 ps
CPU time 446.29 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:18:25 PM PDT 24
Peak memory 199844 kb
Host smart-e0dc6455-02cc-4921-83e7-89192c9d14dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342786077 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha_vectors.1342786077
Directory /workspace/30.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2961958883
Short name T482
Test name
Test status
Simulation time 12694562408 ps
CPU time 67.26 seconds
Started Jun 13 01:10:57 PM PDT 24
Finished Jun 13 01:12:08 PM PDT 24
Peak memory 199916 kb
Host smart-424496b9-f295-4059-873a-ddc417432b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961958883 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2961958883
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.2561473571
Short name T18
Test name
Test status
Simulation time 14561404 ps
CPU time 0.67 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:04 PM PDT 24
Peak memory 194824 kb
Host smart-8adaff0f-04e1-4fc9-8b36-c4e48ca23098
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561473571 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.2561473571
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.2593960623
Short name T490
Test name
Test status
Simulation time 425340723 ps
CPU time 23.37 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:11:21 PM PDT 24
Peak memory 216140 kb
Host smart-e8187c78-4cd8-4979-adde-1db44a3c8084
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593960623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.2593960623
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.2052451146
Short name T259
Test name
Test status
Simulation time 3103451447 ps
CPU time 19.77 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:11:19 PM PDT 24
Peak memory 199880 kb
Host smart-1d93c460-5bd7-4bde-a914-b3ee0352f04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052451146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.2052451146
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.1432058076
Short name T389
Test name
Test status
Simulation time 20267280226 ps
CPU time 800.64 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:24:20 PM PDT 24
Peak memory 727852 kb
Host smart-cfede0f7-d0c8-42bf-bb24-67db29e48f0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1432058076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.1432058076
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3020859062
Short name T430
Test name
Test status
Simulation time 3200115491 ps
CPU time 56.27 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:11:55 PM PDT 24
Peak memory 199976 kb
Host smart-00991747-8cc1-415f-b186-324f27ddc1d9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020859062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3020859062
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.738949584
Short name T498
Test name
Test status
Simulation time 1561581803 ps
CPU time 22.1 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:11:19 PM PDT 24
Peak memory 199804 kb
Host smart-a8b6c293-1cc2-4c86-af17-f5f582deb962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738949584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.738949584
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4272693705
Short name T554
Test name
Test status
Simulation time 510311933 ps
CPU time 5.23 seconds
Started Jun 13 01:10:57 PM PDT 24
Finished Jun 13 01:11:06 PM PDT 24
Peak memory 199812 kb
Host smart-4c1d4222-7b11-4d02-84e6-f95ca2cceebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272693705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4272693705
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3940014712
Short name T27
Test name
Test status
Simulation time 36877545990 ps
CPU time 343.25 seconds
Started Jun 13 01:10:58 PM PDT 24
Finished Jun 13 01:16:45 PM PDT 24
Peak memory 199900 kb
Host smart-217fb1ae-6a74-4a73-a407-6f6a9cb41ec0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940014712 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3940014712
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.3878856009
Short name T241
Test name
Test status
Simulation time 498463351 ps
CPU time 1.37 seconds
Started Jun 13 01:10:56 PM PDT 24
Finished Jun 13 01:11:01 PM PDT 24
Peak memory 199840 kb
Host smart-f9b893a3-154e-45e3-a5da-adc277700342
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878856009 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.hmac_test_hmac_vectors.3878856009
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha_vectors.3446261514
Short name T320
Test name
Test status
Simulation time 17259022795 ps
CPU time 477.78 seconds
Started Jun 13 01:10:57 PM PDT 24
Finished Jun 13 01:19:00 PM PDT 24
Peak memory 199852 kb
Host smart-2d5c5fc3-3e4c-406e-abed-b70573a8f45d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446261514 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha_vectors.3446261514
Directory /workspace/31.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.2451931914
Short name T126
Test name
Test status
Simulation time 6033940124 ps
CPU time 45.7 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:11:45 PM PDT 24
Peak memory 199840 kb
Host smart-94ba92cb-1536-44cb-b805-a9a3b2f99bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451931914 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.2451931914
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.3258935846
Short name T564
Test name
Test status
Simulation time 36483719 ps
CPU time 0.58 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:08 PM PDT 24
Peak memory 195816 kb
Host smart-ea19b24c-2a22-43e1-beb0-90c0edf678d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258935846 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.3258935846
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.141953564
Short name T411
Test name
Test status
Simulation time 1352747536 ps
CPU time 34.59 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:38 PM PDT 24
Peak memory 225428 kb
Host smart-d7ebc5b5-485a-4386-9d20-d6ed78f0a1e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=141953564 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.141953564
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1023674871
Short name T416
Test name
Test status
Simulation time 8776446716 ps
CPU time 48.17 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:52 PM PDT 24
Peak memory 199860 kb
Host smart-15e1a674-4609-4f9c-8337-83333cc90c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023674871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1023674871
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.1345498480
Short name T359
Test name
Test status
Simulation time 2051709513 ps
CPU time 328.71 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:16:39 PM PDT 24
Peak memory 663248 kb
Host smart-11d0972c-8c96-43b8-ab06-10d2417073ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345498480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.1345498480
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3412699631
Short name T546
Test name
Test status
Simulation time 16953380920 ps
CPU time 76.9 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:12:27 PM PDT 24
Peak memory 199508 kb
Host smart-2f9846c2-84d6-428a-8e52-21fd4b8f7d1f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412699631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3412699631
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.625004492
Short name T294
Test name
Test status
Simulation time 429262047 ps
CPU time 27.05 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:31 PM PDT 24
Peak memory 199784 kb
Host smart-a96f5884-0454-4fa3-ad8e-c81848cae508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625004492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.625004492
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.2643735692
Short name T141
Test name
Test status
Simulation time 877343319 ps
CPU time 4.23 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:11:08 PM PDT 24
Peak memory 199784 kb
Host smart-9fffdf71-8126-48c9-8ede-d07a427a63d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643735692 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.2643735692
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_stress_all.11019786
Short name T535
Test name
Test status
Simulation time 260063252670 ps
CPU time 1590.24 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:37:41 PM PDT 24
Peak memory 763800 kb
Host smart-6deedb88-0c13-4db2-acb8-445dcf07d856
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11019786 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.11019786
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.297305074
Short name T563
Test name
Test status
Simulation time 56778785 ps
CPU time 1.2 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:11:07 PM PDT 24
Peak memory 199776 kb
Host smart-8ad84ccf-cba7-4a21-8ba4-adae2f04d372
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297305074 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.hmac_test_hmac_vectors.297305074
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha_vectors.1943948863
Short name T552
Test name
Test status
Simulation time 155684843781 ps
CPU time 489.87 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:19:13 PM PDT 24
Peak memory 199936 kb
Host smart-58d2f665-81f3-4b7e-83df-2995237eac8b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943948863 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha_vectors.1943948863
Directory /workspace/32.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.949633947
Short name T220
Test name
Test status
Simulation time 9267644056 ps
CPU time 67.56 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:12:12 PM PDT 24
Peak memory 199928 kb
Host smart-0bb32496-de65-492c-84a5-71962d987147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949633947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.949633947
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.2090462446
Short name T314
Test name
Test status
Simulation time 29913321 ps
CPU time 0.55 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:10:50 PM PDT 24
Peak memory 194804 kb
Host smart-99aeb1a3-4919-440e-8112-62e18e8c1cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090462446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.2090462446
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3219817433
Short name T424
Test name
Test status
Simulation time 593718633 ps
CPU time 30.41 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:39 PM PDT 24
Peak memory 216088 kb
Host smart-c25faaea-4381-4d84-a1ca-58f5ffdcddfa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3219817433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3219817433
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1587559620
Short name T566
Test name
Test status
Simulation time 4151546088 ps
CPU time 47.47 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:55 PM PDT 24
Peak memory 199868 kb
Host smart-9c16328b-8ee3-4e67-b15c-7bffa632e653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587559620 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1587559620
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1121962327
Short name T136
Test name
Test status
Simulation time 7363324458 ps
CPU time 441.57 seconds
Started Jun 13 01:11:04 PM PDT 24
Finished Jun 13 01:18:31 PM PDT 24
Peak memory 689412 kb
Host smart-ea57b79f-e6dc-4bec-967f-52a54e5d4855
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121962327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1121962327
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.2867957731
Short name T209
Test name
Test status
Simulation time 2315124933 ps
CPU time 135.46 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:13:24 PM PDT 24
Peak memory 199852 kb
Host smart-3eabc403-8efd-4a22-8f36-f4e9c5f3139d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867957731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.2867957731
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_smoke.1079282506
Short name T408
Test name
Test status
Simulation time 722334317 ps
CPU time 8.3 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:17 PM PDT 24
Peak memory 199836 kb
Host smart-96814fc6-dd58-40f8-80c6-e7d42d5c56e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079282506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1079282506
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.1619086906
Short name T302
Test name
Test status
Simulation time 4670899391 ps
CPU time 867.18 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:25:18 PM PDT 24
Peak memory 735844 kb
Host smart-19f49b8f-6c56-4a96-8b33-301069088842
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619086906 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.1619086906
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.2427880707
Short name T252
Test name
Test status
Simulation time 108986353 ps
CPU time 1.06 seconds
Started Jun 13 01:11:02 PM PDT 24
Finished Jun 13 01:11:08 PM PDT 24
Peak memory 199800 kb
Host smart-e4eda2b8-aeab-45f6-9411-96df73d8a93a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427880707 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.hmac_test_hmac_vectors.2427880707
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha_vectors.323556892
Short name T447
Test name
Test status
Simulation time 61167597752 ps
CPU time 547.02 seconds
Started Jun 13 01:10:58 PM PDT 24
Finished Jun 13 01:20:09 PM PDT 24
Peak memory 199824 kb
Host smart-74029b0c-35b8-4e66-8614-4937cbc9fbcf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323556892 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha_vectors.323556892
Directory /workspace/33.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.2371094312
Short name T4
Test name
Test status
Simulation time 1096853480 ps
CPU time 50.69 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:59 PM PDT 24
Peak memory 199664 kb
Host smart-af299608-45e1-45dc-9858-695fdb709623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371094312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.2371094312
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.824632468
Short name T20
Test name
Test status
Simulation time 29453196 ps
CPU time 0.57 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:10:59 PM PDT 24
Peak memory 195416 kb
Host smart-6a850b4a-9cc7-4f7d-b2be-5aad991df4c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824632468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.824632468
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.2183881232
Short name T155
Test name
Test status
Simulation time 1434443461 ps
CPU time 14.99 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:11:05 PM PDT 24
Peak memory 199788 kb
Host smart-621ab03a-3a62-4250-a93e-f33f60b422e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183881232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.2183881232
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.199320046
Short name T538
Test name
Test status
Simulation time 1986199586 ps
CPU time 9.42 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:11:01 PM PDT 24
Peak memory 199712 kb
Host smart-e3a04d1f-5f01-4661-ac8b-c9f9dc10c853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199320046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.199320046
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.3024845989
Short name T441
Test name
Test status
Simulation time 15414474558 ps
CPU time 1292.06 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:32:27 PM PDT 24
Peak memory 715604 kb
Host smart-673c9857-ac72-43b4-9e41-2f177d20a300
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024845989 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.3024845989
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3683930712
Short name T180
Test name
Test status
Simulation time 1996873352 ps
CPU time 37.72 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:11:32 PM PDT 24
Peak memory 199784 kb
Host smart-ff5ae1bd-281b-4a08-ab7e-e13c7b5a8f3f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683930712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3683930712
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.3324498766
Short name T477
Test name
Test status
Simulation time 489759049 ps
CPU time 15 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:11:12 PM PDT 24
Peak memory 199804 kb
Host smart-55085948-e3a6-453b-89d4-bcd45c7c98e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324498766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.3324498766
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.2193110526
Short name T41
Test name
Test status
Simulation time 1118930668 ps
CPU time 5.45 seconds
Started Jun 13 01:11:04 PM PDT 24
Finished Jun 13 01:11:14 PM PDT 24
Peak memory 199704 kb
Host smart-3b3692a0-700d-4b18-b68f-b344a9d5c9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193110526 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.2193110526
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.1886778606
Short name T62
Test name
Test status
Simulation time 240660951242 ps
CPU time 1854.86 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:41:52 PM PDT 24
Peak memory 706080 kb
Host smart-60f462ed-1d9b-4ebf-93b1-e298c63c5733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886778606 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.1886778606
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.2935085247
Short name T421
Test name
Test status
Simulation time 47180449 ps
CPU time 1.15 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:10:52 PM PDT 24
Peak memory 199704 kb
Host smart-d64c3b7d-502c-4261-b53f-827ef8b02638
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935085247 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.hmac_test_hmac_vectors.2935085247
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha_vectors.2414987642
Short name T303
Test name
Test status
Simulation time 7723689851 ps
CPU time 418.78 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:17:55 PM PDT 24
Peak memory 199852 kb
Host smart-1248ebbb-ddad-40c3-ac1d-7e3650dbb1a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414987642 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha_vectors.2414987642
Directory /workspace/34.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.3696025653
Short name T565
Test name
Test status
Simulation time 11304866243 ps
CPU time 92.9 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:12:32 PM PDT 24
Peak memory 199856 kb
Host smart-c51e0bd3-b68f-489c-9fca-c98225e4714d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696025653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.3696025653
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2964511192
Short name T163
Test name
Test status
Simulation time 42571085 ps
CPU time 0.57 seconds
Started Jun 13 01:10:56 PM PDT 24
Finished Jun 13 01:11:01 PM PDT 24
Peak memory 195856 kb
Host smart-2579196a-00bd-419b-a629-35bf8ea45e3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964511192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2964511192
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.2533421652
Short name T567
Test name
Test status
Simulation time 1731094231 ps
CPU time 15.93 seconds
Started Jun 13 01:10:57 PM PDT 24
Finished Jun 13 01:11:17 PM PDT 24
Peak memory 199848 kb
Host smart-72768441-1134-43db-ac7a-585f83b1cd66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2533421652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.2533421652
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.2288543971
Short name T454
Test name
Test status
Simulation time 4054390933 ps
CPU time 32.23 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:11:31 PM PDT 24
Peak memory 199852 kb
Host smart-6efa96c4-e71f-40bd-9411-6dbcdfe4f2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288543971 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.2288543971
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1656763324
Short name T537
Test name
Test status
Simulation time 1461005045 ps
CPU time 387.04 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:17:25 PM PDT 24
Peak memory 677588 kb
Host smart-9b1a9155-09bd-43ad-a52f-0668603d5d04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1656763324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1656763324
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1912640563
Short name T516
Test name
Test status
Simulation time 6101594974 ps
CPU time 78.04 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:12:17 PM PDT 24
Peak memory 199856 kb
Host smart-cf814b7b-6475-4308-a6a9-8f7fdd2e44c7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912640563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1912640563
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.509260200
Short name T217
Test name
Test status
Simulation time 6018883450 ps
CPU time 112.56 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:12:48 PM PDT 24
Peak memory 199848 kb
Host smart-01ef5cf9-1762-436f-8264-2de98db9e6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509260200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.509260200
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.2229837048
Short name T452
Test name
Test status
Simulation time 223109113 ps
CPU time 4.59 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:11:03 PM PDT 24
Peak memory 199720 kb
Host smart-58308e98-b4e8-43bd-b496-6f3a4e00ed29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229837048 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.2229837048
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_stress_all.889247719
Short name T556
Test name
Test status
Simulation time 22453940978 ps
CPU time 310.11 seconds
Started Jun 13 01:10:56 PM PDT 24
Finished Jun 13 01:16:10 PM PDT 24
Peak memory 216288 kb
Host smart-bc2be694-f70b-4d81-b964-073892b3b354
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889247719 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 35.hmac_stress_all.889247719
Directory /workspace/35.hmac_stress_all/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.1114063763
Short name T355
Test name
Test status
Simulation time 80083717 ps
CPU time 1.59 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:10:56 PM PDT 24
Peak memory 199780 kb
Host smart-b207ab49-36fa-499e-b352-b2b95325142e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114063763 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.hmac_test_hmac_vectors.1114063763
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha_vectors.1564178570
Short name T504
Test name
Test status
Simulation time 96284183386 ps
CPU time 411.62 seconds
Started Jun 13 01:10:56 PM PDT 24
Finished Jun 13 01:17:52 PM PDT 24
Peak memory 199844 kb
Host smart-4807c812-cf3c-4ecf-bd7b-38da5b0d311d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564178570 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha_vectors.1564178570
Directory /workspace/35.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.1570318161
Short name T281
Test name
Test status
Simulation time 10980181409 ps
CPU time 69.13 seconds
Started Jun 13 01:10:57 PM PDT 24
Finished Jun 13 01:12:10 PM PDT 24
Peak memory 199888 kb
Host smart-117149d1-5319-4a5f-9f8c-ddf4a8c62245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570318161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.1570318161
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1701750835
Short name T208
Test name
Test status
Simulation time 19751207 ps
CPU time 0.58 seconds
Started Jun 13 01:11:01 PM PDT 24
Finished Jun 13 01:11:07 PM PDT 24
Peak memory 194992 kb
Host smart-d80ccf92-efe7-4881-a6a4-3078edbb86b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701750835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1701750835
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.581734020
Short name T257
Test name
Test status
Simulation time 723364703 ps
CPU time 8.34 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:11:14 PM PDT 24
Peak memory 208012 kb
Host smart-a4cb2428-f76e-4497-8472-1d575cfaf117
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=581734020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.581734020
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.2896463916
Short name T93
Test name
Test status
Simulation time 19143510649 ps
CPU time 72.46 seconds
Started Jun 13 01:11:24 PM PDT 24
Finished Jun 13 01:12:38 PM PDT 24
Peak memory 199876 kb
Host smart-09a67a8f-9ccb-4167-953f-3da181c0dbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896463916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.2896463916
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.3979986171
Short name T121
Test name
Test status
Simulation time 1081235259 ps
CPU time 101.27 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:12:45 PM PDT 24
Peak memory 406936 kb
Host smart-e2f669c8-29b1-4d41-9cae-5dea0515d2a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3979986171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.3979986171
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1915667077
Short name T16
Test name
Test status
Simulation time 19291889010 ps
CPU time 125.02 seconds
Started Jun 13 01:11:02 PM PDT 24
Finished Jun 13 01:13:11 PM PDT 24
Peak memory 199832 kb
Host smart-73eda3f1-84b6-4fde-9d0a-1dcea5fe3ae2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915667077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1915667077
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_smoke.1223917030
Short name T183
Test name
Test status
Simulation time 487764071 ps
CPU time 2.28 seconds
Started Jun 13 01:10:58 PM PDT 24
Finished Jun 13 01:11:04 PM PDT 24
Peak memory 199832 kb
Host smart-a2b9bf1a-8a3b-4c47-b7f6-c3e8a3f7624c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223917030 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.1223917030
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3071512331
Short name T61
Test name
Test status
Simulation time 535293686331 ps
CPU time 2389.69 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:51:00 PM PDT 24
Peak memory 774392 kb
Host smart-1a917fe1-6a74-4874-a5a5-cfa765a08c1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071512331 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3071512331
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_stress_all_with_rand_reset.1588767672
Short name T49
Test name
Test status
Simulation time 22085014502 ps
CPU time 1873.69 seconds
Started Jun 13 01:11:04 PM PDT 24
Finished Jun 13 01:42:23 PM PDT 24
Peak memory 776924 kb
Host smart-db3314a9-3b8d-4e6b-9bd6-73b0cd1f13ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588767672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all_with_rand_reset.1588767672
Directory /workspace/36.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.1489778083
Short name T214
Test name
Test status
Simulation time 31372542 ps
CPU time 1.24 seconds
Started Jun 13 01:11:02 PM PDT 24
Finished Jun 13 01:11:09 PM PDT 24
Peak memory 199792 kb
Host smart-942107a1-b5df-489d-b656-bd5a2fa50c40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489778083 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.hmac_test_hmac_vectors.1489778083
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha_vectors.3744326553
Short name T187
Test name
Test status
Simulation time 15274497597 ps
CPU time 421.14 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:18:09 PM PDT 24
Peak memory 199892 kb
Host smart-4f823fe7-eea9-4af1-99a1-ef7188e625da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744326553 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha_vectors.3744326553
Directory /workspace/36.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1995416457
Short name T426
Test name
Test status
Simulation time 2526311416 ps
CPU time 34.85 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:42 PM PDT 24
Peak memory 199916 kb
Host smart-3f631c86-cd05-4a4e-bb9f-53edca1f299b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995416457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1995416457
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.4217933481
Short name T309
Test name
Test status
Simulation time 39779070 ps
CPU time 0.58 seconds
Started Jun 13 01:10:56 PM PDT 24
Finished Jun 13 01:11:00 PM PDT 24
Peak memory 195464 kb
Host smart-07a5cbf1-c5a9-43d1-b714-14aadaca8130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217933481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.4217933481
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.4202241992
Short name T33
Test name
Test status
Simulation time 1102475091 ps
CPU time 47.7 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:56 PM PDT 24
Peak memory 207972 kb
Host smart-ad3eec7e-d747-48b8-9ee6-576266df206f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4202241992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.4202241992
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.3430912317
Short name T329
Test name
Test status
Simulation time 4801694747 ps
CPU time 72 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:12:22 PM PDT 24
Peak memory 199644 kb
Host smart-7fe84db6-7338-4c04-888a-1a146b575d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430912317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.3430912317
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2224125209
Short name T188
Test name
Test status
Simulation time 8381405029 ps
CPU time 699.18 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:22:47 PM PDT 24
Peak memory 676236 kb
Host smart-d31eaf71-e09e-447c-9e7a-6f27cf5449ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2224125209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2224125209
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2792666861
Short name T428
Test name
Test status
Simulation time 4040579117 ps
CPU time 103.97 seconds
Started Jun 13 01:10:57 PM PDT 24
Finished Jun 13 01:12:45 PM PDT 24
Peak memory 199900 kb
Host smart-8c1e948f-e6e3-4936-8d0f-63e36571f468
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792666861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2792666861
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.4231856100
Short name T515
Test name
Test status
Simulation time 1669242026 ps
CPU time 8.33 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:17 PM PDT 24
Peak memory 199532 kb
Host smart-9409b8b6-02af-4418-8bfd-cd9f00210f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231856100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.4231856100
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.23624709
Short name T274
Test name
Test status
Simulation time 54742255 ps
CPU time 1.23 seconds
Started Jun 13 01:11:04 PM PDT 24
Finished Jun 13 01:11:10 PM PDT 24
Peak memory 199772 kb
Host smart-25cba979-c2bb-4b8b-9295-4e9f6d26e746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23624709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.23624709
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_stress_all.2675980868
Short name T361
Test name
Test status
Simulation time 34898572092 ps
CPU time 891.06 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:25:59 PM PDT 24
Peak memory 676724 kb
Host smart-1887c264-3c82-4410-9d45-75c5465cf7ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675980868 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.2675980868
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.1156935067
Short name T168
Test name
Test status
Simulation time 298074494 ps
CPU time 1.13 seconds
Started Jun 13 01:10:54 PM PDT 24
Finished Jun 13 01:10:59 PM PDT 24
Peak memory 199696 kb
Host smart-0fb3b993-9cb8-4b53-9294-dadd5c0cf2da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156935067 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 37.hmac_test_hmac_vectors.1156935067
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha_vectors.445036892
Short name T318
Test name
Test status
Simulation time 34492637018 ps
CPU time 501.38 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:19:30 PM PDT 24
Peak memory 199856 kb
Host smart-6dfb563c-92c6-4f0b-803c-a3b1428b2ba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445036892 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha_vectors.445036892
Directory /workspace/37.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.3268474778
Short name T481
Test name
Test status
Simulation time 30424841414 ps
CPU time 76.54 seconds
Started Jun 13 01:11:04 PM PDT 24
Finished Jun 13 01:12:25 PM PDT 24
Peak memory 199836 kb
Host smart-5b2f54ab-c6c1-487c-937a-a5ea5759bc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268474778 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.3268474778
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.1354960920
Short name T365
Test name
Test status
Simulation time 49079566 ps
CPU time 0.59 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:10:50 PM PDT 24
Peak memory 196592 kb
Host smart-5c1c97f1-46cb-472a-aae2-823fd16cbf4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354960920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.1354960920
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.740074194
Short name T161
Test name
Test status
Simulation time 89240697 ps
CPU time 3.59 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:10:58 PM PDT 24
Peak memory 199700 kb
Host smart-7c8f3797-f324-4edc-932a-d309bb831565
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=740074194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.740074194
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.631720913
Short name T479
Test name
Test status
Simulation time 397263998 ps
CPU time 22.7 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:11:21 PM PDT 24
Peak memory 199856 kb
Host smart-ad11173f-b7ad-4aa6-921e-193a9468b75a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631720913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.631720913
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.2924623041
Short name T484
Test name
Test status
Simulation time 1772594788 ps
CPU time 110.09 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:12:44 PM PDT 24
Peak memory 432884 kb
Host smart-c83480e6-7031-43b2-b271-593030ab2909
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924623041 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.2924623041
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.765951675
Short name T354
Test name
Test status
Simulation time 21936326256 ps
CPU time 98.1 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:12:30 PM PDT 24
Peak memory 199892 kb
Host smart-a4aa3f42-c5e7-4145-8f5a-24aadd4ff731
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765951675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.765951675
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.1831877821
Short name T506
Test name
Test status
Simulation time 3095382420 ps
CPU time 31.06 seconds
Started Jun 13 01:11:05 PM PDT 24
Finished Jun 13 01:11:41 PM PDT 24
Peak memory 199888 kb
Host smart-ebb6be4b-1e09-4f08-a53c-03678ab978dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831877821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.1831877821
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.986649959
Short name T379
Test name
Test status
Simulation time 92228126 ps
CPU time 3.24 seconds
Started Jun 13 01:11:05 PM PDT 24
Finished Jun 13 01:11:13 PM PDT 24
Peak memory 199772 kb
Host smart-48d6b5b4-78d8-438f-a42a-c3d0d8b91c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986649959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.986649959
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.663359963
Short name T386
Test name
Test status
Simulation time 180534450462 ps
CPU time 623.02 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:21:19 PM PDT 24
Peak memory 216244 kb
Host smart-d5e0ac78-242f-445c-aa37-2e676d60c437
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663359963 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.663359963
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2776493857
Short name T226
Test name
Test status
Simulation time 426214762 ps
CPU time 1.39 seconds
Started Jun 13 01:10:49 PM PDT 24
Finished Jun 13 01:10:53 PM PDT 24
Peak memory 199748 kb
Host smart-9975f3d6-d09d-45b6-80a1-4107b8620072
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776493857 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.hmac_test_hmac_vectors.2776493857
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha_vectors.2926657473
Short name T570
Test name
Test status
Simulation time 7157640812 ps
CPU time 409.04 seconds
Started Jun 13 01:10:47 PM PDT 24
Finished Jun 13 01:17:37 PM PDT 24
Peak memory 199880 kb
Host smart-4b720f76-1a29-4ddb-baec-a1f4b95428d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926657473 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha_vectors.2926657473
Directory /workspace/38.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.726768084
Short name T332
Test name
Test status
Simulation time 85554390 ps
CPU time 2.95 seconds
Started Jun 13 01:10:51 PM PDT 24
Finished Jun 13 01:10:56 PM PDT 24
Peak memory 199656 kb
Host smart-031a1afc-4457-4621-9f30-b221fe68804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726768084 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.726768084
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.2022207094
Short name T218
Test name
Test status
Simulation time 14182401 ps
CPU time 0.6 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:09 PM PDT 24
Peak memory 196576 kb
Host smart-ffdfece8-d668-4907-8aae-29b48318bca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022207094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.2022207094
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1391944606
Short name T186
Test name
Test status
Simulation time 617027751 ps
CPU time 34.71 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:11:28 PM PDT 24
Peak memory 248076 kb
Host smart-5ae05796-88a9-4dff-a585-7f5b28da47b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1391944606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1391944606
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.2414360848
Short name T582
Test name
Test status
Simulation time 112726669032 ps
CPU time 109.44 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:12:46 PM PDT 24
Peak memory 199864 kb
Host smart-faad62b7-4ddd-4d37-9e02-5b1f3f0a7a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414360848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.2414360848
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.1833889584
Short name T185
Test name
Test status
Simulation time 6347420620 ps
CPU time 976.61 seconds
Started Jun 13 01:10:50 PM PDT 24
Finished Jun 13 01:27:09 PM PDT 24
Peak memory 774080 kb
Host smart-0a80ded3-8c52-4bc4-9a9c-42dafcada4ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833889584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.1833889584
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.362647415
Short name T15
Test name
Test status
Simulation time 17131272586 ps
CPU time 153.23 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:13:30 PM PDT 24
Peak memory 199836 kb
Host smart-a7c94193-e5ff-4797-b43e-d921df25c203
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362647415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.362647415
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.4223312899
Short name T129
Test name
Test status
Simulation time 1079011906 ps
CPU time 52.97 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:11:49 PM PDT 24
Peak memory 199832 kb
Host smart-addc0565-434c-42b7-8d06-d0a1ef70c59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223312899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.4223312899
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.1027238319
Short name T45
Test name
Test status
Simulation time 98573622 ps
CPU time 3.48 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:10:59 PM PDT 24
Peak memory 199784 kb
Host smart-640366b6-af82-4029-b9ff-93c9dea9a901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027238319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.1027238319
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.3858059672
Short name T148
Test name
Test status
Simulation time 110728949136 ps
CPU time 1536.69 seconds
Started Jun 13 01:10:56 PM PDT 24
Finished Jun 13 01:36:37 PM PDT 24
Peak memory 223448 kb
Host smart-50cbe417-b9bc-4e3c-992d-364a2129b1f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858059672 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.3858059672
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.2947696678
Short name T243
Test name
Test status
Simulation time 80194203 ps
CPU time 1.37 seconds
Started Jun 13 01:10:53 PM PDT 24
Finished Jun 13 01:10:58 PM PDT 24
Peak memory 199780 kb
Host smart-b2fc7132-2282-499e-846b-da3ce6799fb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947696678 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.hmac_test_hmac_vectors.2947696678
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha_vectors.2610064848
Short name T135
Test name
Test status
Simulation time 30894993935 ps
CPU time 428.82 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:18:08 PM PDT 24
Peak memory 199868 kb
Host smart-ad94e3db-2deb-42e2-a421-b92fe5d80ed2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610064848 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha_vectors.2610064848
Directory /workspace/39.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.4147857240
Short name T400
Test name
Test status
Simulation time 8368203302 ps
CPU time 86.7 seconds
Started Jun 13 01:10:56 PM PDT 24
Finished Jun 13 01:12:27 PM PDT 24
Peak memory 199852 kb
Host smart-1e5d843f-0785-4797-b10d-f598dc76740d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147857240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.4147857240
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.178067271
Short name T304
Test name
Test status
Simulation time 11102939 ps
CPU time 0.6 seconds
Started Jun 13 01:09:50 PM PDT 24
Finished Jun 13 01:09:52 PM PDT 24
Peak memory 195468 kb
Host smart-e7332cef-6cec-45e9-b468-f1939c66983f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178067271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.178067271
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.884284337
Short name T238
Test name
Test status
Simulation time 1291148313 ps
CPU time 18.4 seconds
Started Jun 13 01:09:46 PM PDT 24
Finished Jun 13 01:10:05 PM PDT 24
Peak memory 199780 kb
Host smart-25f00c4e-643f-4c8a-b862-2740e0655683
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=884284337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.884284337
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.4076832799
Short name T88
Test name
Test status
Simulation time 2623091454 ps
CPU time 38.14 seconds
Started Jun 13 01:09:30 PM PDT 24
Finished Jun 13 01:10:09 PM PDT 24
Peak memory 199912 kb
Host smart-d75b6221-1c05-4aba-9391-c1bfe39e8d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076832799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.4076832799
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.549196783
Short name T253
Test name
Test status
Simulation time 1307933065 ps
CPU time 35.22 seconds
Started Jun 13 01:09:41 PM PDT 24
Finished Jun 13 01:10:18 PM PDT 24
Peak memory 239892 kb
Host smart-743f8857-cd90-4f96-b41b-27796b77ce99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=549196783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.549196783
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.1564792657
Short name T14
Test name
Test status
Simulation time 24881048448 ps
CPU time 79.82 seconds
Started Jun 13 01:09:38 PM PDT 24
Finished Jun 13 01:10:58 PM PDT 24
Peak memory 199820 kb
Host smart-7bf0b2c8-98a3-4924-ad05-49835f04acb4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564792657 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.1564792657
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.1469965920
Short name T557
Test name
Test status
Simulation time 928280162 ps
CPU time 57.17 seconds
Started Jun 13 01:09:37 PM PDT 24
Finished Jun 13 01:10:35 PM PDT 24
Peak memory 199724 kb
Host smart-364d2e72-18b2-46e9-8378-90386c902ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469965920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.1469965920
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.3318475501
Short name T28
Test name
Test status
Simulation time 997366228 ps
CPU time 1.19 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:09:49 PM PDT 24
Peak memory 219232 kb
Host smart-2f41d5db-8b40-4985-bee5-0d17cc449d5a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318475501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.3318475501
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.2767238456
Short name T503
Test name
Test status
Simulation time 500075891 ps
CPU time 5.58 seconds
Started Jun 13 01:09:40 PM PDT 24
Finished Jun 13 01:09:47 PM PDT 24
Peak memory 199724 kb
Host smart-12ef1d21-c552-4141-9680-a90146e07a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767238456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.2767238456
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3984317612
Short name T544
Test name
Test status
Simulation time 167979732 ps
CPU time 1.19 seconds
Started Jun 13 01:09:31 PM PDT 24
Finished Jun 13 01:09:33 PM PDT 24
Peak memory 199768 kb
Host smart-bacc3d77-590a-4ae6-8312-808350f28763
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984317612 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.hmac_test_hmac_vectors.3984317612
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha_vectors.3750700904
Short name T323
Test name
Test status
Simulation time 100643495741 ps
CPU time 441.58 seconds
Started Jun 13 01:09:37 PM PDT 24
Finished Jun 13 01:17:00 PM PDT 24
Peak memory 199892 kb
Host smart-7da667bf-a7bb-4ab2-b2d6-802e7a6e068a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750700904 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha_vectors.3750700904
Directory /workspace/4.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.1726084470
Short name T551
Test name
Test status
Simulation time 3607155017 ps
CPU time 66.79 seconds
Started Jun 13 01:09:46 PM PDT 24
Finished Jun 13 01:10:53 PM PDT 24
Peak memory 199860 kb
Host smart-86d918dd-c80d-480b-b4fb-6189cf01abd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726084470 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.1726084470
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2788162210
Short name T415
Test name
Test status
Simulation time 16189394 ps
CPU time 0.68 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:03 PM PDT 24
Peak memory 195864 kb
Host smart-63d205b7-8feb-44fc-a483-3f16e7440550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788162210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2788162210
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1307296285
Short name T232
Test name
Test status
Simulation time 3285230293 ps
CPU time 38.26 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:41 PM PDT 24
Peak memory 224616 kb
Host smart-09661bbe-115e-409b-a3e7-54ff989b77a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307296285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1307296285
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.2465456256
Short name T512
Test name
Test status
Simulation time 2896220737 ps
CPU time 36.76 seconds
Started Jun 13 01:10:56 PM PDT 24
Finished Jun 13 01:11:37 PM PDT 24
Peak memory 199916 kb
Host smart-6448335c-6742-4309-8f17-32455c7bb8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465456256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.2465456256
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.1820544402
Short name T89
Test name
Test status
Simulation time 43197072263 ps
CPU time 977.32 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:27:17 PM PDT 24
Peak memory 749996 kb
Host smart-66dc831c-34ee-4ed5-934c-21758bc2a297
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820544402 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.1820544402
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.4157072153
Short name T488
Test name
Test status
Simulation time 9853810849 ps
CPU time 19.4 seconds
Started Jun 13 01:10:57 PM PDT 24
Finished Jun 13 01:11:20 PM PDT 24
Peak memory 199832 kb
Host smart-8195e461-cc5c-4659-af27-697a4e42ef96
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157072153 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.4157072153
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.1498145582
Short name T412
Test name
Test status
Simulation time 3780610225 ps
CPU time 50.8 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:11:50 PM PDT 24
Peak memory 199984 kb
Host smart-8e5a5137-094b-4d89-a107-5f854ae6a91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498145582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.1498145582
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.877964314
Short name T456
Test name
Test status
Simulation time 392225378 ps
CPU time 4.79 seconds
Started Jun 13 01:10:55 PM PDT 24
Finished Jun 13 01:11:04 PM PDT 24
Peak memory 199872 kb
Host smart-13bd80ce-1fd1-4839-8e76-809aa5437bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877964314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.877964314
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3164941281
Short name T405
Test name
Test status
Simulation time 42536449264 ps
CPU time 588.56 seconds
Started Jun 13 01:10:58 PM PDT 24
Finished Jun 13 01:20:51 PM PDT 24
Peak memory 232664 kb
Host smart-ec98f4fa-24f0-44ea-a897-1eef4e38815a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164941281 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3164941281
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.3240062063
Short name T24
Test name
Test status
Simulation time 56517086 ps
CPU time 1.06 seconds
Started Jun 13 01:10:57 PM PDT 24
Finished Jun 13 01:11:03 PM PDT 24
Peak memory 199616 kb
Host smart-7943549a-4c63-455c-a269-736a45ad55ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240062063 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.hmac_test_hmac_vectors.3240062063
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha_vectors.1207641644
Short name T210
Test name
Test status
Simulation time 176113003013 ps
CPU time 489.61 seconds
Started Jun 13 01:10:57 PM PDT 24
Finished Jun 13 01:19:11 PM PDT 24
Peak memory 199824 kb
Host smart-9b2ecc2d-67f8-46b8-94db-e0d6d54e5722
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207641644 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha_vectors.1207641644
Directory /workspace/40.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2696046014
Short name T502
Test name
Test status
Simulation time 6991322289 ps
CPU time 14.94 seconds
Started Jun 13 01:10:56 PM PDT 24
Finished Jun 13 01:11:16 PM PDT 24
Peak memory 199848 kb
Host smart-44430090-97ac-4b63-b29f-055c411d5976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696046014 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2696046014
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.2582863117
Short name T403
Test name
Test status
Simulation time 10362659 ps
CPU time 0.56 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:09 PM PDT 24
Peak memory 194444 kb
Host smart-9ef57dcb-89e8-482a-a796-fbcc90b55cf7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582863117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.2582863117
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.2923209111
Short name T339
Test name
Test status
Simulation time 2434923856 ps
CPU time 61 seconds
Started Jun 13 01:10:52 PM PDT 24
Finished Jun 13 01:11:56 PM PDT 24
Peak memory 232552 kb
Host smart-80ace545-cf9c-4cda-9266-408d85534863
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2923209111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.2923209111
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.2713097412
Short name T459
Test name
Test status
Simulation time 1332009747 ps
CPU time 70.6 seconds
Started Jun 13 01:11:01 PM PDT 24
Finished Jun 13 01:12:17 PM PDT 24
Peak memory 199796 kb
Host smart-5f412937-2b5a-4820-b13b-cccca2846ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713097412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.2713097412
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.166739748
Short name T327
Test name
Test status
Simulation time 2862019277 ps
CPU time 245.45 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:15:14 PM PDT 24
Peak memory 640048 kb
Host smart-2566b470-a0b8-4400-96c3-67340901a61b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=166739748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.166739748
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.2315690324
Short name T573
Test name
Test status
Simulation time 1583868237 ps
CPU time 44.8 seconds
Started Jun 13 01:11:01 PM PDT 24
Finished Jun 13 01:11:51 PM PDT 24
Peak memory 199160 kb
Host smart-9f5fa3ea-c2bd-47f5-aa07-efe847ad9103
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315690324 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.2315690324
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.3978425450
Short name T57
Test name
Test status
Simulation time 13972709971 ps
CPU time 55.93 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:12:04 PM PDT 24
Peak memory 199924 kb
Host smart-b3485d26-56c8-445f-9cba-e87a6f1bf4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978425450 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.3978425450
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.2943496303
Short name T541
Test name
Test status
Simulation time 106950747 ps
CPU time 3.66 seconds
Started Jun 13 01:10:58 PM PDT 24
Finished Jun 13 01:11:06 PM PDT 24
Peak memory 199784 kb
Host smart-5ffd40a1-a5a3-48c1-9ec8-70dbd4c7a1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943496303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.2943496303
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.853737798
Short name T132
Test name
Test status
Simulation time 450592223 ps
CPU time 1.34 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:05 PM PDT 24
Peak memory 199732 kb
Host smart-e3fac421-5d4b-4b47-abf6-d8e5bd286b32
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853737798 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.hmac_test_hmac_vectors.853737798
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha_vectors.526267100
Short name T568
Test name
Test status
Simulation time 15733388356 ps
CPU time 431.05 seconds
Started Jun 13 01:10:58 PM PDT 24
Finished Jun 13 01:18:13 PM PDT 24
Peak memory 199908 kb
Host smart-6c76a841-6ce2-42da-a74c-0e1673ec2fbb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526267100 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha_vectors.526267100
Directory /workspace/41.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.1455756091
Short name T483
Test name
Test status
Simulation time 2902104571 ps
CPU time 7.37 seconds
Started Jun 13 01:11:01 PM PDT 24
Finished Jun 13 01:11:14 PM PDT 24
Peak memory 199724 kb
Host smart-6e162f03-431b-475e-9e00-be8cc8ada1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455756091 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.1455756091
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.2681126432
Short name T587
Test name
Test status
Simulation time 17910609 ps
CPU time 0.62 seconds
Started Jun 13 01:11:01 PM PDT 24
Finished Jun 13 01:11:07 PM PDT 24
Peak memory 195540 kb
Host smart-e6f9b742-1de2-4a45-9ce6-e436baf68e8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681126432 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.2681126432
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1272216851
Short name T531
Test name
Test status
Simulation time 32264189 ps
CPU time 1.67 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:11:06 PM PDT 24
Peak memory 199668 kb
Host smart-492d7415-639e-4194-8e0a-66e2e387caf0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1272216851 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1272216851
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2773600365
Short name T189
Test name
Test status
Simulation time 6743618446 ps
CPU time 25.35 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:28 PM PDT 24
Peak memory 199864 kb
Host smart-4083bf59-29ab-4270-833e-eee52ee589bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773600365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2773600365
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.3261176320
Short name T449
Test name
Test status
Simulation time 3593591196 ps
CPU time 223.11 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:14:48 PM PDT 24
Peak memory 652812 kb
Host smart-aa643a61-14bf-4cc7-b92f-398ed1414b88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3261176320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.3261176320
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2519481715
Short name T480
Test name
Test status
Simulation time 3871961437 ps
CPU time 133.65 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:13:17 PM PDT 24
Peak memory 199884 kb
Host smart-0f8c6b1d-ca52-44b1-87cd-13fb6051a241
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519481715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2519481715
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.2562629480
Short name T580
Test name
Test status
Simulation time 1559435540 ps
CPU time 49 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:11:54 PM PDT 24
Peak memory 199844 kb
Host smart-b036d051-4c9c-409c-b1de-bec94b810514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562629480 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.2562629480
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3110851555
Short name T545
Test name
Test status
Simulation time 117071401 ps
CPU time 2.31 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:05 PM PDT 24
Peak memory 199788 kb
Host smart-906007d5-9dd0-4af7-8b5b-22a840f79d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110851555 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3110851555
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_stress_all.139540436
Short name T98
Test name
Test status
Simulation time 3898171067 ps
CPU time 196.88 seconds
Started Jun 13 01:11:01 PM PDT 24
Finished Jun 13 01:14:23 PM PDT 24
Peak memory 228572 kb
Host smart-edb9c6a3-a8c0-4a2e-b8ee-6687e9a0b794
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139540436 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.139540436
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.3718039653
Short name T265
Test name
Test status
Simulation time 111648233 ps
CPU time 1.18 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:11:05 PM PDT 24
Peak memory 199752 kb
Host smart-34e697a3-17ba-4a73-8639-d766f7e02793
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718039653 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.hmac_test_hmac_vectors.3718039653
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha_vectors.2433532232
Short name T344
Test name
Test status
Simulation time 179385647571 ps
CPU time 497.99 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:19:27 PM PDT 24
Peak memory 199912 kb
Host smart-f83cdecd-21e3-4e04-8c1e-4de9f67e7c6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433532232 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha_vectors.2433532232
Directory /workspace/42.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.574358477
Short name T256
Test name
Test status
Simulation time 1614129654 ps
CPU time 70.81 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:12:14 PM PDT 24
Peak memory 199876 kb
Host smart-756c6bcc-e55f-40fb-bcba-738f37e07742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574358477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.574358477
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1846198009
Short name T156
Test name
Test status
Simulation time 60024237 ps
CPU time 0.66 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:04 PM PDT 24
Peak memory 194752 kb
Host smart-0d8d81ad-8540-45e0-b0d8-3b50d1a512bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846198009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1846198009
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.2790088934
Short name T31
Test name
Test status
Simulation time 980519223 ps
CPU time 40.59 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:11:45 PM PDT 24
Peak memory 215512 kb
Host smart-4582c37d-5421-4c61-ac30-5d5c8c49950a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2790088934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.2790088934
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1543707290
Short name T216
Test name
Test status
Simulation time 1995821432 ps
CPU time 29.63 seconds
Started Jun 13 01:11:01 PM PDT 24
Finished Jun 13 01:11:35 PM PDT 24
Peak memory 199816 kb
Host smart-6c33e69a-d64a-48d3-8bb6-b13b07a3a6a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543707290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1543707290
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3094118972
Short name T517
Test name
Test status
Simulation time 2757518680 ps
CPU time 729.34 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:23:14 PM PDT 24
Peak memory 741116 kb
Host smart-c958807c-645f-47c5-9906-22d7d8593f2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094118972 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3094118972
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2707856537
Short name T52
Test name
Test status
Simulation time 1419635618 ps
CPU time 5.01 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:11:11 PM PDT 24
Peak memory 199764 kb
Host smart-90326efe-c052-41c8-b6e6-99c999fc3080
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707856537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2707856537
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1065232077
Short name T384
Test name
Test status
Simulation time 2523387668 ps
CPU time 76.74 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:12:22 PM PDT 24
Peak memory 199892 kb
Host smart-f0f164d0-d406-4ab2-9526-78903e9c369e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065232077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1065232077
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3387237975
Short name T321
Test name
Test status
Simulation time 1109255524 ps
CPU time 7.2 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:11:11 PM PDT 24
Peak memory 199784 kb
Host smart-96282f83-aee6-4f20-823e-154b922bb7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387237975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3387237975
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_stress_all.2438296802
Short name T179
Test name
Test status
Simulation time 49331181396 ps
CPU time 329.79 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:16:33 PM PDT 24
Peak memory 199904 kb
Host smart-024f8363-8f4a-4b26-8558-8ea4239ab2c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438296802 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.hmac_stress_all.2438296802
Directory /workspace/43.hmac_stress_all/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.3079656833
Short name T500
Test name
Test status
Simulation time 194363405 ps
CPU time 1.09 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:11:11 PM PDT 24
Peak memory 199756 kb
Host smart-589acca0-c81c-4034-9464-1dcf413ecfd7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079656833 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.hmac_test_hmac_vectors.3079656833
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha_vectors.3255472678
Short name T293
Test name
Test status
Simulation time 34261360209 ps
CPU time 469.28 seconds
Started Jun 13 01:11:09 PM PDT 24
Finished Jun 13 01:19:01 PM PDT 24
Peak memory 199816 kb
Host smart-a4db16a9-1a03-4360-b87a-80d38c048c20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255472678 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha_vectors.3255472678
Directory /workspace/43.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.3110213601
Short name T368
Test name
Test status
Simulation time 5817371391 ps
CPU time 11.01 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:11:16 PM PDT 24
Peak memory 199852 kb
Host smart-a706f7cd-b96c-4382-a77a-162aad3bc666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110213601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.3110213601
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.2887041760
Short name T197
Test name
Test status
Simulation time 19945921 ps
CPU time 0.56 seconds
Started Jun 13 01:11:04 PM PDT 24
Finished Jun 13 01:11:10 PM PDT 24
Peak memory 196532 kb
Host smart-b4cb7c42-2bff-4ff2-ac51-edbc9b118f8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887041760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.2887041760
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.546298611
Short name T36
Test name
Test status
Simulation time 424813826 ps
CPU time 5 seconds
Started Jun 13 01:11:07 PM PDT 24
Finished Jun 13 01:11:16 PM PDT 24
Peak memory 199788 kb
Host smart-a6ab86d5-804d-490a-881f-81d87f1a9d04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=546298611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.546298611
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.2128346563
Short name T221
Test name
Test status
Simulation time 1049229484 ps
CPU time 21.73 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:11:32 PM PDT 24
Peak memory 199836 kb
Host smart-19081a0f-c5b5-4b36-b269-45db6c5384c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128346563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.2128346563
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.2404495258
Short name T526
Test name
Test status
Simulation time 2616028771 ps
CPU time 631.3 seconds
Started Jun 13 01:10:59 PM PDT 24
Finished Jun 13 01:21:35 PM PDT 24
Peak memory 669364 kb
Host smart-cfc8f059-5d50-4265-b56a-c5e02e508ef6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2404495258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.2404495258
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.1427879602
Short name T475
Test name
Test status
Simulation time 6220143844 ps
CPU time 58.69 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:12:04 PM PDT 24
Peak memory 199828 kb
Host smart-d06b3046-eab4-4cfe-9f72-06ee91892a9a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427879602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1427879602
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.154077394
Short name T555
Test name
Test status
Simulation time 965467805 ps
CPU time 54.72 seconds
Started Jun 13 01:11:01 PM PDT 24
Finished Jun 13 01:12:01 PM PDT 24
Peak memory 199996 kb
Host smart-e9f926ff-2512-4c0a-914c-45abd5927b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154077394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.154077394
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.4129986878
Short name T278
Test name
Test status
Simulation time 608428803 ps
CPU time 6.26 seconds
Started Jun 13 01:11:05 PM PDT 24
Finished Jun 13 01:11:16 PM PDT 24
Peak memory 199812 kb
Host smart-bde9657a-e092-474d-8931-3447c72652b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129986878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.4129986878
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.1455364328
Short name T494
Test name
Test status
Simulation time 47857245 ps
CPU time 1.11 seconds
Started Jun 13 01:11:02 PM PDT 24
Finished Jun 13 01:11:08 PM PDT 24
Peak memory 199556 kb
Host smart-87d34ad2-6a58-45e0-be0e-9e2de5a0c347
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455364328 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.hmac_test_hmac_vectors.1455364328
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha_vectors.3163350728
Short name T199
Test name
Test status
Simulation time 78255242093 ps
CPU time 395.08 seconds
Started Jun 13 01:11:05 PM PDT 24
Finished Jun 13 01:17:45 PM PDT 24
Peak memory 199808 kb
Host smart-1b118b6b-75fa-4099-a435-8a3399fac98a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163350728 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha_vectors.3163350728
Directory /workspace/44.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1485736962
Short name T55
Test name
Test status
Simulation time 8753915951 ps
CPU time 31.78 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:11:42 PM PDT 24
Peak memory 199808 kb
Host smart-fcbf2c7c-5f0e-4824-9f04-350758d102a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485736962 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1485736962
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.2607152100
Short name T453
Test name
Test status
Simulation time 16832628 ps
CPU time 0.58 seconds
Started Jun 13 01:31:31 PM PDT 24
Finished Jun 13 01:31:33 PM PDT 24
Peak memory 194832 kb
Host smart-1c893e12-86b9-4870-9ce8-24043b2d83cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607152100 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.2607152100
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.104296249
Short name T237
Test name
Test status
Simulation time 3052425996 ps
CPU time 36.39 seconds
Started Jun 13 02:13:57 PM PDT 24
Finished Jun 13 02:14:34 PM PDT 24
Peak memory 231936 kb
Host smart-52a315ac-2a43-450c-8cd6-87a5248c91b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104296249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.104296249
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.2453440132
Short name T397
Test name
Test status
Simulation time 5343714192 ps
CPU time 27.38 seconds
Started Jun 13 01:11:03 PM PDT 24
Finished Jun 13 01:11:35 PM PDT 24
Peak memory 199868 kb
Host smart-e49fdbcf-76af-418e-aaed-c71764841fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453440132 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.2453440132
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2839805233
Short name T153
Test name
Test status
Simulation time 8165408875 ps
CPU time 256.54 seconds
Started Jun 13 02:14:46 PM PDT 24
Finished Jun 13 02:19:03 PM PDT 24
Peak memory 416352 kb
Host smart-9094ef9f-fae9-4e64-9006-14226c0374f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2839805233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2839805233
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.615675261
Short name T469
Test name
Test status
Simulation time 40130037184 ps
CPU time 185.08 seconds
Started Jun 13 01:56:07 PM PDT 24
Finished Jun 13 01:59:16 PM PDT 24
Peak memory 199912 kb
Host smart-2ba50e57-2922-4b4e-b4f9-265c68f16b53
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615675261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.615675261
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1996689670
Short name T349
Test name
Test status
Simulation time 21043777991 ps
CPU time 73.59 seconds
Started Jun 13 01:35:58 PM PDT 24
Finished Jun 13 01:37:12 PM PDT 24
Peak memory 199872 kb
Host smart-83a6a30b-fbec-4577-bc1f-bc8a543c69f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996689670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1996689670
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.4241703820
Short name T235
Test name
Test status
Simulation time 415273496 ps
CPU time 6.26 seconds
Started Jun 13 01:11:05 PM PDT 24
Finished Jun 13 01:11:16 PM PDT 24
Peak memory 199748 kb
Host smart-16af8fe5-7081-4ca2-93e1-1b984b9d407c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241703820 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.4241703820
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.3890369655
Short name T461
Test name
Test status
Simulation time 793959158 ps
CPU time 1.4 seconds
Started Jun 13 01:12:24 PM PDT 24
Finished Jun 13 01:12:25 PM PDT 24
Peak memory 199792 kb
Host smart-363611db-e161-4aa4-befc-b81f8f31bb46
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890369655 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.hmac_test_hmac_vectors.3890369655
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha_vectors.196915759
Short name T432
Test name
Test status
Simulation time 42530886156 ps
CPU time 456.42 seconds
Started Jun 13 01:54:46 PM PDT 24
Finished Jun 13 02:02:28 PM PDT 24
Peak memory 199856 kb
Host smart-fabde443-0740-42fe-b05f-ff349a5e6324
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196915759 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha_vectors.196915759
Directory /workspace/45.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.4269739964
Short name T444
Test name
Test status
Simulation time 2004217085 ps
CPU time 37.5 seconds
Started Jun 13 01:11:07 PM PDT 24
Finished Jun 13 01:11:48 PM PDT 24
Peak memory 199880 kb
Host smart-42802bf6-2dcf-4fc1-8d4d-765fcc40b8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269739964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.4269739964
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.2832009814
Short name T290
Test name
Test status
Simulation time 52651226 ps
CPU time 0.58 seconds
Started Jun 13 01:49:52 PM PDT 24
Finished Jun 13 01:49:54 PM PDT 24
Peak memory 195636 kb
Host smart-5482dd68-194f-4f54-a4b8-fb30eeafbb4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832009814 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.2832009814
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1216334405
Short name T562
Test name
Test status
Simulation time 4212052779 ps
CPU time 44.03 seconds
Started Jun 13 02:30:04 PM PDT 24
Finished Jun 13 02:30:48 PM PDT 24
Peak memory 221212 kb
Host smart-d5f0cceb-1b58-4b4b-a56f-42610b569490
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1216334405 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1216334405
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1693146160
Short name T116
Test name
Test status
Simulation time 329576154 ps
CPU time 3.62 seconds
Started Jun 13 02:32:18 PM PDT 24
Finished Jun 13 02:32:30 PM PDT 24
Peak memory 199856 kb
Host smart-3c355b79-285a-479e-8fb6-376d64f31fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693146160 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1693146160
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1797358078
Short name T505
Test name
Test status
Simulation time 3674794790 ps
CPU time 1123.59 seconds
Started Jun 13 01:15:04 PM PDT 24
Finished Jun 13 01:33:49 PM PDT 24
Peak memory 719076 kb
Host smart-5774be79-61e1-4444-a08d-f876b89795db
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1797358078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1797358078
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.757855611
Short name T196
Test name
Test status
Simulation time 1934438178 ps
CPU time 109.43 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:13:00 PM PDT 24
Peak memory 199864 kb
Host smart-32610f15-ba12-4afd-b605-1eddd00d11d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757855611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.757855611
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1331718891
Short name T425
Test name
Test status
Simulation time 1057799864 ps
CPU time 63.2 seconds
Started Jun 13 01:39:20 PM PDT 24
Finished Jun 13 01:40:24 PM PDT 24
Peak memory 199844 kb
Host smart-4b5146e5-2ded-4f91-93c5-d9556959a2ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331718891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1331718891
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.3812472185
Short name T124
Test name
Test status
Simulation time 189495390 ps
CPU time 4.31 seconds
Started Jun 13 02:19:00 PM PDT 24
Finished Jun 13 02:19:13 PM PDT 24
Peak memory 199792 kb
Host smart-39d6776c-5c40-4d31-939a-e9c9e13a10c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812472185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.3812472185
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.347891821
Short name T511
Test name
Test status
Simulation time 46540472591 ps
CPU time 2388.3 seconds
Started Jun 13 01:23:34 PM PDT 24
Finished Jun 13 02:03:23 PM PDT 24
Peak memory 654388 kb
Host smart-5bf7faa8-39ef-4e56-a0a7-a039d87fc9ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347891821 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.347891821
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.3605860010
Short name T167
Test name
Test status
Simulation time 949844062 ps
CPU time 1.43 seconds
Started Jun 13 01:11:01 PM PDT 24
Finished Jun 13 01:11:08 PM PDT 24
Peak memory 199784 kb
Host smart-2748bf47-3d99-49d3-b180-3cdec330ac6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605860010 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.hmac_test_hmac_vectors.3605860010
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha_vectors.3000334821
Short name T204
Test name
Test status
Simulation time 13044594779 ps
CPU time 453.95 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:18:39 PM PDT 24
Peak memory 199772 kb
Host smart-5dbbc527-0057-464b-bef0-ee4cf8c33a3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000334821 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha_vectors.3000334821
Directory /workspace/46.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.2369795344
Short name T287
Test name
Test status
Simulation time 3489022932 ps
CPU time 47.96 seconds
Started Jun 13 01:11:10 PM PDT 24
Finished Jun 13 01:12:00 PM PDT 24
Peak memory 199864 kb
Host smart-0715e99a-3e20-4f91-b2fe-8c9813a53032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369795344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.2369795344
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.3813252280
Short name T380
Test name
Test status
Simulation time 42561537 ps
CPU time 0.59 seconds
Started Jun 13 01:11:10 PM PDT 24
Finished Jun 13 01:11:13 PM PDT 24
Peak memory 195828 kb
Host smart-20abc7cc-e699-468f-bb64-8f5d2241b244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813252280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.3813252280
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.891159341
Short name T250
Test name
Test status
Simulation time 6582333932 ps
CPU time 32.5 seconds
Started Jun 13 02:03:27 PM PDT 24
Finished Jun 13 02:04:01 PM PDT 24
Peak memory 208060 kb
Host smart-aa687fe1-bb13-4a4d-b891-f46d2cdb43a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=891159341 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.891159341
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.782427093
Short name T550
Test name
Test status
Simulation time 8336410544 ps
CPU time 44.33 seconds
Started Jun 13 01:44:02 PM PDT 24
Finished Jun 13 01:44:48 PM PDT 24
Peak memory 199876 kb
Host smart-a55c8dfb-14dc-4684-8f66-ede664b0c2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782427093 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.782427093
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.3679821206
Short name T130
Test name
Test status
Simulation time 2441327460 ps
CPU time 673.93 seconds
Started Jun 13 01:48:54 PM PDT 24
Finished Jun 13 02:00:10 PM PDT 24
Peak memory 662000 kb
Host smart-f3ad411a-9513-4862-8147-94a0ff73d489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3679821206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.3679821206
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.1922095772
Short name T174
Test name
Test status
Simulation time 10480774128 ps
CPU time 92.08 seconds
Started Jun 13 01:11:11 PM PDT 24
Finished Jun 13 01:12:44 PM PDT 24
Peak memory 199788 kb
Host smart-c259b069-6ad9-4176-b2ab-076d34187003
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922095772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.1922095772
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3267685483
Short name T133
Test name
Test status
Simulation time 1529504429 ps
CPU time 91.95 seconds
Started Jun 13 01:26:47 PM PDT 24
Finished Jun 13 01:28:20 PM PDT 24
Peak memory 199856 kb
Host smart-4fedf777-aba7-4ffd-b9d9-910d227d382d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267685483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3267685483
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.42030445
Short name T184
Test name
Test status
Simulation time 1761504048 ps
CPU time 7.5 seconds
Started Jun 13 01:51:00 PM PDT 24
Finished Jun 13 01:51:10 PM PDT 24
Peak memory 199812 kb
Host smart-1c2320d3-a260-4db5-ad9b-353b39b823bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42030445 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.42030445
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.473322635
Short name T193
Test name
Test status
Simulation time 85210822578 ps
CPU time 1934.86 seconds
Started Jun 13 01:11:02 PM PDT 24
Finished Jun 13 01:43:22 PM PDT 24
Peak memory 672656 kb
Host smart-e41f5588-4d2c-44ee-bbcc-6c38e81f35df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473322635 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.473322635
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.2015768708
Short name T513
Test name
Test status
Simulation time 123799772 ps
CPU time 1.51 seconds
Started Jun 13 01:33:21 PM PDT 24
Finished Jun 13 01:33:23 PM PDT 24
Peak memory 199792 kb
Host smart-4f2a33c1-dce2-4b1a-a1f1-77c197a9c8e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015768708 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.hmac_test_hmac_vectors.2015768708
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha_vectors.1098548940
Short name T122
Test name
Test status
Simulation time 170932404435 ps
CPU time 546.71 seconds
Started Jun 13 02:12:19 PM PDT 24
Finished Jun 13 02:21:26 PM PDT 24
Peak memory 199936 kb
Host smart-69e7e4fd-113f-43af-a386-676691091ab7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098548940 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha_vectors.1098548940
Directory /workspace/47.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1202017557
Short name T525
Test name
Test status
Simulation time 8243332357 ps
CPU time 31.95 seconds
Started Jun 13 02:05:08 PM PDT 24
Finished Jun 13 02:05:40 PM PDT 24
Peak memory 199944 kb
Host smart-2b8960ce-dc26-46a0-b574-77c868909642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202017557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1202017557
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1254896699
Short name T251
Test name
Test status
Simulation time 100432628 ps
CPU time 0.59 seconds
Started Jun 13 01:45:54 PM PDT 24
Finished Jun 13 01:45:55 PM PDT 24
Peak memory 195848 kb
Host smart-c585ebf0-05df-4f1f-a562-2c3a6d7d55b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254896699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1254896699
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.920625877
Short name T271
Test name
Test status
Simulation time 1269659546 ps
CPU time 41.27 seconds
Started Jun 13 01:34:52 PM PDT 24
Finished Jun 13 01:35:33 PM PDT 24
Peak memory 232028 kb
Host smart-33796485-2107-4a4b-a2f3-69b111d88d7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=920625877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.920625877
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.1620068680
Short name T114
Test name
Test status
Simulation time 302438929 ps
CPU time 5.06 seconds
Started Jun 13 01:25:30 PM PDT 24
Finished Jun 13 01:25:36 PM PDT 24
Peak memory 199724 kb
Host smart-fa04d5b4-8a92-4341-8e5b-0b10cd85849f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620068680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.1620068680
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.1812548012
Short name T117
Test name
Test status
Simulation time 6083217176 ps
CPU time 335.42 seconds
Started Jun 13 02:13:07 PM PDT 24
Finished Jun 13 02:18:44 PM PDT 24
Peak memory 648024 kb
Host smart-1802eba9-b756-433f-945c-1403469f2427
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1812548012 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.1812548012
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3282796369
Short name T358
Test name
Test status
Simulation time 8945395753 ps
CPU time 61.93 seconds
Started Jun 13 01:59:42 PM PDT 24
Finished Jun 13 02:00:46 PM PDT 24
Peak memory 199808 kb
Host smart-29e2215c-eca3-4acf-84a9-a1c25039c22b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282796369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3282796369
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2499738186
Short name T177
Test name
Test status
Simulation time 78259407 ps
CPU time 4.38 seconds
Started Jun 13 01:11:10 PM PDT 24
Finished Jun 13 01:11:16 PM PDT 24
Peak memory 199768 kb
Host smart-6f20ea21-fa1c-405e-acce-e7ef942ee485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499738186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2499738186
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.796202551
Short name T222
Test name
Test status
Simulation time 626707979 ps
CPU time 5.57 seconds
Started Jun 13 01:23:11 PM PDT 24
Finished Jun 13 01:23:17 PM PDT 24
Peak memory 199808 kb
Host smart-d6dd5b38-4482-43b1-8788-697b55495e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796202551 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.796202551
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.2922828435
Short name T420
Test name
Test status
Simulation time 74170696250 ps
CPU time 786.12 seconds
Started Jun 13 01:11:06 PM PDT 24
Finished Jun 13 01:24:16 PM PDT 24
Peak memory 229128 kb
Host smart-451f0444-e1ce-41ec-ac1e-a38dd00d2c35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922828435 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.2922828435
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.2766622761
Short name T171
Test name
Test status
Simulation time 222053487 ps
CPU time 1.44 seconds
Started Jun 13 01:33:46 PM PDT 24
Finished Jun 13 01:33:48 PM PDT 24
Peak memory 199836 kb
Host smart-860de4b7-fd86-49b4-83b6-1a0eb4e6f819
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766622761 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.hmac_test_hmac_vectors.2766622761
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha_vectors.2233647628
Short name T286
Test name
Test status
Simulation time 788754945009 ps
CPU time 557.5 seconds
Started Jun 13 01:36:10 PM PDT 24
Finished Jun 13 01:45:28 PM PDT 24
Peak memory 199908 kb
Host smart-75164a37-7689-4aa6-be09-2cacf8f5ff53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233647628 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha_vectors.2233647628
Directory /workspace/48.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1736994760
Short name T324
Test name
Test status
Simulation time 3546678008 ps
CPU time 49 seconds
Started Jun 13 01:33:49 PM PDT 24
Finished Jun 13 01:34:39 PM PDT 24
Peak memory 199860 kb
Host smart-536bef5a-c28b-4365-a8f1-89ccc3b86d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736994760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1736994760
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.1084825888
Short name T476
Test name
Test status
Simulation time 12811725 ps
CPU time 0.57 seconds
Started Jun 13 01:11:10 PM PDT 24
Finished Jun 13 01:11:13 PM PDT 24
Peak memory 195828 kb
Host smart-e6131a0b-ec1c-4ad7-855d-9fedc5a2b7bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084825888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.1084825888
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.3676099409
Short name T111
Test name
Test status
Simulation time 2573384902 ps
CPU time 27.2 seconds
Started Jun 13 02:20:21 PM PDT 24
Finished Jun 13 02:20:59 PM PDT 24
Peak memory 221416 kb
Host smart-79a652de-d7f8-463b-b3c0-12da23acbe6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676099409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.3676099409
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1950153511
Short name T508
Test name
Test status
Simulation time 2683200407 ps
CPU time 39.04 seconds
Started Jun 13 02:09:43 PM PDT 24
Finished Jun 13 02:10:23 PM PDT 24
Peak memory 199872 kb
Host smart-c6257076-1570-464c-8bf2-e7fbd273b654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950153511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1950153511
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.1082243861
Short name T457
Test name
Test status
Simulation time 12768801667 ps
CPU time 815.09 seconds
Started Jun 13 02:13:20 PM PDT 24
Finished Jun 13 02:26:56 PM PDT 24
Peak memory 749572 kb
Host smart-2b001446-e3d1-4f4d-a112-2b28aebb31f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1082243861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.1082243861
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.2711799137
Short name T413
Test name
Test status
Simulation time 1305233688 ps
CPU time 75.03 seconds
Started Jun 13 01:27:32 PM PDT 24
Finished Jun 13 01:28:49 PM PDT 24
Peak memory 199760 kb
Host smart-548116bc-39e6-46fa-9f50-7a0cdcc1d087
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711799137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.2711799137
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2688595934
Short name T115
Test name
Test status
Simulation time 15329124567 ps
CPU time 100.81 seconds
Started Jun 13 02:00:34 PM PDT 24
Finished Jun 13 02:02:16 PM PDT 24
Peak memory 199912 kb
Host smart-3a46ae1c-fa04-4169-a412-476ce73ba99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688595934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2688595934
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.574381591
Short name T125
Test name
Test status
Simulation time 1680922274 ps
CPU time 9.55 seconds
Started Jun 13 02:35:02 PM PDT 24
Finished Jun 13 02:35:12 PM PDT 24
Peak memory 199816 kb
Host smart-074062df-8449-4534-851b-b3619ed53dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574381591 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.574381591
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_stress_all.2365068643
Short name T496
Test name
Test status
Simulation time 15123269774 ps
CPU time 157.94 seconds
Started Jun 13 02:02:02 PM PDT 24
Finished Jun 13 02:04:41 PM PDT 24
Peak memory 209128 kb
Host smart-2434efef-73a2-45ea-b755-15b5952c45b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365068643 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.hmac_stress_all.2365068643
Directory /workspace/49.hmac_stress_all/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.995354330
Short name T341
Test name
Test status
Simulation time 29866739 ps
CPU time 1.1 seconds
Started Jun 13 01:18:20 PM PDT 24
Finished Jun 13 01:18:22 PM PDT 24
Peak memory 199596 kb
Host smart-e998633d-dd5f-4f40-bd9a-0e5e496e5000
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995354330 -assert nopostproc +UVM_TESTNAME=hmac_base_
test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.hmac_test_hmac_vectors.995354330
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha_vectors.2525803247
Short name T360
Test name
Test status
Simulation time 54916826922 ps
CPU time 557.38 seconds
Started Jun 13 02:00:55 PM PDT 24
Finished Jun 13 02:10:14 PM PDT 24
Peak memory 199900 kb
Host smart-852e8552-b6f3-4dec-a5b5-3a531da9e37c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525803247 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha_vectors.2525803247
Directory /workspace/49.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.809286272
Short name T118
Test name
Test status
Simulation time 583927428 ps
CPU time 30.75 seconds
Started Jun 13 01:11:00 PM PDT 24
Finished Jun 13 01:11:36 PM PDT 24
Peak memory 199804 kb
Host smart-fd1ff754-f51a-4bfe-816f-62f2b76e8dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809286272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.809286272
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1115862015
Short name T346
Test name
Test status
Simulation time 12563517 ps
CPU time 0.58 seconds
Started Jun 13 01:09:34 PM PDT 24
Finished Jun 13 01:09:36 PM PDT 24
Peak memory 195848 kb
Host smart-ed36de99-0f33-4a5a-ba9e-4ca5bd3251e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115862015 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1115862015
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.1844922588
Short name T402
Test name
Test status
Simulation time 956736237 ps
CPU time 49.7 seconds
Started Jun 13 01:09:37 PM PDT 24
Finished Jun 13 01:10:28 PM PDT 24
Peak memory 223876 kb
Host smart-003247d3-b037-4e9f-baef-a02d5b614964
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844922588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.1844922588
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.4215666384
Short name T463
Test name
Test status
Simulation time 484711169 ps
CPU time 6.62 seconds
Started Jun 13 01:09:34 PM PDT 24
Finished Jun 13 01:09:42 PM PDT 24
Peak memory 199844 kb
Host smart-4281efcf-f585-4bc8-a071-23b6ac16a9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215666384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.4215666384
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1253077106
Short name T42
Test name
Test status
Simulation time 1180976855 ps
CPU time 320.66 seconds
Started Jun 13 01:09:50 PM PDT 24
Finished Jun 13 01:15:12 PM PDT 24
Peak memory 666500 kb
Host smart-e5691404-cb5f-4e30-b089-c5b20ea28439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1253077106 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1253077106
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.4270718792
Short name T442
Test name
Test status
Simulation time 61250854473 ps
CPU time 186.46 seconds
Started Jun 13 01:09:33 PM PDT 24
Finished Jun 13 01:12:41 PM PDT 24
Peak memory 199840 kb
Host smart-34bf577d-8f76-40ba-a2d4-d33df73a55e7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270718792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.4270718792
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3338064297
Short name T348
Test name
Test status
Simulation time 976092818 ps
CPU time 54.82 seconds
Started Jun 13 01:09:50 PM PDT 24
Finished Jun 13 01:10:46 PM PDT 24
Peak memory 199864 kb
Host smart-f9dd2544-0b6e-4460-8d45-53f9d6239391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338064297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3338064297
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.2863737799
Short name T149
Test name
Test status
Simulation time 798757558 ps
CPU time 5.4 seconds
Started Jun 13 01:09:31 PM PDT 24
Finished Jun 13 01:09:37 PM PDT 24
Peak memory 199816 kb
Host smart-e5440102-5af5-4501-bc4f-90f29e455e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863737799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.2863737799
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1354167829
Short name T198
Test name
Test status
Simulation time 44690566295 ps
CPU time 621.93 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:20:17 PM PDT 24
Peak memory 227524 kb
Host smart-241b26ee-3b9b-47dc-b04d-d31de1e6b8a3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354167829 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1354167829
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.3243742643
Short name T523
Test name
Test status
Simulation time 30568053 ps
CPU time 1.01 seconds
Started Jun 13 01:09:48 PM PDT 24
Finished Jun 13 01:09:50 PM PDT 24
Peak memory 199408 kb
Host smart-e00ec870-11a2-498a-ab92-5ea0e6387daa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243742643 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.hmac_test_hmac_vectors.3243742643
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha_vectors.3934594773
Short name T5
Test name
Test status
Simulation time 26545245024 ps
CPU time 500.89 seconds
Started Jun 13 01:09:33 PM PDT 24
Finished Jun 13 01:17:55 PM PDT 24
Peak memory 199840 kb
Host smart-17afcc52-67a0-4b73-8553-74667d72c730
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934594773 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha_vectors.3934594773
Directory /workspace/5.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.1198175857
Short name T340
Test name
Test status
Simulation time 1372552019 ps
CPU time 25.79 seconds
Started Jun 13 01:09:37 PM PDT 24
Finished Jun 13 01:10:03 PM PDT 24
Peak memory 199840 kb
Host smart-fd57957a-c692-4cc9-8999-88fff0a7c6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198175857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.1198175857
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1944519786
Short name T467
Test name
Test status
Simulation time 13508131 ps
CPU time 0.58 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:09:49 PM PDT 24
Peak memory 195496 kb
Host smart-30459fd0-484c-43d9-a37b-812569b981f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944519786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1944519786
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.3086456755
Short name T228
Test name
Test status
Simulation time 882133287 ps
CPU time 38.94 seconds
Started Jun 13 01:09:39 PM PDT 24
Finished Jun 13 01:10:19 PM PDT 24
Peak memory 208044 kb
Host smart-11c83cf6-4bbc-413b-915a-f375310cb47c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3086456755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.3086456755
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3200409143
Short name T381
Test name
Test status
Simulation time 2389881856 ps
CPU time 45.78 seconds
Started Jun 13 01:09:35 PM PDT 24
Finished Jun 13 01:10:22 PM PDT 24
Peak memory 199860 kb
Host smart-11795f33-9f5c-4b49-ac45-61763c3d9ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200409143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3200409143
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2999325128
Short name T267
Test name
Test status
Simulation time 143189725 ps
CPU time 2.31 seconds
Started Jun 13 01:09:36 PM PDT 24
Finished Jun 13 01:09:39 PM PDT 24
Peak memory 199812 kb
Host smart-d5213e67-91cc-4afa-ad83-e90aa94e49f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2999325128 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2999325128
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.2087918779
Short name T401
Test name
Test status
Simulation time 27686566353 ps
CPU time 87.44 seconds
Started Jun 13 01:09:36 PM PDT 24
Finished Jun 13 01:11:04 PM PDT 24
Peak memory 199860 kb
Host smart-68af811b-d009-443e-9501-785827f2f259
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087918779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.2087918779
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.1906807469
Short name T272
Test name
Test status
Simulation time 1637850057 ps
CPU time 49.09 seconds
Started Jun 13 01:09:32 PM PDT 24
Finished Jun 13 01:10:23 PM PDT 24
Peak memory 199856 kb
Host smart-651dc1b1-0202-4abb-b995-71726c25bc84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906807469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.1906807469
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.1217647558
Short name T68
Test name
Test status
Simulation time 134930069 ps
CPU time 1.72 seconds
Started Jun 13 01:09:36 PM PDT 24
Finished Jun 13 01:09:39 PM PDT 24
Peak memory 199780 kb
Host smart-b7b9e60e-0074-4037-81aa-260b6b2c49b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217647558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.1217647558
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.1900544609
Short name T200
Test name
Test status
Simulation time 29422505483 ps
CPU time 1297.55 seconds
Started Jun 13 01:09:37 PM PDT 24
Finished Jun 13 01:31:16 PM PDT 24
Peak memory 648320 kb
Host smart-5c88e073-998d-488a-964a-f70e6617757c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900544609 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.1900544609
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.3887337471
Short name T489
Test name
Test status
Simulation time 132182504 ps
CPU time 1.09 seconds
Started Jun 13 01:09:39 PM PDT 24
Finished Jun 13 01:09:41 PM PDT 24
Peak memory 199844 kb
Host smart-c04af94d-7823-4048-8fcf-86d214b47382
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887337471 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.hmac_test_hmac_vectors.3887337471
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha_vectors.1067915988
Short name T417
Test name
Test status
Simulation time 49126164412 ps
CPU time 459.41 seconds
Started Jun 13 01:09:41 PM PDT 24
Finished Jun 13 01:17:22 PM PDT 24
Peak memory 199896 kb
Host smart-f0e2e94f-3bb5-4aae-8101-5c383c1f1baa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067915988 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha_vectors.1067915988
Directory /workspace/6.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.2897797877
Short name T343
Test name
Test status
Simulation time 755050666 ps
CPU time 11.39 seconds
Started Jun 13 01:09:36 PM PDT 24
Finished Jun 13 01:09:49 PM PDT 24
Peak memory 199828 kb
Host smart-a300207c-af56-486a-88d1-5d7c1db74842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897797877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.2897797877
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2398572397
Short name T240
Test name
Test status
Simulation time 12088103 ps
CPU time 0.58 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:09:48 PM PDT 24
Peak memory 195544 kb
Host smart-ad3f53a8-a93d-428d-afc8-fee834dcd125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398572397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2398572397
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1164975782
Short name T410
Test name
Test status
Simulation time 405418242 ps
CPU time 16.77 seconds
Started Jun 13 01:09:42 PM PDT 24
Finished Jun 13 01:10:00 PM PDT 24
Peak memory 207976 kb
Host smart-0abba5c0-39bb-4aea-afdb-9119c4788c30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1164975782 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1164975782
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1553269543
Short name T371
Test name
Test status
Simulation time 2450562863 ps
CPU time 14.2 seconds
Started Jun 13 01:09:39 PM PDT 24
Finished Jun 13 01:09:54 PM PDT 24
Peak memory 199912 kb
Host smart-448769ee-5ec2-4a43-ba4a-5e1e50ed4c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553269543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1553269543
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.640349252
Short name T353
Test name
Test status
Simulation time 3664747096 ps
CPU time 415.69 seconds
Started Jun 13 01:09:41 PM PDT 24
Finished Jun 13 01:16:38 PM PDT 24
Peak memory 668876 kb
Host smart-20d2550c-e8cb-46e1-b765-700316ade128
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=640349252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.640349252
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3920952768
Short name T170
Test name
Test status
Simulation time 11988055410 ps
CPU time 216.42 seconds
Started Jun 13 01:09:40 PM PDT 24
Finished Jun 13 01:13:18 PM PDT 24
Peak memory 199860 kb
Host smart-75d81169-7f3d-4187-bdca-9776ecc2178a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920952768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3920952768
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.4180634858
Short name T331
Test name
Test status
Simulation time 927028006 ps
CPU time 13.64 seconds
Started Jun 13 01:09:39 PM PDT 24
Finished Jun 13 01:09:54 PM PDT 24
Peak memory 199832 kb
Host smart-39b03d82-95f6-4d1b-bc7e-97b03cdb1a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180634858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.4180634858
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.766955335
Short name T547
Test name
Test status
Simulation time 360596190 ps
CPU time 6.72 seconds
Started Jun 13 01:09:50 PM PDT 24
Finished Jun 13 01:09:58 PM PDT 24
Peak memory 199800 kb
Host smart-0050e024-ed96-4e7d-87e1-c40246e0c0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766955335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.766955335
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.13468287
Short name T67
Test name
Test status
Simulation time 38940300372 ps
CPU time 1059.55 seconds
Started Jun 13 01:09:47 PM PDT 24
Finished Jun 13 01:27:28 PM PDT 24
Peak memory 649024 kb
Host smart-6135c0ba-c12d-4c84-8415-6d63f6065bef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13468287 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.13468287
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.3954928503
Short name T247
Test name
Test status
Simulation time 66291584 ps
CPU time 1.28 seconds
Started Jun 13 01:09:39 PM PDT 24
Finished Jun 13 01:09:42 PM PDT 24
Peak memory 199808 kb
Host smart-80932ccf-7135-4639-88ae-a5183e00f32d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954928503 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.hmac_test_hmac_vectors.3954928503
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha_vectors.155707842
Short name T540
Test name
Test status
Simulation time 41340881838 ps
CPU time 431.45 seconds
Started Jun 13 01:09:39 PM PDT 24
Finished Jun 13 01:16:51 PM PDT 24
Peak memory 199868 kb
Host smart-62ce5f07-722e-49fe-a66c-05ab3300320b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155707842 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha_vectors.155707842
Directory /workspace/7.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2324290171
Short name T335
Test name
Test status
Simulation time 8950958081 ps
CPU time 17.59 seconds
Started Jun 13 01:09:38 PM PDT 24
Finished Jun 13 01:09:56 PM PDT 24
Peak memory 199860 kb
Host smart-ede78953-1017-4e57-bc50-a9de1f5660b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324290171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2324290171
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/70.hmac_stress_all_with_rand_reset.587996535
Short name T11
Test name
Test status
Simulation time 21159172483 ps
CPU time 1586.17 seconds
Started Jun 13 01:20:10 PM PDT 24
Finished Jun 13 01:46:37 PM PDT 24
Peak memory 684284 kb
Host smart-784babfd-ea02-4bd1-a9fd-655443a38b0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587996535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.hmac_stress_all_with_rand_reset.587996535
Directory /workspace/70.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.hmac_alert_test.1635937587
Short name T375
Test name
Test status
Simulation time 12890480 ps
CPU time 0.59 seconds
Started Jun 13 01:09:38 PM PDT 24
Finished Jun 13 01:09:39 PM PDT 24
Peak memory 195552 kb
Host smart-ab419c0b-7d72-429b-beb8-4e19de534523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635937587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.1635937587
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2202451036
Short name T151
Test name
Test status
Simulation time 1714149695 ps
CPU time 20.67 seconds
Started Jun 13 01:09:45 PM PDT 24
Finished Jun 13 01:10:06 PM PDT 24
Peak memory 215588 kb
Host smart-678a1b98-466f-4bb0-954a-8ceafc72f7ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2202451036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2202451036
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1513562772
Short name T315
Test name
Test status
Simulation time 437305271 ps
CPU time 22.86 seconds
Started Jun 13 01:09:43 PM PDT 24
Finished Jun 13 01:10:07 PM PDT 24
Peak memory 199808 kb
Host smart-dbf4f1cc-8fda-439e-8e93-645d48dd8b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513562772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1513562772
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.291083414
Short name T211
Test name
Test status
Simulation time 2434909076 ps
CPU time 568.79 seconds
Started Jun 13 01:09:36 PM PDT 24
Finished Jun 13 01:19:05 PM PDT 24
Peak memory 703748 kb
Host smart-a0ee25fe-28fc-4dca-b177-0a30cb64ecfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=291083414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.291083414
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3768504321
Short name T532
Test name
Test status
Simulation time 26335367070 ps
CPU time 79.98 seconds
Started Jun 13 01:09:40 PM PDT 24
Finished Jun 13 01:11:01 PM PDT 24
Peak memory 199844 kb
Host smart-6430318c-efc8-4c3c-9bc3-3677081694b2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768504321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3768504321
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.3035311714
Short name T440
Test name
Test status
Simulation time 315553074 ps
CPU time 8.4 seconds
Started Jun 13 01:09:51 PM PDT 24
Finished Jun 13 01:10:01 PM PDT 24
Peak memory 199772 kb
Host smart-998c0b9a-9531-476b-92ed-d9002879ab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035311714 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.3035311714
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.1414401268
Short name T356
Test name
Test status
Simulation time 478050049 ps
CPU time 5.06 seconds
Started Jun 13 01:09:43 PM PDT 24
Finished Jun 13 01:09:49 PM PDT 24
Peak memory 199772 kb
Host smart-f008228a-3887-4c4b-8f0f-08a8272fc614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414401268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.1414401268
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.2668214667
Short name T561
Test name
Test status
Simulation time 51273655354 ps
CPU time 720.61 seconds
Started Jun 13 01:09:40 PM PDT 24
Finished Jun 13 01:21:42 PM PDT 24
Peak memory 224436 kb
Host smart-6f07a3a7-efce-4c24-a45c-ada0b1074c44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668214667 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.2668214667
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.1990097439
Short name T54
Test name
Test status
Simulation time 90287258 ps
CPU time 0.99 seconds
Started Jun 13 01:09:41 PM PDT 24
Finished Jun 13 01:09:44 PM PDT 24
Peak memory 199584 kb
Host smart-0fbec8de-f0be-40da-98c4-5ab0c3a79d71
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990097439 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.hmac_test_hmac_vectors.1990097439
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha_vectors.152954123
Short name T328
Test name
Test status
Simulation time 9351179176 ps
CPU time 513.41 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:18:29 PM PDT 24
Peak memory 199840 kb
Host smart-cce37739-c059-497f-9948-1d63c9434044
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152954123 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha_vectors.152954123
Directory /workspace/8.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_alert_test.3760554126
Short name T450
Test name
Test status
Simulation time 39977749 ps
CPU time 0.58 seconds
Started Jun 13 01:09:52 PM PDT 24
Finished Jun 13 01:09:55 PM PDT 24
Peak memory 194836 kb
Host smart-f37ffe08-5016-4095-b245-21286ee021f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760554126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.3760554126
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.2675056539
Short name T495
Test name
Test status
Simulation time 7123019923 ps
CPU time 37.98 seconds
Started Jun 13 01:09:53 PM PDT 24
Finished Jun 13 01:10:33 PM PDT 24
Peak memory 216160 kb
Host smart-3ee4b0ba-5f5a-46ee-a343-298bbb47f421
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2675056539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.2675056539
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.3844881438
Short name T140
Test name
Test status
Simulation time 11535058125 ps
CPU time 48.05 seconds
Started Jun 13 01:09:38 PM PDT 24
Finished Jun 13 01:10:27 PM PDT 24
Peak memory 199840 kb
Host smart-7345095e-f319-4836-bceb-b71d6d769765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844881438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.3844881438
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.510253604
Short name T586
Test name
Test status
Simulation time 486364607 ps
CPU time 9.41 seconds
Started Jun 13 01:09:40 PM PDT 24
Finished Jun 13 01:09:50 PM PDT 24
Peak memory 201032 kb
Host smart-7dc99d24-96c0-4ba5-aeb3-3e648184d55c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=510253604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.510253604
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_long_msg.3233891459
Short name T268
Test name
Test status
Simulation time 308177894 ps
CPU time 6.27 seconds
Started Jun 13 01:09:38 PM PDT 24
Finished Jun 13 01:09:45 PM PDT 24
Peak memory 199852 kb
Host smart-df21c58c-cd61-41ee-9ba2-5e7c95c95d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233891459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.3233891459
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1921834296
Short name T451
Test name
Test status
Simulation time 1722212443 ps
CPU time 8.9 seconds
Started Jun 13 01:09:42 PM PDT 24
Finished Jun 13 01:09:52 PM PDT 24
Peak memory 199844 kb
Host smart-0ef8ceaf-d973-4c9d-955f-2bf55b3465df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921834296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1921834296
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.3633785743
Short name T478
Test name
Test status
Simulation time 567997763808 ps
CPU time 4184.83 seconds
Started Jun 13 01:09:39 PM PDT 24
Finished Jun 13 02:19:25 PM PDT 24
Peak memory 884040 kb
Host smart-615cd3e0-7b2b-4586-be1d-a98ee1860959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633785743 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.3633785743
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.1666525678
Short name T418
Test name
Test status
Simulation time 170404488 ps
CPU time 1.51 seconds
Started Jun 13 01:09:40 PM PDT 24
Finished Jun 13 01:09:43 PM PDT 24
Peak memory 199792 kb
Host smart-2be6bb08-d982-4f09-8526-ce577e0c4d2c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666525678 -assert nopostproc +UVM_TESTNAME=hmac_base
_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.hmac_test_hmac_vectors.1666525678
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha_vectors.832006168
Short name T194
Test name
Test status
Simulation time 25927346610 ps
CPU time 481.79 seconds
Started Jun 13 01:09:49 PM PDT 24
Finished Jun 13 01:17:51 PM PDT 24
Peak memory 199844 kb
Host smart-86c26105-8ad8-4428-82d6-da606038ab85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832006168 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha_vectors.832006168
Directory /workspace/9.hmac_test_sha_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.667717411
Short name T352
Test name
Test status
Simulation time 6074105503 ps
CPU time 92.69 seconds
Started Jun 13 01:09:48 PM PDT 24
Finished Jun 13 01:11:21 PM PDT 24
Peak memory 199824 kb
Host smart-7c9e48ba-cd8a-47ca-b58a-e4b41b56bef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667717411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.667717411
Directory /workspace/9.hmac_wipe_secret/latest
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