Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

85352123

1

T1

2358

T2

32697

T3

54083

full_word

89210353

1

T1

13488

T2

29138

T3

52570

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	174562116	1			T1	15846		T2	61835		T3	106653
auto[TlIntgErrCmd]	124	1			T37	7		T38	11		T39	12
auto[TlIntgErrData]	106	1			T37	8		T38	6		T39	8
auto[TlIntgErrBoth]	130	1			T37	5		T38	13		T39	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

70498940

1

T1

1262

T2

29178

T3

48839

auto[1]

104063536

1

T1

14584

T2

32657

T3

57814

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	35453042	1			T1	848		T2	14747		T3	24594
auto[TlIntgErrNone]	partial	auto[1]	49898748	1			T1	1510		T2	17950		T3	29489
auto[TlIntgErrNone]	full_word	auto[0]	35045743	1			T1	414		T2	14431		T3	24245
auto[TlIntgErrNone]	full_word	auto[1]	54164583	1			T1	13074		T2	14707		T3	28325
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T37	3		T38	4		T39	4
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T37	4		T38	4		T39	8
auto[TlIntgErrCmd]	full_word	auto[0]	7	1			T38	2		T146	1		T147	2
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T38	1		T148	1		T149	1
auto[TlIntgErrData]	partial	auto[0]	44	1			T37	4		T38	2		T39	4
auto[TlIntgErrData]	partial	auto[1]	52	1			T37	2		T38	4		T39	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T39	1		T145	1		T148	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T37	2		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T37	1		T38	5		T39	5
auto[TlIntgErrBoth]	partial	auto[1]	71	1			T37	4		T38	7		T39	4
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T148	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T38	1		T39	1		T83	1