Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.42	100.00	93.75	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1025622689	114146	0	0
intr_enable_rd_A	1025622689	2813	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025622689	114146	0	0
T37	7517	11	0	0
T38	11692	8	0	0
T39	21707	4	0	0
T56	6776	1049	0	0
T57	10230	23	0	0
T58	10551	16	0	0
T59	5658	7	0	0
T69	4163	14	0	0
T71	9268	4	0	0
T72	11129	8	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1025622689	2813	0	0
T40	19906	0	0	0
T45	1479	0	0	0
T46	134908	0	0	0
T47	151200	0	0	0
T57	0	32	0	0
T58	0	35	0	0
T65	392596	26	0	0
T66	0	15	0	0
T69	0	2	0	0
T73	0	10	0	0
T74	0	53	0	0
T75	0	18	0	0
T76	0	10	0	0
T77	0	26	0	0
T78	58111	0	0	0
T79	93828	0	0	0
T80	305587	0	0	0
T81	23079	0	0	0
T82	106641	0	0	0