Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	88000324	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

92007915

1

T1

702140

T2

29843

T3

9

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	72696806	1			T1	548657		T2	26157		T3	1
values[0x0]	50546301	1			T1	400863		T2	17137		T3	12
values[0x1]	56765132	1			T1	450358		T2	21363		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66019751	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

113988488

1

T1

875588

T2

39147

T3

9

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	517172	1			T1	5372		T2	261		T4	2
valid_sources[0x01]	2032126	1			T1	5445		T2	208		T8	7
valid_sources[0x02]	520969	1			T1	5507		T2	236		T8	10
valid_sources[0x03]	521769	1			T1	5595		T2	264		T8	5
valid_sources[0x04]	2107899	1			T1	5318		T2	282		T8	3
valid_sources[0x05]	518518	1			T1	5592		T2	234		T4	3
valid_sources[0x06]	519107	1			T1	5504		T2	245		T4	3
valid_sources[0x07]	517435	1			T1	5426		T2	239		T8	7
valid_sources[0x08]	2087791	1			T1	5379		T2	243		T4	1
valid_sources[0x09]	2267770	1			T1	5577		T2	240		T4	1
valid_sources[0x0a]	516843	1			T1	5289		T2	272		T4	3
valid_sources[0x0b]	515426	1			T1	5322		T2	261		T4	4
valid_sources[0x0c]	2118560	1			T1	5485		T2	274		T4	3
valid_sources[0x0d]	518825	1			T1	5534		T2	260		T4	1
valid_sources[0x0e]	516984	1			T1	5323		T2	263		T4	3
valid_sources[0x0f]	523424	1			T1	5458		T2	280		T4	3
valid_sources[0x10]	939697	1			T1	5506		T2	230		T4	4
valid_sources[0x11]	517350	1			T1	5556		T2	245		T4	2
valid_sources[0x12]	519240	1			T1	5414		T2	265		T4	1
valid_sources[0x13]	901096	1			T1	5469		T2	252		T4	2
valid_sources[0x14]	520710	1			T1	5383		T2	235		T4	2
valid_sources[0x15]	516997	1			T1	5533		T2	269		T8	21
valid_sources[0x16]	2145637	1			T1	5410		T2	240		T4	1
valid_sources[0x17]	589094	1			T1	5609		T2	253		T4	2
valid_sources[0x18]	2201024	1			T1	5479		T2	262		T4	2
valid_sources[0x19]	519834	1			T1	5557		T2	251		T3	1
valid_sources[0x1a]	519886	1			T1	5424		T2	261		T4	3
valid_sources[0x1b]	517681	1			T1	5480		T2	278		T4	4
valid_sources[0x1c]	519317	1			T1	5405		T2	258		T4	6
valid_sources[0x1d]	519096	1			T1	5571		T2	239		T4	2
valid_sources[0x1e]	2106303	1			T1	5443		T2	275		T4	4
valid_sources[0x1f]	519375	1			T1	5396		T2	234		T4	2
valid_sources[0x20]	536843	1			T1	5431		T2	261		T4	1
valid_sources[0x21]	516154	1			T1	5374		T2	245		T4	1
valid_sources[0x22]	521624	1			T1	5475		T2	240		T4	2
valid_sources[0x23]	572672	1			T1	5358		T2	282		T4	4
valid_sources[0x24]	516291	1			T1	5455		T2	247		T4	1
valid_sources[0x25]	518243	1			T1	5523		T2	242		T9	1441
valid_sources[0x26]	518776	1			T1	5459		T2	239		T4	1
valid_sources[0x27]	513982	1			T1	5431		T2	241		T3	1
valid_sources[0x28]	519954	1			T1	5505		T2	266		T4	1
valid_sources[0x29]	516958	1			T1	5432		T2	278		T9	1532
valid_sources[0x2a]	519010	1			T1	5541		T2	255		T4	2
valid_sources[0x2b]	516364	1			T1	5568		T2	248		T4	1
valid_sources[0x2c]	522107	1			T1	5465		T2	269		T4	1
valid_sources[0x2d]	519487	1			T1	5460		T2	256		T8	17
valid_sources[0x2e]	574622	1			T1	5515		T2	246		T4	6
valid_sources[0x2f]	517483	1			T1	5398		T2	243		T4	2
valid_sources[0x30]	553919	1			T1	5660		T2	258		T4	3
valid_sources[0x31]	518723	1			T1	5360		T2	264		T4	1
valid_sources[0x32]	518605	1			T1	5520		T2	252		T4	2
valid_sources[0x33]	547892	1			T1	5624		T2	239		T4	2
valid_sources[0x34]	2049405	1			T1	5379		T2	274		T8	13
valid_sources[0x35]	517056	1			T1	5393		T2	292		T4	1
valid_sources[0x36]	549546	1			T1	5561		T2	237		T4	2
valid_sources[0x37]	526823	1			T1	5385		T2	265		T8	71
valid_sources[0x38]	591332	1			T1	5441		T2	268		T8	45
valid_sources[0x39]	518765	1			T1	5520		T2	258		T8	12
valid_sources[0x3a]	526434	1			T1	5227		T2	250		T3	3
valid_sources[0x3b]	518969	1			T1	5369		T2	270		T4	2
valid_sources[0x3c]	517016	1			T1	5443		T2	248		T3	2
valid_sources[0x3d]	536515	1			T1	5482		T2	260		T4	5
valid_sources[0x3e]	517406	1			T1	5478		T2	251		T4	1
valid_sources[0x3f]	599365	1			T1	5462		T2	239		T8	24
valid_sources[0x40]	518516	1			T1	5453		T2	273		T4	2
valid_sources[0x41]	518608	1			T1	5465		T2	256		T4	1
valid_sources[0x42]	603104	1			T1	5691		T2	239		T4	1
valid_sources[0x43]	522647	1			T1	5505		T2	231		T4	2
valid_sources[0x44]	563550	1			T1	5427		T2	250		T4	3
valid_sources[0x45]	519390	1			T1	5429		T2	228		T4	1
valid_sources[0x46]	534193	1			T1	5576		T2	237		T4	2
valid_sources[0x47]	520044	1			T1	5477		T2	273		T9	1448
valid_sources[0x48]	2049881	1			T1	5593		T2	256		T4	2
valid_sources[0x49]	898078	1			T1	5435		T2	272		T4	2
valid_sources[0x4a]	517302	1			T1	5610		T2	239		T4	1
valid_sources[0x4b]	518235	1			T1	5392		T2	251		T4	2
valid_sources[0x4c]	516340	1			T1	5452		T2	261		T9	1552
valid_sources[0x4d]	2024038	1			T1	5492		T2	250		T4	2
valid_sources[0x4e]	519401	1			T1	5404		T2	268		T4	2
valid_sources[0x4f]	521557	1			T1	5469		T2	260		T4	1
valid_sources[0x50]	517480	1			T1	5398		T2	263		T9	1512
valid_sources[0x51]	546209	1			T1	5478		T2	241		T4	2
valid_sources[0x52]	540468	1			T1	5477		T2	272		T4	1
valid_sources[0x53]	581136	1			T1	5433		T2	219		T4	1
valid_sources[0x54]	517647	1			T1	5598		T2	234		T4	2
valid_sources[0x55]	519069	1			T1	5373		T2	245		T8	5
valid_sources[0x56]	518766	1			T1	5427		T2	214		T4	3
valid_sources[0x57]	520758	1			T1	5400		T2	275		T4	2
valid_sources[0x58]	518700	1			T1	5478		T2	257		T4	1
valid_sources[0x59]	519430	1			T1	5491		T2	255		T4	1
valid_sources[0x5a]	521175	1			T1	5451		T2	286		T4	1
valid_sources[0x5b]	517873	1			T1	5577		T2	215		T4	1
valid_sources[0x5c]	520577	1			T1	5445		T2	260		T4	3
valid_sources[0x5d]	2113464	1			T1	5237		T2	239		T4	2
valid_sources[0x5e]	561736	1			T1	5462		T2	246		T4	2
valid_sources[0x5f]	521777	1			T1	5546		T2	232		T4	3
valid_sources[0x60]	517963	1			T1	5561		T2	255		T4	1
valid_sources[0x61]	522280	1			T1	5300		T2	240		T4	1
valid_sources[0x62]	554662	1			T1	5375		T2	238		T9	1515
valid_sources[0x63]	924750	1			T1	5562		T2	228		T4	2
valid_sources[0x64]	523203	1			T1	5515		T2	270		T8	34
valid_sources[0x65]	518991	1			T1	5476		T2	242		T4	1
valid_sources[0x66]	557924	1			T1	5420		T2	261		T4	1
valid_sources[0x67]	549387	1			T1	5418		T2	258		T4	3
valid_sources[0x68]	518123	1			T1	5549		T2	218		T4	2
valid_sources[0x69]	1278157	1			T1	5282		T2	280		T4	4
valid_sources[0x6a]	522520	1			T1	5395		T2	248		T8	1
valid_sources[0x6b]	603532	1			T1	5559		T2	277		T3	3
valid_sources[0x6c]	559873	1			T1	5453		T2	277		T4	3
valid_sources[0x6d]	514617	1			T1	5369		T2	273		T4	1
valid_sources[0x6e]	551502	1			T1	5505		T2	262		T4	1
valid_sources[0x6f]	516125	1			T1	5344		T2	265		T4	1
valid_sources[0x70]	528323	1			T1	5503		T2	226		T4	4
valid_sources[0x71]	514353	1			T1	5603		T2	240		T4	2
valid_sources[0x72]	2223956	1			T1	5418		T2	279		T4	3
valid_sources[0x73]	517736	1			T1	5378		T2	272		T4	2
valid_sources[0x74]	517842	1			T1	5613		T2	260		T4	2
valid_sources[0x75]	2065416	1			T1	5560		T2	247		T4	3
valid_sources[0x76]	519547	1			T1	5300		T2	239		T4	3
valid_sources[0x77]	515611	1			T1	5432		T2	244		T4	3
valid_sources[0x78]	518015	1			T1	5512		T2	234		T4	1
valid_sources[0x79]	519629	1			T1	5603		T2	255		T8	34
valid_sources[0x7a]	520539	1			T1	5569		T2	228		T8	8
valid_sources[0x7b]	544625	1			T1	5441		T2	228		T4	2
valid_sources[0x7c]	517184	1			T1	5441		T2	255		T4	3
valid_sources[0x7d]	519473	1			T1	5575		T2	251		T4	1
valid_sources[0x7e]	519538	1			T1	5635		T2	287		T4	1
valid_sources[0x7f]	517154	1			T1	5423		T2	257		T4	2
valid_sources[0x80]	1876005	1			T1	5589		T2	287		T4	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36196597

1

T1

274439

T2

13027

T3

1

values[0x0]

all_enables

biggest_size

29642112

1

T1

229761

T2

8976

T3

6

values[0x1]

all_enables

biggest_size

26169206

1

T1

197940

T2

7840

T3

2