Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

88284242

1

T1

697738

T2

34814

T3

15

full_word

92026087

1

T1

702140

T2

29843

T3

9

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	180309959	1			T1	139987		T2	64657		T3	24
auto[TlIntgErrCmd]	129	1			T46	3		T48	5		T62	3
auto[TlIntgErrData]	116	1			T46	10		T48	4		T62	3
auto[TlIntgErrBoth]	125	1			T46	7		T48	1		T62	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72794075

1

T1

548657

T2

26157

T3

1

auto[1]

107516254

1

T1

851221

T2

38500

T3

23

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	36590059	1			T1	274218		T2	13130		T4	99
auto[TlIntgErrNone]	partial	auto[1]	51693840	1			T1	423520		T2	21684		T3	15
auto[TlIntgErrNone]	full_word	auto[0]	36203857	1			T1	274439		T2	13027		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	55822203	1			T1	427701		T2	16816		T3	8
auto[TlIntgErrCmd]	partial	auto[0]	53	1			T46	1		T48	1		T62	1
auto[TlIntgErrCmd]	partial	auto[1]	68	1			T46	2		T48	4		T62	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T76	1		T75	1		T145	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T144	1		T146	1		T147	1
auto[TlIntgErrData]	partial	auto[0]	61	1			T46	6		T48	3		T62	2
auto[TlIntgErrData]	partial	auto[1]	49	1			T46	4		T48	1		T62	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T144	1		T145	1		T147	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T77	1		T75	1		T146	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T46	2		T48	1		T62	1
auto[TlIntgErrBoth]	partial	auto[1]	76	1			T46	4		T62	2		T76	8
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T62	1		T144	1		T148	1
auto[TlIntgErrBoth]	full_word	auto[1]	10	1			T46	1		T76	1		T77	3