Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.42	100.00	93.75	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1075934273	160469	0	0
intr_enable_rd_A	1075934273	3045	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075934273	160469	0	0
T46	9409	4	0	0
T47	10745	763	0	0
T48	4480	2	0	0
T60	3626	5	0	0
T61	3362	15	0	0
T62	7771	3	0	0
T63	11809	527	0	0
T76	21938	8	0	0
T77	12811	6	0	0
T78	4859	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1075934273	3045	0	0
T69	420577	10	0	0
T70	0	13	0	0
T79	0	13	0	0
T80	0	34	0	0
T81	0	31	0	0
T82	0	228	0	0
T83	0	27	0	0
T84	0	5	0	0
T85	0	77	0	0
T86	0	3	0	0
T87	251979	0	0	0
T88	25919	0	0	0
T89	1222	0	0	0
T90	271461	0	0	0
T91	224607	0	0	0
T92	954256	0	0	0
T93	1086	0	0	0
T94	27029	0	0	0
T95	1433	0	0	0