Line Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
1 |
1 |
64 |
1 |
1 |
67 |
1 |
1 |
69 |
1 |
1 |
95 |
1 |
1 |
96 |
1 |
1 |
98 |
1 |
1 |
Line Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 10 | 100.00 |
ALWAYS | 75 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
75 |
2 |
2 |
76 |
2 |
2 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
83 |
1 |
1 |
88 |
1 |
1 |
95 |
1 |
1 |
96 |
1 |
1 |
98 |
1 |
1 |
Cond Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T68,T69,T70 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T68,T69,T70 |
1 | 1 | Covered | T68,T69,T70 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T4,T11,T5 |
1 | 1 | Covered | T1,T2,T4 |
Cond Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T68,T69,T70 |
1 | 0 | Covered | T5,T7,T17 |
LINE 83
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T68,T69,T70 |
1 | 0 | Covered | T5,T7,T17 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T68,T69,T121 |
1 | 1 | Covered | T5,T7,T17 |
Branch Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 95 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
75 |
3 |
3 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 75 if ((!rst_ni))
-2-: 76 if (reg2hw_intr_test_qe_i)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T68,T69,T70 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_intr_hw
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
1830 |
1830 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1830 |
1830 |
0 |
0 |
T1 |
3 |
3 |
0 |
0 |
T2 |
3 |
3 |
0 |
0 |
T3 |
3 |
3 |
0 |
0 |
T4 |
3 |
3 |
0 |
0 |
T8 |
3 |
3 |
0 |
0 |
T9 |
3 |
3 |
0 |
0 |
T10 |
3 |
3 |
0 |
0 |
T11 |
3 |
3 |
0 |
0 |
T12 |
3 |
3 |
0 |
0 |
T13 |
3 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.intr_hw_hmac_done
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
1 |
1 |
64 |
1 |
1 |
67 |
1 |
1 |
69 |
1 |
1 |
95 |
1 |
1 |
96 |
1 |
1 |
98 |
1 |
1 |
Cond Coverage for Instance : tb.dut.intr_hw_hmac_done
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T68,T69,T70 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T68,T69,T70 |
1 | 1 | Covered | T68,T69,T70 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T5,T53,T122 |
1 | 1 | Covered | T1,T2,T4 |
Branch Coverage for Instance : tb.dut.intr_hw_hmac_done
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 95 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.intr_hw_hmac_done
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
610 |
610 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
610 |
610 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.intr_hw_fifo_empty
| Line No. | Total | Covered | Percent |
TOTAL | | 10 | 10 | 100.00 |
ALWAYS | 75 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 83 | 1 | 1 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
75 |
2 |
2 |
76 |
2 |
2 |
|
|
|
MISSING_ELSE |
81 |
1 |
1 |
83 |
1 |
1 |
88 |
1 |
1 |
95 |
1 |
1 |
96 |
1 |
1 |
98 |
1 |
1 |
Cond Coverage for Instance : tb.dut.intr_hw_fifo_empty
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T68,T69,T70 |
1 | 0 | Covered | T5,T7,T17 |
LINE 83
EXPRESSION (event_intr_i | g_intr_status.test_q)
------1----- ----------2---------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T68,T69,T70 |
1 | 0 | Covered | T5,T7,T17 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T68,T69,T121 |
1 | 1 | Covered | T5,T7,T17 |
Branch Coverage for Instance : tb.dut.intr_hw_fifo_empty
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
IF |
75 |
3 |
3 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 75 if ((!rst_ni))
-2-: 76 if (reg2hw_intr_test_qe_i)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T68,T69,T70 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 95 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.intr_hw_fifo_empty
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
610 |
610 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
610 |
610 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.intr_hw_hmac_err
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
CONT_ASSIGN | 62 | 1 | 1 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 67 | 1 | 1 | 100.00 |
CONT_ASSIGN | 69 | 1 | 1 | 100.00 |
ALWAYS | 95 | 3 | 3 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
62 |
1 |
1 |
64 |
1 |
1 |
67 |
1 |
1 |
69 |
1 |
1 |
95 |
1 |
1 |
96 |
1 |
1 |
98 |
1 |
1 |
Cond Coverage for Instance : tb.dut.intr_hw_hmac_err
| Total | Covered | Percent |
Conditions | 12 | 12 | 100.00 |
Logical | 12 | 12 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 62
EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
-----------------------------1---------------------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T68,T69,T70 |
LINE 62
SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
----------------1---------------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T68,T69,T70 |
1 | 1 | Covered | T68,T69,T70 |
LINE 67
EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
-----------1---------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T4 |
1 | 0 | Covered | T1,T2,T4 |
LINE 98
EXPRESSION (status & reg2hw_intr_enable_q_i)
---1-- -----------2----------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T8 |
1 | 0 | Covered | T4,T11,T55 |
1 | 1 | Covered | T1,T2,T8 |
Branch Coverage for Instance : tb.dut.intr_hw_hmac_err
| Line No. | Total | Covered | Percent |
Branches |
|
2 |
2 |
100.00 |
IF |
95 |
2 |
2 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_intr_hw.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 95 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.intr_hw_hmac_err
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
IntrTKind_A |
610 |
610 |
0 |
0 |
IntrTKind_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
610 |
610 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |
T11 |
1 |
1 |
0 |
0 |
T12 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |