Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	88567485	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

92646560

1

T1

2840

T2

7580

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	72951002	1			T1	2333		T2	6733		T3	1
values[0x0]	51010704	1			T1	1249		T2	4284		T3	10
values[0x1]	57252339	1			T1	1461		T2	5276		T3	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66437486	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

114776559

1

T1

3414

T2

9875

T3

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	506307	1			T1	23		T2	62		T4	29
valid_sources[0x01]	505458	1			T1	18		T2	57		T4	25
valid_sources[0x02]	505353	1			T1	26		T2	61		T4	28
valid_sources[0x03]	606262	1			T1	15		T2	65		T4	17
valid_sources[0x04]	507293	1			T1	10		T2	53		T4	59
valid_sources[0x05]	1951242	1			T1	12		T2	63		T3	1
valid_sources[0x06]	554457	1			T1	16		T2	69		T4	40
valid_sources[0x07]	505620	1			T1	19		T2	62		T4	11
valid_sources[0x08]	2059187	1			T1	10		T2	59		T4	59
valid_sources[0x09]	505565	1			T1	15		T2	57		T4	13
valid_sources[0x0a]	504938	1			T1	13		T2	66		T4	22
valid_sources[0x0b]	504405	1			T1	20		T2	78		T4	78
valid_sources[0x0c]	544311	1			T1	16		T2	50		T4	19
valid_sources[0x0d]	558530	1			T1	33		T2	77		T4	33
valid_sources[0x0e]	591727	1			T1	16		T2	78		T3	4
valid_sources[0x0f]	503578	1			T1	27		T2	43		T4	14
valid_sources[0x10]	1878154	1			T1	16		T2	71		T4	10
valid_sources[0x11]	644372	1			T1	30		T2	72		T4	41
valid_sources[0x12]	504939	1			T1	19		T2	43		T4	44
valid_sources[0x13]	588211	1			T1	22		T2	63		T4	27
valid_sources[0x14]	930687	1			T1	21		T2	61		T4	38
valid_sources[0x15]	504205	1			T1	16		T2	64		T4	31
valid_sources[0x16]	2167406	1			T1	10		T2	54		T4	30
valid_sources[0x17]	506134	1			T1	10		T2	68		T4	28
valid_sources[0x18]	501490	1			T1	19		T2	62		T4	49
valid_sources[0x19]	889456	1			T1	33		T2	65		T4	27
valid_sources[0x1a]	505777	1			T1	21		T2	63		T4	40
valid_sources[0x1b]	505979	1			T1	22		T2	75		T4	26
valid_sources[0x1c]	535855	1			T1	17		T2	65		T4	69
valid_sources[0x1d]	514258	1			T1	23		T2	68		T4	21
valid_sources[0x1e]	524036	1			T1	19		T2	63		T4	37
valid_sources[0x1f]	613641	1			T1	16		T2	46		T4	49
valid_sources[0x20]	505641	1			T1	24		T2	59		T4	70
valid_sources[0x21]	506343	1			T1	12		T2	75		T4	5
valid_sources[0x22]	507957	1			T1	33		T2	47		T4	28
valid_sources[0x23]	504757	1			T1	9		T2	49		T4	28
valid_sources[0x24]	505860	1			T1	8		T2	53		T3	1
valid_sources[0x25]	503990	1			T1	15		T2	65		T4	47
valid_sources[0x26]	503391	1			T1	31		T2	64		T4	21
valid_sources[0x27]	503074	1			T1	29		T2	64		T4	41
valid_sources[0x28]	505234	1			T1	16		T2	55		T4	4
valid_sources[0x29]	508499	1			T1	25		T2	76		T4	72
valid_sources[0x2a]	506425	1			T1	19		T2	64		T4	23
valid_sources[0x2b]	507492	1			T1	14		T2	68		T4	104
valid_sources[0x2c]	589226	1			T1	17		T2	68		T4	44
valid_sources[0x2d]	514807	1			T1	19		T2	73		T4	21
valid_sources[0x2e]	507915	1			T1	12		T2	64		T4	34
valid_sources[0x2f]	504138	1			T1	14		T2	54		T4	49
valid_sources[0x30]	532996	1			T1	22		T2	73		T4	83
valid_sources[0x31]	507950	1			T1	19		T2	61		T4	41
valid_sources[0x32]	501649	1			T1	30		T2	52		T4	36
valid_sources[0x33]	544588	1			T1	17		T2	54		T4	59
valid_sources[0x34]	506301	1			T1	4		T2	58		T4	38
valid_sources[0x35]	509520	1			T1	27		T2	48		T4	52
valid_sources[0x36]	505327	1			T1	17		T2	83		T4	26
valid_sources[0x37]	504825	1			T1	40		T2	67		T4	46
valid_sources[0x38]	569895	1			T1	13		T2	67		T4	37
valid_sources[0x39]	501152	1			T1	17		T2	69		T4	16
valid_sources[0x3a]	502346	1			T1	21		T2	55		T4	65
valid_sources[0x3b]	508038	1			T1	27		T2	62		T4	53
valid_sources[0x3c]	502264	1			T1	16		T2	89		T4	13
valid_sources[0x3d]	510264	1			T1	21		T2	65		T4	50
valid_sources[0x3e]	506114	1			T1	14		T2	74		T4	52
valid_sources[0x3f]	505913	1			T1	17		T2	68		T4	23
valid_sources[0x40]	505136	1			T1	8		T2	67		T4	37
valid_sources[0x41]	508573	1			T1	22		T2	54		T4	54
valid_sources[0x42]	509381	1			T1	11		T2	56		T4	8
valid_sources[0x43]	502731	1			T1	20		T2	57		T4	19
valid_sources[0x44]	504607	1			T1	12		T2	57		T4	72
valid_sources[0x45]	894587	1			T1	17		T2	63		T4	19
valid_sources[0x46]	503930	1			T1	4		T2	62		T4	7
valid_sources[0x47]	3417723	1			T1	22		T2	77		T3	2
valid_sources[0x48]	503849	1			T1	24		T2	70		T4	60
valid_sources[0x49]	503806	1			T1	19		T2	65		T4	19
valid_sources[0x4a]	507173	1			T1	9		T2	77		T4	34
valid_sources[0x4b]	501035	1			T1	17		T2	74		T4	63
valid_sources[0x4c]	505344	1			T1	33		T2	51		T4	6
valid_sources[0x4d]	503615	1			T1	17		T2	65		T4	33
valid_sources[0x4e]	1935238	1			T1	23		T2	71		T4	54
valid_sources[0x4f]	509062	1			T1	20		T2	66		T4	28
valid_sources[0x50]	2019710	1			T1	12		T2	58		T4	41
valid_sources[0x51]	505597	1			T1	15		T2	72		T4	31
valid_sources[0x52]	2020036	1			T1	37		T2	65		T4	41
valid_sources[0x53]	506032	1			T1	22		T2	72		T4	17
valid_sources[0x54]	504656	1			T1	26		T2	53		T4	68
valid_sources[0x55]	507168	1			T1	34		T2	67		T4	41
valid_sources[0x56]	522161	1			T1	16		T2	66		T4	27
valid_sources[0x57]	508686	1			T1	27		T2	69		T4	83
valid_sources[0x58]	505671	1			T1	12		T2	62		T4	39
valid_sources[0x59]	501589	1			T1	12		T2	54		T4	39
valid_sources[0x5a]	503779	1			T1	14		T2	40		T4	47
valid_sources[0x5b]	504333	1			T1	29		T2	58		T4	71
valid_sources[0x5c]	505299	1			T1	17		T2	52		T4	21
valid_sources[0x5d]	526324	1			T1	44		T2	68		T4	65
valid_sources[0x5e]	626890	1			T1	29		T2	69		T4	28
valid_sources[0x5f]	502248	1			T1	25		T2	61		T4	39
valid_sources[0x60]	521665	1			T1	20		T2	72		T4	43
valid_sources[0x61]	508361	1			T1	10		T2	66		T4	55
valid_sources[0x62]	505534	1			T1	30		T2	69		T4	21
valid_sources[0x63]	532998	1			T1	15		T2	62		T4	37
valid_sources[0x64]	508499	1			T1	27		T2	65		T4	24
valid_sources[0x65]	506589	1			T1	21		T2	60		T4	66
valid_sources[0x66]	2078146	1			T1	11		T2	56		T4	42
valid_sources[0x67]	500867	1			T1	15		T2	63		T4	27
valid_sources[0x68]	531977	1			T1	25		T2	67		T4	18
valid_sources[0x69]	505638	1			T1	26		T2	68		T4	31
valid_sources[0x6a]	505857	1			T1	14		T2	59		T4	24
valid_sources[0x6b]	506611	1			T1	18		T2	61		T4	30
valid_sources[0x6c]	878351	1			T1	15		T2	57		T4	32
valid_sources[0x6d]	501939	1			T1	9		T2	49		T4	26
valid_sources[0x6e]	509721	1			T1	27		T2	63		T4	61
valid_sources[0x6f]	897232	1			T1	22		T2	51		T4	55
valid_sources[0x70]	508662	1			T1	7		T2	68		T4	17
valid_sources[0x71]	506285	1			T1	8		T2	72		T4	45
valid_sources[0x72]	2164644	1			T1	22		T2	67		T4	36
valid_sources[0x73]	503053	1			T1	18		T2	55		T4	59
valid_sources[0x74]	568465	1			T1	21		T2	67		T4	46
valid_sources[0x75]	507070	1			T1	12		T2	55		T4	47
valid_sources[0x76]	555198	1			T1	15		T2	67		T4	30
valid_sources[0x77]	621115	1			T1	33		T2	80		T4	18
valid_sources[0x78]	503698	1			T1	21		T2	60		T3	11
valid_sources[0x79]	1939134	1			T1	16		T2	58		T4	44
valid_sources[0x7a]	503403	1			T1	29		T2	92		T4	43
valid_sources[0x7b]	1003002	1			T1	7		T2	67		T4	30
valid_sources[0x7c]	509613	1			T1	20		T2	65		T4	32
valid_sources[0x7d]	507373	1			T1	32		T2	55		T4	25
valid_sources[0x7e]	563413	1			T1	17		T2	69		T4	21
valid_sources[0x7f]	542211	1			T1	22		T2	58		T4	36
valid_sources[0x80]	507088	1			T1	15		T2	80		T4	81

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36330801

1

T1

1104

T2

3342

T3

1

values[0x0]

all_enables

biggest_size

29929802

1

T1

888

T2

2233

T3

5

values[0x1]

all_enables

biggest_size

26385957

1

T1

848

T2

2005

T3

2