Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

89356023

1

T1

2203

T2

8713

T3

14

full_word

92698092

1

T1

2840

T2

7580

T3

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	182053715	1			T1	5043		T2	16293		T3	22
auto[TlIntgErrCmd]	129	1			T41	6		T59	9		T60	4
auto[TlIntgErrData]	138	1			T41	7		T59	11		T60	3
auto[TlIntgErrBoth]	133	1			T41	7		T59	10		T60	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73216496

1

T1

2333

T2

6733

T3

1

auto[1]

108837619

1

T1

2710

T2

9560

T3

21

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	36865273	1			T1	1229		T2	3391		T4	1938
auto[TlIntgErrNone]	partial	auto[1]	52490383	1			T1	974		T2	5322		T3	14
auto[TlIntgErrNone]	full_word	auto[0]	36351029	1			T1	1104		T2	3342		T3	1
auto[TlIntgErrNone]	full_word	auto[1]	56347030	1			T1	1736		T2	4238		T3	7
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T41	1		T59	5		T60	2
auto[TlIntgErrCmd]	partial	auto[1]	63	1			T41	4		T59	4		T60	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T137	1		T138	1		T139	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T41	1		T79	1		T80	1
auto[TlIntgErrData]	partial	auto[0]	72	1			T41	4		T59	5		T60	1
auto[TlIntgErrData]	partial	auto[1]	53	1			T41	3		T59	5		T60	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T79	1		T137	1		T140	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T59	1		T79	2		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	49	1			T41	5		T59	2		T60	1
auto[TlIntgErrBoth]	partial	auto[1]	73	1			T41	2		T59	6		T60	2
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T59	2		T79	1		T80	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T81	1		T80	1		T136	1