Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.42	100.00	93.75	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1106425346	452229	0	0
intr_enable_rd_A	1106425346	3391	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106425346	452229	0	0
T41	10945	6	0	0
T42	11882	642	0	0
T43	3776	16	0	0
T57	3818	9	0	0
T58	261728	107425	0	0
T59	12191	10	0	0
T60	9173	3	0	0
T61	1980	11	0	0
T62	752299	186513	0	0
T67	6540	13	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1106425346	3391	0	0
T27	128892	27	0	0
T28	513283	0	0	0
T44	6283	0	0	0
T57	0	11	0	0
T60	0	51	0	0
T62	0	83	0	0
T64	0	87	0	0
T67	0	23	0	0
T68	0	12	0	0
T69	0	8	0	0
T70	0	1	0	0
T71	0	84	0	0
T72	219505	0	0	0
T73	100730	0	0	0
T74	6004	0	0	0
T75	160573	0	0	0
T76	86292	0	0	0
T77	237811	0	0	0
T78	114276	0	0	0