Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	87797553	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

92051259

1

T1

37490

T2

200562

T3

6414

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	72753385	1			T1	28508		T2	160077		T3	5779
values[0x0]	50438320	1			T1	16781		T2	108149		T3	3695
values[0x1]	56657107	1			T1	16808		T2	120703		T3	4702

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	65838479	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

114010333

1

T1

45719

T2

247274

T3

8541

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	575923	1			T4	1571		T12	6066		T18	1218
valid_sources[0x01]	587605	1			T4	1505		T12	6009		T18	1364
valid_sources[0x02]	571300	1			T4	1561		T12	6012		T18	1421
valid_sources[0x03]	639857	1			T4	1491		T8	3		T12	6014
valid_sources[0x04]	621575	1			T4	1514		T8	1		T12	5928
valid_sources[0x05]	570058	1			T4	1611		T12	6057		T18	1375
valid_sources[0x06]	586141	1			T4	1496		T8	5		T12	5975
valid_sources[0x07]	572301	1			T4	1606		T12	5950		T18	1698
valid_sources[0x08]	568619	1			T4	1593		T8	1		T12	5960
valid_sources[0x09]	572571	1			T4	1588		T8	12		T12	6064
valid_sources[0x0a]	709800	1			T4	1579		T12	6058		T18	1570
valid_sources[0x0b]	572611	1			T4	1526		T12	5968		T18	1409
valid_sources[0x0c]	577378	1			T4	1562		T8	1		T12	6010
valid_sources[0x0d]	568225	1			T4	1610		T12	5926		T18	1608
valid_sources[0x0e]	570704	1			T4	1537		T8	4		T12	5974
valid_sources[0x0f]	924118	1			T4	1579		T12	5945		T18	1553
valid_sources[0x10]	567042	1			T4	1567		T8	8		T12	6023
valid_sources[0x11]	574563	1			T4	1569		T8	5		T12	5845
valid_sources[0x12]	575118	1			T4	1509		T12	6014		T18	1571
valid_sources[0x13]	573195	1			T4	1585		T12	5945		T18	1513
valid_sources[0x14]	567200	1			T4	1539		T12	5967		T18	1520
valid_sources[0x15]	2142633	1			T4	1567		T8	2		T12	6171
valid_sources[0x16]	567220	1			T4	1621		T12	6125		T18	1385
valid_sources[0x17]	569615	1			T4	1618		T12	6051		T18	1383
valid_sources[0x18]	570045	1			T4	1623		T11	14		T12	6046
valid_sources[0x19]	623151	1			T4	1521		T12	6004		T18	1370
valid_sources[0x1a]	1965924	1			T4	1548		T12	5996		T18	1406
valid_sources[0x1b]	571454	1			T4	1529		T12	6012		T18	1287
valid_sources[0x1c]	588963	1			T4	1635		T12	5984		T18	1483
valid_sources[0x1d]	781578	1			T4	1510		T12	5956		T18	1695
valid_sources[0x1e]	2114805	1			T4	1689		T12	5908		T18	1427
valid_sources[0x1f]	943456	1			T4	1631		T12	6056		T13	19729
valid_sources[0x20]	587092	1			T4	1648		T12	5976		T18	1452
valid_sources[0x21]	599068	1			T4	1481		T8	8		T12	5883
valid_sources[0x22]	572560	1			T4	1535		T12	6050		T18	1538
valid_sources[0x23]	630829	1			T4	1615		T12	6052		T18	1478
valid_sources[0x24]	569182	1			T4	1620		T8	18		T12	5937
valid_sources[0x25]	675914	1			T1	62097		T4	1644		T8	1
valid_sources[0x26]	573842	1			T4	1483		T12	5743		T18	1299
valid_sources[0x27]	977071	1			T4	1706		T8	1		T12	5843
valid_sources[0x28]	570723	1			T4	1570		T12	5995		T18	1476
valid_sources[0x29]	573303	1			T4	1605		T12	6014		T18	1313
valid_sources[0x2a]	571648	1			T4	1561		T8	6		T12	5941
valid_sources[0x2b]	569084	1			T4	1624		T8	4		T12	6126
valid_sources[0x2c]	572790	1			T4	1592		T8	2		T12	6065
valid_sources[0x2d]	572170	1			T4	1574		T12	5931		T18	1259
valid_sources[0x2e]	925227	1			T4	1567		T8	2		T12	6185
valid_sources[0x2f]	601753	1			T4	1641		T8	1		T12	5964
valid_sources[0x30]	580258	1			T4	1547		T12	6010		T18	1620
valid_sources[0x31]	571531	1			T4	1636		T12	6041		T18	1345
valid_sources[0x32]	575697	1			T4	1732		T8	1		T12	5905
valid_sources[0x33]	571386	1			T4	1472		T8	2		T12	6144
valid_sources[0x34]	571594	1			T4	1547		T12	6061		T18	1587
valid_sources[0x35]	1033841	1			T2	388929		T4	1573		T12	5933
valid_sources[0x36]	610456	1			T4	1463		T8	5		T12	5954
valid_sources[0x37]	588576	1			T4	1570		T12	5808		T18	1371
valid_sources[0x38]	581345	1			T4	1532		T12	5916		T18	1493
valid_sources[0x39]	569412	1			T4	1623		T12	5830		T18	1606
valid_sources[0x3a]	618392	1			T4	1603		T8	2		T12	5920
valid_sources[0x3b]	569413	1			T4	1655		T12	6010		T18	1382
valid_sources[0x3c]	2389184	1			T4	1570		T12	5950		T18	1421
valid_sources[0x3d]	2093864	1			T4	1505		T12	5953		T18	1450
valid_sources[0x3e]	564790	1			T4	1547		T12	5998		T18	1441
valid_sources[0x3f]	569445	1			T4	1586		T8	3		T12	6109
valid_sources[0x40]	571566	1			T4	1593		T8	5		T12	6081
valid_sources[0x41]	566910	1			T4	1495		T12	6008		T18	1651
valid_sources[0x42]	569665	1			T4	1522		T12	5964		T18	1544
valid_sources[0x43]	564696	1			T4	1466		T8	4		T12	5956
valid_sources[0x44]	571348	1			T4	1552		T12	6084		T18	1429
valid_sources[0x45]	568324	1			T4	1583		T12	5990		T18	1514
valid_sources[0x46]	566026	1			T4	1481		T12	6048		T18	1399
valid_sources[0x47]	655177	1			T4	1625		T12	5986		T18	1742
valid_sources[0x48]	574612	1			T4	1521		T12	6000		T18	1436
valid_sources[0x49]	572874	1			T4	1570		T12	5889		T18	1468
valid_sources[0x4a]	921129	1			T4	1576		T12	6051		T18	1336
valid_sources[0x4b]	570638	1			T4	1482		T12	6016		T18	1816
valid_sources[0x4c]	569520	1			T4	1533		T12	5933		T18	1453
valid_sources[0x4d]	588739	1			T4	1584		T8	3		T12	6026
valid_sources[0x4e]	571143	1			T4	1507		T12	6114		T18	1563
valid_sources[0x4f]	569583	1			T4	1528		T12	6122		T18	1446
valid_sources[0x50]	572151	1			T4	1411		T12	6084		T18	1491
valid_sources[0x51]	571067	1			T4	1576		T11	13		T12	5979
valid_sources[0x52]	575458	1			T4	1444		T12	6022		T18	1562
valid_sources[0x53]	593925	1			T4	1560		T8	9		T12	5915
valid_sources[0x54]	573187	1			T4	1623		T12	6029		T18	1538
valid_sources[0x55]	576417	1			T4	1530		T12	5899		T18	1308
valid_sources[0x56]	571728	1			T4	1579		T12	5855		T18	1736
valid_sources[0x57]	570888	1			T4	1544		T12	6022		T18	1407
valid_sources[0x58]	570527	1			T4	1608		T12	6041		T18	1381
valid_sources[0x59]	568279	1			T4	1552		T8	2		T12	5897
valid_sources[0x5a]	571299	1			T4	1609		T8	1		T12	6032
valid_sources[0x5b]	569951	1			T4	1517		T8	6		T12	5994
valid_sources[0x5c]	2053902	1			T4	1563		T12	5874		T18	1472
valid_sources[0x5d]	575554	1			T4	1545		T12	5998		T18	1420
valid_sources[0x5e]	586270	1			T4	1619		T8	1		T12	5946
valid_sources[0x5f]	574665	1			T4	1680		T12	5930		T18	1438
valid_sources[0x60]	573505	1			T4	1557		T12	5974		T18	1530
valid_sources[0x61]	573848	1			T4	1526		T12	6011		T18	1324
valid_sources[0x62]	579072	1			T4	1537		T12	6002		T18	1458
valid_sources[0x63]	570642	1			T4	1555		T12	6083		T18	1626
valid_sources[0x64]	569556	1			T4	1574		T12	6015		T18	1511
valid_sources[0x65]	658237	1			T4	1563		T12	5893		T18	1155
valid_sources[0x66]	777219	1			T4	1600		T12	5938		T18	1611
valid_sources[0x67]	568235	1			T4	1505		T12	5924		T18	1416
valid_sources[0x68]	653514	1			T4	1612		T12	5983		T18	1441
valid_sources[0x69]	571065	1			T4	1527		T8	13		T12	5773
valid_sources[0x6a]	571730	1			T4	1610		T8	1		T12	5980
valid_sources[0x6b]	568521	1			T4	1489		T12	6048		T18	1392
valid_sources[0x6c]	572123	1			T4	1574		T12	6087		T18	1657
valid_sources[0x6d]	588170	1			T3	14176		T4	1488		T12	5996
valid_sources[0x6e]	567740	1			T4	1539		T12	6030		T18	1189
valid_sources[0x6f]	588221	1			T4	1592		T12	6067		T18	1610
valid_sources[0x70]	596370	1			T4	1543		T12	6052		T18	1205
valid_sources[0x71]	597784	1			T4	1509		T8	7		T12	5889
valid_sources[0x72]	565636	1			T4	1526		T12	6050		T18	1407
valid_sources[0x73]	701919	1			T4	1571		T12	5896		T18	1542
valid_sources[0x74]	572874	1			T4	1625		T12	5920		T18	1632
valid_sources[0x75]	573325	1			T4	1623		T12	6032		T18	1445
valid_sources[0x76]	565798	1			T4	1744		T12	6116		T18	1492
valid_sources[0x77]	569668	1			T4	1554		T12	5980		T18	1340
valid_sources[0x78]	573437	1			T4	1625		T8	2		T12	6038
valid_sources[0x79]	567888	1			T4	1553		T12	6100		T18	1318
valid_sources[0x7a]	573337	1			T4	1586		T12	6155		T18	1391
valid_sources[0x7b]	567820	1			T4	1509		T12	6015		T18	1745
valid_sources[0x7c]	576599	1			T4	1560		T12	5987		T18	1497
valid_sources[0x7d]	569196	1			T4	1574		T12	5926		T18	1307
valid_sources[0x7e]	568992	1			T4	1565		T8	2		T12	6091
valid_sources[0x7f]	568657	1			T4	1568		T12	6013		T18	1479
valid_sources[0x80]	570808	1			T4	1543		T12	5932		T18	1393

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

36231925

1

T1

8081

T2

80091

T3

2814

values[0x0]

all_enables

biggest_size

29636901

1

T1

14904

T2

63893

T3

1931

values[0x1]

all_enables

biggest_size

26182433

1

T1

14505

T2

56578

T3

1669