Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

88841542

1

T1

24607

T2

188367

T3

7762

full_word

92119074

1

T1

37490

T2

200562

T3

6414

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	180960256	1			T1	62097		T2	388929		T3	14176
auto[TlIntgErrCmd]	126	1			T46	5		T47	5		T64	7
auto[TlIntgErrData]	113	1			T46	10		T47	2		T64	2
auto[TlIntgErrBoth]	121	1			T46	5		T47	3		T64	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

73106458

1

T1

28508

T2

160077

T3

5779

auto[1]

107854158

1

T1

33589

T2

228852

T3

8397

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	36847574	1			T1	20427		T2	79986		T3	2965
auto[TlIntgErrNone]	partial	auto[1]	51993641	1			T1	4180		T2	108381		T3	4797
auto[TlIntgErrNone]	full_word	auto[0]	36258714	1			T1	8081		T2	80091		T3	2814
auto[TlIntgErrNone]	full_word	auto[1]	55860327	1			T1	29409		T2	120471		T3	3600
auto[TlIntgErrCmd]	partial	auto[0]	44	1			T46	3		T47	4		T64	4
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T46	2		T47	1		T64	2
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T64	1		T160	1		T161	2
auto[TlIntgErrCmd]	full_word	auto[1]	7	1			T158	1		T162	1		T163	3
auto[TlIntgErrData]	partial	auto[0]	59	1			T46	7		T47	2		T64	2
auto[TlIntgErrData]	partial	auto[1]	48	1			T46	3		T90	1		T92	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T91	2		T162	1		T159	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T90	1		T157	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T46	4		T47	2		T64	1
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T47	1		T90	2		T92	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T90	1		T162	1		T161	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T46	1		T158	2		T156	1