Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.42	100.00	93.75	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	992196969	599949	0	0
intr_enable_rd_A	992196969	2140	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	992196969	599949	0	0
T45	5258	17	0	0
T46	16004	6	0	0
T47	5304	4	0	0
T62	8352	27	0	0
T63	6638	640	0	0
T64	10569	4	0	0
T65	2558	443	0	0
T66	19835	868	0	0
T67	548935	139768	0	0
T68	8674	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	992196969	2140	0	0
T64	0	64	0	0
T66	0	2	0	0
T67	0	129	0	0
T69	682581	4	0	0
T73	0	5	0	0
T74	0	19	0	0
T75	0	30	0	0
T76	0	14	0	0
T77	0	56	0	0
T78	0	19	0	0
T79	246235	0	0	0
T80	222063	0	0	0
T81	411742	0	0	0
T82	269783	0	0	0
T83	259991	0	0	0
T84	116401	0	0	0
T85	43102	0	0	0
T86	876	0	0	0
T87	125185	0	0	0