Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

92313507

1

T1

62501

T2

39013

T3

1329

full_word

95175575

1

T1

51957

T2

32620

T3

1727

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	187488682	1			T1	114458		T2	71633		T3	3056
auto[TlIntgErrCmd]	138	1			T57	6		T58	8		T59	4
auto[TlIntgErrData]	131	1			T57	1		T58	12		T59	4
auto[TlIntgErrBoth]	131	1			T57	3		T58	10		T59	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

75426749

1

T1

46114

T2

29006

T3

1407

auto[1]

112062333

1

T1

68344

T2

42627

T3

1649

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	38112260	1			T1	23204		T2	14545		T3	722
auto[TlIntgErrNone]	partial	auto[1]	54200883	1			T1	39297		T2	24468		T3	607
auto[TlIntgErrNone]	full_word	auto[0]	37314311	1			T1	22910		T2	14461		T3	685
auto[TlIntgErrNone]	full_word	auto[1]	57861228	1			T1	29047		T2	18159		T3	1042
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T57	3		T58	6		T59	1
auto[TlIntgErrCmd]	partial	auto[1]	73	1			T57	2		T58	2		T59	3
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T140	1		T143	1		T144	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T57	1		T138	1		T145	1
auto[TlIntgErrData]	partial	auto[0]	59	1			T57	1		T58	8		T59	1
auto[TlIntgErrData]	partial	auto[1]	61	1			T58	3		T59	3		T138	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T145	1		T146	1		T147	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T58	1		T148	1		T141	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T57	1		T58	3		T59	1
auto[TlIntgErrBoth]	partial	auto[1]	67	1			T57	2		T58	6		T59	1
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T58	1		T146	1		T147	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T146	1		T147	2		T149	1