Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.42	100.00	93.75	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1182920633	1076728	0	0
intr_enable_rd_A	1182920633	3617	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182920633	1076728	0	0
T39	190321	558864	0	0
T40	6399	15	0	0
T41	8666	344	0	0
T57	8625	2	0	0
T58	22021	9	0	0
T60	25234	985	0	0
T61	3115	345	0	0
T64	4004	19	0	0
T65	8568	29	0	0
T66	4300	25	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1182920633	3617	0	0
T25	97900	0	0	0
T26	42882	0	0	0
T37	2057	23	0	0
T40	0	18	0	0
T57	0	50	0	0
T62	0	91	0	0
T67	0	23	0	0
T68	0	47	0	0
T69	0	17	0	0
T70	0	5	0	0
T71	0	4	0	0
T72	0	11	0	0
T73	90670	0	0	0
T74	242195	0	0	0
T75	4248	0	0	0
T76	502549	0	0	0
T77	42341	0	0	0
T78	283404	0	0	0
T79	26850	0	0	0