Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

88868526

1

T1

37955

T2

736549

T3

2374

full_word

91149706

1

T1

32636

T2

765046

T3

2080

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	180017782	1			T1	70591		T2	150159		T3	4454
auto[TlIntgErrCmd]	148	1			T39	3		T40	11		T56	12
auto[TlIntgErrData]	159	1			T39	6		T40	12		T56	3
auto[TlIntgErrBoth]	143	1			T39	1		T40	7		T56	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

72411701

1

T1

28976

T2

600199

T3

2239

auto[1]

107606531

1

T1

41615

T2

901396

T3

2215

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	36585088	1			T1	14631		T2	300166		T3	1104
auto[TlIntgErrNone]	partial	auto[1]	52283025	1			T1	23324		T2	436383		T3	1270
auto[TlIntgErrNone]	full_word	auto[0]	35826414	1			T1	14345		T2	300033		T3	1135
auto[TlIntgErrNone]	full_word	auto[1]	55323255	1			T1	18291		T2	465013		T3	945
auto[TlIntgErrCmd]	partial	auto[0]	57	1			T39	3		T40	6		T56	4
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T40	5		T56	6		T142	7
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T56	2		T147	1		T144	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T145	1		T148	1		T149	1
auto[TlIntgErrData]	partial	auto[0]	74	1			T39	3		T40	9		T56	2
auto[TlIntgErrData]	partial	auto[1]	71	1			T39	3		T40	2		T142	9
auto[TlIntgErrData]	full_word	auto[0]	6	1			T40	1		T56	1		T67	1
auto[TlIntgErrData]	full_word	auto[1]	8	1			T145	1		T150	2		T146	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T40	2		T56	3		T142	3
auto[TlIntgErrBoth]	partial	auto[1]	79	1			T39	1		T40	5		T56	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T145	1		T150	1		T146	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T143	1		T151	1		T152	1