Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
92.58 95.85 93.09 100.00 74.36 91.89 99.49 93.40


Total test records in report: 773
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html
T753 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3604142435 Jun 26 06:29:28 PM PDT 24 Jun 26 06:29:36 PM PDT 24 415163989 ps
T754 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2557026361 Jun 26 06:29:27 PM PDT 24 Jun 26 06:29:35 PM PDT 24 188928583 ps
T755 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.322678793 Jun 26 06:29:41 PM PDT 24 Jun 26 06:29:48 PM PDT 24 213919656 ps
T756 /workspace/coverage/cover_reg_top/47.hmac_intr_test.3975514677 Jun 26 06:29:44 PM PDT 24 Jun 26 06:29:48 PM PDT 24 24864782 ps
T757 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2325252587 Jun 26 06:29:54 PM PDT 24 Jun 26 06:29:56 PM PDT 24 16168001 ps
T758 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4078160969 Jun 26 06:29:46 PM PDT 24 Jun 26 06:29:51 PM PDT 24 57955191 ps
T759 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1502274079 Jun 26 06:29:41 PM PDT 24 Jun 26 06:29:48 PM PDT 24 167641911 ps
T760 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3099005644 Jun 26 06:29:31 PM PDT 24 Jun 26 06:29:40 PM PDT 24 42648686 ps
T761 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4211312924 Jun 26 06:29:31 PM PDT 24 Jun 26 06:29:40 PM PDT 24 19463503 ps
T762 /workspace/coverage/cover_reg_top/5.hmac_intr_test.1468292409 Jun 26 06:29:27 PM PDT 24 Jun 26 06:29:33 PM PDT 24 20982529 ps
T763 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2938694559 Jun 26 06:29:52 PM PDT 24 Jun 26 06:29:53 PM PDT 24 38360155 ps
T764 /workspace/coverage/cover_reg_top/20.hmac_intr_test.1529184864 Jun 26 06:29:47 PM PDT 24 Jun 26 06:29:51 PM PDT 24 12523947 ps
T765 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3548408184 Jun 26 06:30:11 PM PDT 24 Jun 26 06:30:13 PM PDT 24 16340698 ps
T97 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.848087011 Jun 26 06:29:27 PM PDT 24 Jun 26 06:29:44 PM PDT 24 151615042 ps
T766 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1029040125 Jun 26 06:29:25 PM PDT 24 Jun 26 06:29:31 PM PDT 24 15913080 ps
T767 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2200852517 Jun 26 06:29:31 PM PDT 24 Jun 26 06:29:41 PM PDT 24 764485368 ps
T98 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2058271311 Jun 26 06:29:29 PM PDT 24 Jun 26 06:29:37 PM PDT 24 47627586 ps
T768 /workspace/coverage/cover_reg_top/39.hmac_intr_test.4184728054 Jun 26 06:29:53 PM PDT 24 Jun 26 06:29:55 PM PDT 24 45196144 ps
T769 /workspace/coverage/cover_reg_top/13.hmac_intr_test.854823187 Jun 26 06:29:40 PM PDT 24 Jun 26 06:29:46 PM PDT 24 13693778 ps
T770 /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2054019158 Jun 26 06:29:32 PM PDT 24 Jun 26 06:29:47 PM PDT 24 1077521638 ps
T771 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2960204327 Jun 26 06:29:30 PM PDT 24 Jun 26 06:29:40 PM PDT 24 206554247 ps
T772 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.842972945 Jun 26 06:30:10 PM PDT 24 Jun 26 06:30:15 PM PDT 24 80890472 ps
T773 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3104037599 Jun 26 06:29:28 PM PDT 24 Jun 26 06:30:40 PM PDT 24 18210745202 ps

Test location /workspace/coverage/default/26.hmac_wipe_secret.3940048394
Short name T1
Test name
Test status
Simulation time 2097898394 ps
CPU time 88.03 seconds
Started Jun 26 06:19:19 PM PDT 24
Finished Jun 26 06:20:48 PM PDT 24
Peak memory 200124 kb
Host smart-269bf1f9-7a68-4a5f-a0a1-022475c4794d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940048394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.3940048394
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.2556324478
Short name T27
Test name
Test status
Simulation time 3337266716 ps
CPU time 60.36 seconds
Started Jun 26 06:20:19 PM PDT 24
Finished Jun 26 06:21:21 PM PDT 24
Peak memory 199984 kb
Host smart-cce10e10-97b4-41f6-917c-705a174c4f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556324478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.2556324478
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.3908260242
Short name T58
Test name
Test status
Simulation time 1351714911 ps
CPU time 3.87 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:45 PM PDT 24
Peak memory 199644 kb
Host smart-6c7a2748-c2fa-4c8f-8966-fea5acd7f885
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908260242 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.3908260242
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/default/4.hmac_stress_all.4266920150
Short name T38
Test name
Test status
Simulation time 349756670183 ps
CPU time 2096.42 seconds
Started Jun 26 06:18:21 PM PDT 24
Finished Jun 26 06:53:19 PM PDT 24
Peak memory 750712 kb
Host smart-c3346f55-2a26-4ed8-8cf7-a75cc71e5784
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266920150 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.4266920150
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.697990522
Short name T6
Test name
Test status
Simulation time 2055172467 ps
CPU time 43.61 seconds
Started Jun 26 06:18:44 PM PDT 24
Finished Jun 26 06:19:29 PM PDT 24
Peak memory 200080 kb
Host smart-0677e1be-f640-4a15-a16e-26028ccaa5e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697990522 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.697990522
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.1884476661
Short name T145
Test name
Test status
Simulation time 241338116 ps
CPU time 4.33 seconds
Started Jun 26 06:29:23 PM PDT 24
Finished Jun 26 06:29:32 PM PDT 24
Peak memory 199756 kb
Host smart-e18d24d0-b97e-480a-abda-b219ff85b014
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884476661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.1884476661
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/44.hmac_error.1667041027
Short name T30
Test name
Test status
Simulation time 2047374316 ps
CPU time 53.38 seconds
Started Jun 26 06:20:13 PM PDT 24
Finished Jun 26 06:21:08 PM PDT 24
Peak memory 200000 kb
Host smart-78c05276-5896-404d-bc6a-4a435db448f0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667041027 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.1667041027
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.891116848
Short name T36
Test name
Test status
Simulation time 49077683 ps
CPU time 0.85 seconds
Started Jun 26 06:18:20 PM PDT 24
Finished Jun 26 06:18:22 PM PDT 24
Peak memory 218180 kb
Host smart-78cc8ee2-2649-4c9b-b0cb-20348f4afa2e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891116848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.891116848
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.1519266609
Short name T131
Test name
Test status
Simulation time 1213960850 ps
CPU time 63.78 seconds
Started Jun 26 06:18:06 PM PDT 24
Finished Jun 26 06:19:10 PM PDT 24
Peak memory 200136 kb
Host smart-d0082d11-f185-41e0-9d86-054ec77d0b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519266609 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.1519266609
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_error.3427421283
Short name T113
Test name
Test status
Simulation time 13636444933 ps
CPU time 157.03 seconds
Started Jun 26 06:18:45 PM PDT 24
Finished Jun 26 06:21:23 PM PDT 24
Peak memory 200160 kb
Host smart-77f0090c-2f6a-4803-8443-2899c63fa7e6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427421283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.3427421283
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.365043472
Short name T84
Test name
Test status
Simulation time 241993078 ps
CPU time 3.07 seconds
Started Jun 26 06:29:23 PM PDT 24
Finished Jun 26 06:29:30 PM PDT 24
Peak memory 199512 kb
Host smart-67aa2775-4d23-41e1-9a60-a03e8958cadb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365043472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.365043472
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.3581158965
Short name T29
Test name
Test status
Simulation time 63596030531 ps
CPU time 1027 seconds
Started Jun 26 06:19:30 PM PDT 24
Finished Jun 26 06:36:39 PM PDT 24
Peak memory 776616 kb
Host smart-ac83f9f0-3906-40f1-ac65-52dd3f5318f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3581158965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.3581158965
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.2987642628
Short name T56
Test name
Test status
Simulation time 201429253 ps
CPU time 3.31 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 199684 kb
Host smart-0e1550db-9bef-4d39-ad42-11fcdec9f394
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987642628 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.2987642628
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/27.hmac_error.1361324652
Short name T118
Test name
Test status
Simulation time 6164544316 ps
CPU time 78.9 seconds
Started Jun 26 06:19:21 PM PDT 24
Finished Jun 26 06:20:41 PM PDT 24
Peak memory 200108 kb
Host smart-ff747c97-eddb-45cb-ae59-ac30ebf91749
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361324652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.1361324652
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_test_sha256_vectors.2623854167
Short name T9
Test name
Test status
Simulation time 34614265045 ps
CPU time 459.01 seconds
Started Jun 26 06:19:31 PM PDT 24
Finished Jun 26 06:27:11 PM PDT 24
Peak memory 200092 kb
Host smart-177748b2-b4fc-466e-ac51-7dbe39b75cb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2623854167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha256_vectors.2623854167
Directory /workspace/32.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.43893365
Short name T60
Test name
Test status
Simulation time 293667657 ps
CPU time 3.78 seconds
Started Jun 26 06:29:44 PM PDT 24
Finished Jun 26 06:29:52 PM PDT 24
Peak memory 199452 kb
Host smart-088a9963-222c-493d-b490-8e4726bb72e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43893365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.43893365
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/default/0.hmac_alert_test.1460200799
Short name T34
Test name
Test status
Simulation time 103964927 ps
CPU time 0.56 seconds
Started Jun 26 06:18:07 PM PDT 24
Finished Jun 26 06:18:09 PM PDT 24
Peak memory 195756 kb
Host smart-c5762955-9561-4e0e-8a33-36284cfb5734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460200799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.1460200799
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_stress_all.2173248684
Short name T61
Test name
Test status
Simulation time 81194677155 ps
CPU time 961.01 seconds
Started Jun 26 06:19:09 PM PDT 24
Finished Jun 26 06:35:12 PM PDT 24
Peak memory 744168 kb
Host smart-9686fdcb-9d8d-47e0-a4e8-02bc95058688
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173248684 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.hmac_stress_all.2173248684
Directory /workspace/22.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.2879596330
Short name T128
Test name
Test status
Simulation time 11614598300 ps
CPU time 56.36 seconds
Started Jun 26 06:18:35 PM PDT 24
Finished Jun 26 06:19:33 PM PDT 24
Peak memory 200208 kb
Host smart-e4f298ef-39bf-4624-8c56-09a918c354f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879596330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.2879596330
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2857999631
Short name T144
Test name
Test status
Simulation time 165839635 ps
CPU time 3.1 seconds
Started Jun 26 06:29:51 PM PDT 24
Finished Jun 26 06:29:55 PM PDT 24
Peak memory 199736 kb
Host smart-d5327e65-120a-4f6f-b5e3-670a5316ef9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857999631 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2857999631
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.4188364076
Short name T130
Test name
Test status
Simulation time 3407445221 ps
CPU time 67.05 seconds
Started Jun 26 06:19:09 PM PDT 24
Finished Jun 26 06:20:18 PM PDT 24
Peak memory 200156 kb
Host smart-ceec6215-f2ac-4900-ab68-383150db3a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188364076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.4188364076
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.216222575
Short name T134
Test name
Test status
Simulation time 338086938 ps
CPU time 32.01 seconds
Started Jun 26 06:20:09 PM PDT 24
Finished Jun 26 06:20:43 PM PDT 24
Peak memory 314592 kb
Host smart-64317127-c3a5-481b-98f3-c4d113fea737
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=216222575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.216222575
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_long_msg.2582089475
Short name T133
Test name
Test status
Simulation time 19158418934 ps
CPU time 98.49 seconds
Started Jun 26 06:20:31 PM PDT 24
Finished Jun 26 06:22:11 PM PDT 24
Peak memory 200300 kb
Host smart-01fd2fe9-5b8a-425e-9561-f33ca2f9ad7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582089475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.2582089475
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.301980703
Short name T76
Test name
Test status
Simulation time 87489832 ps
CPU time 1.56 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:31 PM PDT 24
Peak memory 199648 kb
Host smart-7410e04d-2bc2-4700-b894-feef31bc4f77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301980703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.301980703
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.22052839
Short name T78
Test name
Test status
Simulation time 423656579 ps
CPU time 10.41 seconds
Started Jun 26 06:18:05 PM PDT 24
Finished Jun 26 06:18:16 PM PDT 24
Peak memory 199844 kb
Host smart-ff087858-ef70-4c48-84ed-f9c4d132e94b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=22052839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.22052839
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.195031088
Short name T240
Test name
Test status
Simulation time 2227719502 ps
CPU time 20.86 seconds
Started Jun 26 06:19:05 PM PDT 24
Finished Jun 26 06:19:27 PM PDT 24
Peak memory 200144 kb
Host smart-170c5b2c-587c-454f-9f06-a5492b86f0a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195031088 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.195031088
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.143237946
Short name T40
Test name
Test status
Simulation time 461911693 ps
CPU time 4.15 seconds
Started Jun 26 06:29:33 PM PDT 24
Finished Jun 26 06:29:45 PM PDT 24
Peak memory 199780 kb
Host smart-eaa9c063-1c7b-4bc5-9846-b5c45a4b81c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143237946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.143237946
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.3358805712
Short name T67
Test name
Test status
Simulation time 741519459 ps
CPU time 3.31 seconds
Started Jun 26 06:29:47 PM PDT 24
Finished Jun 26 06:29:54 PM PDT 24
Peak memory 199700 kb
Host smart-0b4e0c01-1656-4c78-a491-7f77ff88391e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358805712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.3358805712
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.62652584
Short name T74
Test name
Test status
Simulation time 480703793 ps
CPU time 5.59 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 198656 kb
Host smart-99c51259-e5b3-47f9-ae84-5b8101cadcf3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62652584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.62652584
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.393940363
Short name T92
Test name
Test status
Simulation time 14300119 ps
CPU time 0.73 seconds
Started Jun 26 06:29:21 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 197832 kb
Host smart-ab89d326-5594-458d-8d8d-5bcac0973e6d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393940363 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.393940363
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.4212964184
Short name T54
Test name
Test status
Simulation time 73864130 ps
CPU time 1.18 seconds
Started Jun 26 06:29:20 PM PDT 24
Finished Jun 26 06:29:25 PM PDT 24
Peak memory 199580 kb
Host smart-c21f1ee3-dd2b-432a-a42b-abea33a7aaf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212964184 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.4212964184
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.3507744034
Short name T89
Test name
Test status
Simulation time 509108652 ps
CPU time 0.94 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:32 PM PDT 24
Peak memory 199480 kb
Host smart-3d8c1c9f-e9e1-4e3b-b343-a0974cdb257e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507744034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.3507744034
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1029040125
Short name T766
Test name
Test status
Simulation time 15913080 ps
CPU time 0.61 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:31 PM PDT 24
Peak memory 194528 kb
Host smart-0a1f58f1-d442-482b-8e9e-c97e625ae127
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029040125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1029040125
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.2939218449
Short name T686
Test name
Test status
Simulation time 110899116 ps
CPU time 2.23 seconds
Started Jun 26 06:29:23 PM PDT 24
Finished Jun 26 06:29:29 PM PDT 24
Peak memory 199600 kb
Host smart-2075e385-a8dd-43c5-87c8-3dd24c121496
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939218449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr
_outstanding.2939218449
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.2606160193
Short name T731
Test name
Test status
Simulation time 226300465 ps
CPU time 4.22 seconds
Started Jun 26 06:29:23 PM PDT 24
Finished Jun 26 06:29:32 PM PDT 24
Peak memory 199752 kb
Host smart-5db55754-51c5-4214-b9b2-c175462c1d14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606160193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.2606160193
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.2054019158
Short name T770
Test name
Test status
Simulation time 1077521638 ps
CPU time 6.29 seconds
Started Jun 26 06:29:32 PM PDT 24
Finished Jun 26 06:29:47 PM PDT 24
Peak memory 199616 kb
Host smart-322e5905-303a-4c78-b3ed-f0dcf4127878
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054019158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.2054019158
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.205489508
Short name T674
Test name
Test status
Simulation time 4572626002 ps
CPU time 11.41 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:45 PM PDT 24
Peak memory 199712 kb
Host smart-453398de-68fe-47f5-8875-cadecb5b1cf7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205489508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.205489508
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.2842383907
Short name T87
Test name
Test status
Simulation time 330683847 ps
CPU time 0.75 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:42 PM PDT 24
Peak memory 197880 kb
Host smart-626009ad-8a2a-4be0-9f35-1bc3ccebe7cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842383907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.2842383907
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.140236485
Short name T725
Test name
Test status
Simulation time 189043437085 ps
CPU time 902.1 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:44:41 PM PDT 24
Peak memory 216332 kb
Host smart-2a1819a3-7237-49f3-a003-d7f74e21b4cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140236485 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.140236485
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.1967051902
Short name T693
Test name
Test status
Simulation time 61438786 ps
CPU time 0.69 seconds
Started Jun 26 06:29:32 PM PDT 24
Finished Jun 26 06:29:41 PM PDT 24
Peak memory 197416 kb
Host smart-4dd5dbed-b5b1-46e6-b987-456a47f5a851
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967051902 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.1967051902
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.1326459881
Short name T681
Test name
Test status
Simulation time 14796731 ps
CPU time 0.59 seconds
Started Jun 26 06:29:19 PM PDT 24
Finished Jun 26 06:29:24 PM PDT 24
Peak memory 194512 kb
Host smart-99261421-30bf-45a3-a541-7f85e9d65c6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326459881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.1326459881
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3317588524
Short name T735
Test name
Test status
Simulation time 545965723 ps
CPU time 2.92 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:47 PM PDT 24
Peak memory 199724 kb
Host smart-0c7fdeb6-a09c-466a-9cc4-5fd07b362826
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317588524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3317588524
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.2568316689
Short name T152
Test name
Test status
Simulation time 940776252 ps
CPU time 4.47 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 199724 kb
Host smart-dd204074-e253-42d7-83c6-80b2a7e26986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568316689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.2568316689
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1811486819
Short name T68
Test name
Test status
Simulation time 595454899 ps
CPU time 1.84 seconds
Started Jun 26 06:29:45 PM PDT 24
Finished Jun 26 06:29:51 PM PDT 24
Peak memory 199648 kb
Host smart-cfe1dbed-ff29-4a11-9f3f-23b53947252d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811486819 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1811486819
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.830285661
Short name T90
Test name
Test status
Simulation time 23998280 ps
CPU time 0.7 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:29:38 PM PDT 24
Peak memory 197964 kb
Host smart-4a669e75-6b5f-40bb-9c27-9516a0d57c65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830285661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.830285661
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3710486645
Short name T706
Test name
Test status
Simulation time 19262607 ps
CPU time 0.59 seconds
Started Jun 26 06:29:32 PM PDT 24
Finished Jun 26 06:29:41 PM PDT 24
Peak memory 194556 kb
Host smart-a143b045-e74b-4f54-bece-3f713a0eb7f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710486645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3710486645
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.1502274079
Short name T759
Test name
Test status
Simulation time 167641911 ps
CPU time 1.97 seconds
Started Jun 26 06:29:41 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 199696 kb
Host smart-ba5a285e-9417-48c7-b205-a49538b81717
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502274079 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_cs
r_outstanding.1502274079
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3217724005
Short name T691
Test name
Test status
Simulation time 484703101 ps
CPU time 2.74 seconds
Started Jun 26 06:29:40 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 199680 kb
Host smart-7d10c7ec-a815-4d44-ac1c-4d82adb0c6f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217724005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3217724005
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.744851606
Short name T716
Test name
Test status
Simulation time 98635086 ps
CPU time 2.74 seconds
Started Jun 26 06:29:44 PM PDT 24
Finished Jun 26 06:29:51 PM PDT 24
Peak memory 199488 kb
Host smart-7cbdb7fc-8be8-40b5-b902-6eb835a701fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744851606 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.744851606
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3999539894
Short name T55
Test name
Test status
Simulation time 144031984 ps
CPU time 2.95 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:42 PM PDT 24
Peak memory 199720 kb
Host smart-8539d11c-10eb-4340-9412-8c2531f3d83d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999539894 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3999539894
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.1821305251
Short name T93
Test name
Test status
Simulation time 94765923 ps
CPU time 0.78 seconds
Started Jun 26 06:29:42 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 198888 kb
Host smart-fe2b54e8-c771-4be3-bdc4-059caefb5414
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821305251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.1821305251
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3754206350
Short name T707
Test name
Test status
Simulation time 35696426 ps
CPU time 0.59 seconds
Started Jun 26 06:29:33 PM PDT 24
Finished Jun 26 06:29:42 PM PDT 24
Peak memory 194468 kb
Host smart-8d9d0af6-7874-4bef-98ba-25b74ca2b78b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754206350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3754206350
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.322678793
Short name T755
Test name
Test status
Simulation time 213919656 ps
CPU time 2.32 seconds
Started Jun 26 06:29:41 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 199664 kb
Host smart-0c4e803b-2da0-42c0-a04f-82376d80d407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322678793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_csr
_outstanding.322678793
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.452031077
Short name T711
Test name
Test status
Simulation time 1840765400 ps
CPU time 4.09 seconds
Started Jun 26 06:29:32 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 199784 kb
Host smart-2b278276-ffa2-4109-9013-132586554ee1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452031077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.452031077
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.2246889001
Short name T146
Test name
Test status
Simulation time 253493224 ps
CPU time 4.48 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:39 PM PDT 24
Peak memory 199740 kb
Host smart-47257a8e-5437-4ec0-9cf3-1a7d4527ffe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246889001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.2246889001
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.1823337526
Short name T712
Test name
Test status
Simulation time 73491147 ps
CPU time 1.82 seconds
Started Jun 26 06:29:42 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 199772 kb
Host smart-102ca040-d58b-4db0-9764-6afc4e7f45c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823337526 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.1823337526
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.4078160969
Short name T758
Test name
Test status
Simulation time 57955191 ps
CPU time 0.73 seconds
Started Jun 26 06:29:46 PM PDT 24
Finished Jun 26 06:29:51 PM PDT 24
Peak memory 197512 kb
Host smart-8999d690-c43b-4a12-b802-760dfa338ddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078160969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.4078160969
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.3088407198
Short name T705
Test name
Test status
Simulation time 34478030 ps
CPU time 0.58 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:29:38 PM PDT 24
Peak memory 194440 kb
Host smart-5bf71be4-1128-4eda-a92d-cc6d7ca2c3c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088407198 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.3088407198
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3292250222
Short name T101
Test name
Test status
Simulation time 154768757 ps
CPU time 2.37 seconds
Started Jun 26 06:29:45 PM PDT 24
Finished Jun 26 06:29:51 PM PDT 24
Peak memory 199564 kb
Host smart-4a39ee03-f625-4590-9fd2-e1cea33954f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292250222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3292250222
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.222686244
Short name T749
Test name
Test status
Simulation time 74543637 ps
CPU time 1.85 seconds
Started Jun 26 06:29:35 PM PDT 24
Finished Jun 26 06:29:45 PM PDT 24
Peak memory 199876 kb
Host smart-536f0f2b-5d15-433c-a05f-bd99f024aff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222686244 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.222686244
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.2346900085
Short name T91
Test name
Test status
Simulation time 85285232 ps
CPU time 0.8 seconds
Started Jun 26 06:29:33 PM PDT 24
Finished Jun 26 06:29:42 PM PDT 24
Peak memory 199228 kb
Host smart-24acade6-cf9e-4da0-ba0b-ae95ae295529
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346900085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.2346900085
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.854823187
Short name T769
Test name
Test status
Simulation time 13693778 ps
CPU time 0.63 seconds
Started Jun 26 06:29:40 PM PDT 24
Finished Jun 26 06:29:46 PM PDT 24
Peak memory 194640 kb
Host smart-3160d157-5d4f-4448-89e6-30f99e8548ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854823187 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.854823187
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2352951516
Short name T104
Test name
Test status
Simulation time 119269505 ps
CPU time 2.29 seconds
Started Jun 26 06:29:43 PM PDT 24
Finished Jun 26 06:29:50 PM PDT 24
Peak memory 199640 kb
Host smart-fdf83cd2-5688-48de-8b84-291a9f01ee1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352951516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2352951516
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.2458116669
Short name T724
Test name
Test status
Simulation time 280265431 ps
CPU time 3.69 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 199668 kb
Host smart-574af95b-140b-4b16-8571-006b25ce1f4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458116669 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.2458116669
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.1727454297
Short name T734
Test name
Test status
Simulation time 496110439 ps
CPU time 3.97 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 199756 kb
Host smart-5ce70257-8dde-45d1-b244-1d563e13989a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727454297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.1727454297
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.882357751
Short name T59
Test name
Test status
Simulation time 55534675372 ps
CPU time 587.46 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:39:23 PM PDT 24
Peak memory 216336 kb
Host smart-5b263381-7dc1-496b-a14f-88d0c04df446
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882357751 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.882357751
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2261980333
Short name T102
Test name
Test status
Simulation time 41405417 ps
CPU time 0.72 seconds
Started Jun 26 06:29:41 PM PDT 24
Finished Jun 26 06:29:51 PM PDT 24
Peak memory 197700 kb
Host smart-37fe6737-ec62-4392-aba0-ff3134ef57d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261980333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2261980333
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.3002731933
Short name T72
Test name
Test status
Simulation time 18714252 ps
CPU time 0.61 seconds
Started Jun 26 06:29:44 PM PDT 24
Finished Jun 26 06:29:49 PM PDT 24
Peak memory 194472 kb
Host smart-e80fa966-6f10-4179-8925-9d6d910fcf8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002731933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.3002731933
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.2881733368
Short name T694
Test name
Test status
Simulation time 59580593 ps
CPU time 1.26 seconds
Started Jun 26 06:29:49 PM PDT 24
Finished Jun 26 06:29:52 PM PDT 24
Peak memory 198112 kb
Host smart-2c63b428-fd85-471c-88da-69c9bac2e53d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881733368 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.2881733368
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1027178797
Short name T709
Test name
Test status
Simulation time 420990954 ps
CPU time 2.15 seconds
Started Jun 26 06:29:39 PM PDT 24
Finished Jun 26 06:29:47 PM PDT 24
Peak memory 199676 kb
Host smart-a343ee71-b2c4-442d-b128-3c392d520bd3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027178797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1027178797
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.2057929179
Short name T740
Test name
Test status
Simulation time 117914542263 ps
CPU time 354.94 seconds
Started Jun 26 06:29:43 PM PDT 24
Finished Jun 26 06:35:42 PM PDT 24
Peak memory 215936 kb
Host smart-dd551dc3-1fdf-411f-92dc-e04967f8dbd4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057929179 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.2057929179
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.896213280
Short name T687
Test name
Test status
Simulation time 29344035 ps
CPU time 0.97 seconds
Started Jun 26 06:29:34 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 199260 kb
Host smart-48aa4497-e019-47a4-b74a-ad51d8b174ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896213280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.896213280
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.105233374
Short name T683
Test name
Test status
Simulation time 145959246 ps
CPU time 0.58 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:36 PM PDT 24
Peak memory 194524 kb
Host smart-b9d98086-af6c-4b0a-a044-1f6b425748a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105233374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.105233374
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.181630318
Short name T752
Test name
Test status
Simulation time 36530732 ps
CPU time 1.66 seconds
Started Jun 26 06:29:42 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 199408 kb
Host smart-c6587075-2e85-4a7e-91d2-9aa3b9d23c8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181630318 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_csr
_outstanding.181630318
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.3466923200
Short name T698
Test name
Test status
Simulation time 618112753 ps
CPU time 3.27 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:38 PM PDT 24
Peak memory 199672 kb
Host smart-015c4ab6-92ab-4760-a105-126ce7aa810a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466923200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.3466923200
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3745847298
Short name T69
Test name
Test status
Simulation time 619406095998 ps
CPU time 1566.31 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:55:45 PM PDT 24
Peak memory 223072 kb
Host smart-2d1b6188-a4f6-4215-92cc-cd737213fb5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745847298 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3745847298
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3854732043
Short name T88
Test name
Test status
Simulation time 18125947 ps
CPU time 0.79 seconds
Started Jun 26 06:29:49 PM PDT 24
Finished Jun 26 06:29:52 PM PDT 24
Peak memory 198860 kb
Host smart-572860e5-0eb0-47af-99f5-894391989777
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854732043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3854732043
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3642412690
Short name T671
Test name
Test status
Simulation time 10928690 ps
CPU time 0.57 seconds
Started Jun 26 06:29:43 PM PDT 24
Finished Jun 26 06:29:47 PM PDT 24
Peak memory 194412 kb
Host smart-2350ddf0-668c-4f94-a7c9-33c942f8f58b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642412690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3642412690
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2960204327
Short name T771
Test name
Test status
Simulation time 206554247 ps
CPU time 1.14 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 198112 kb
Host smart-c5fa9bd7-bee2-4e06-b369-9ebd6b92da9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960204327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2960204327
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.1326065934
Short name T150
Test name
Test status
Simulation time 151054031 ps
CPU time 3.13 seconds
Started Jun 26 06:29:49 PM PDT 24
Finished Jun 26 06:29:54 PM PDT 24
Peak memory 199712 kb
Host smart-6c6416bc-d9c0-4bd7-a6f3-6fec7000dd4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326065934 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.1326065934
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.1953880055
Short name T720
Test name
Test status
Simulation time 47418458 ps
CPU time 2.3 seconds
Started Jun 26 06:29:33 PM PDT 24
Finished Jun 26 06:29:43 PM PDT 24
Peak memory 199748 kb
Host smart-cf3d8366-91c4-4b42-8260-c09c60abb066
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953880055 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.1953880055
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.1628036408
Short name T718
Test name
Test status
Simulation time 205811063 ps
CPU time 0.87 seconds
Started Jun 26 06:29:36 PM PDT 24
Finished Jun 26 06:29:45 PM PDT 24
Peak memory 198976 kb
Host smart-0a4fa838-cf46-4194-b426-a6e6a58ce2df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628036408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.1628036408
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.1131676627
Short name T750
Test name
Test status
Simulation time 92221475 ps
CPU time 0.58 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 194476 kb
Host smart-2944438a-30c0-46dc-a601-03fc7accfed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131676627 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.1131676627
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.886581507
Short name T685
Test name
Test status
Simulation time 432835092 ps
CPU time 1.84 seconds
Started Jun 26 06:29:32 PM PDT 24
Finished Jun 26 06:29:43 PM PDT 24
Peak memory 199752 kb
Host smart-950e1e7c-7b20-4a0f-a48c-b25b24355a67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886581507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_csr
_outstanding.886581507
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.2492146034
Short name T751
Test name
Test status
Simulation time 52671169 ps
CPU time 2.15 seconds
Started Jun 26 06:29:34 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 199728 kb
Host smart-ef742672-deec-460e-b8b5-c6a6715caf8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492146034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.2492146034
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.697163706
Short name T151
Test name
Test status
Simulation time 80956691 ps
CPU time 1.88 seconds
Started Jun 26 06:29:34 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 199704 kb
Host smart-3b2d0168-ff06-4f03-a18b-2e6d12a28b21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697163706 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.697163706
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.2395227612
Short name T41
Test name
Test status
Simulation time 36741256 ps
CPU time 2.21 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 199808 kb
Host smart-c29e506d-6f9d-462d-9e71-664a3c674de8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395227612 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.2395227612
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.2504202059
Short name T86
Test name
Test status
Simulation time 30674477 ps
CPU time 0.91 seconds
Started Jun 26 06:29:41 PM PDT 24
Finished Jun 26 06:29:47 PM PDT 24
Peak memory 198732 kb
Host smart-972f68e5-adfe-442a-b4f4-5ad31bf21066
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504202059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.2504202059
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.1225360406
Short name T668
Test name
Test status
Simulation time 43849036 ps
CPU time 0.57 seconds
Started Jun 26 06:29:33 PM PDT 24
Finished Jun 26 06:29:42 PM PDT 24
Peak memory 194488 kb
Host smart-a11d9bfd-67df-4de1-a673-ed58f0ad11b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225360406 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.1225360406
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.712535753
Short name T708
Test name
Test status
Simulation time 59314221 ps
CPU time 1.6 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:29:39 PM PDT 24
Peak memory 199680 kb
Host smart-1fc48e9d-184c-4948-96b0-ec72d19c22da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712535753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_csr
_outstanding.712535753
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.1137908353
Short name T689
Test name
Test status
Simulation time 69594134 ps
CPU time 1.65 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:43 PM PDT 24
Peak memory 199656 kb
Host smart-3148214d-0a37-45d2-8fe9-432f8af3de37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137908353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.1137908353
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.1407756517
Short name T745
Test name
Test status
Simulation time 488687677 ps
CPU time 4.21 seconds
Started Jun 26 06:29:47 PM PDT 24
Finished Jun 26 06:29:54 PM PDT 24
Peak memory 199688 kb
Host smart-0906618d-0d2c-4b9e-8bf2-d762535ffe5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407756517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.1407756517
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.481235698
Short name T672
Test name
Test status
Simulation time 41678435 ps
CPU time 1.38 seconds
Started Jun 26 06:29:53 PM PDT 24
Finished Jun 26 06:29:56 PM PDT 24
Peak memory 199796 kb
Host smart-9905883b-d836-464d-ae01-050001a29741
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481235698 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.481235698
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.3593048476
Short name T96
Test name
Test status
Simulation time 27670984 ps
CPU time 0.86 seconds
Started Jun 26 06:29:36 PM PDT 24
Finished Jun 26 06:29:45 PM PDT 24
Peak memory 199236 kb
Host smart-5d58f5fb-2fe2-4e17-81a9-7777d1dd11e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593048476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.3593048476
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.3171475103
Short name T732
Test name
Test status
Simulation time 113797264 ps
CPU time 0.6 seconds
Started Jun 26 06:29:36 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 194540 kb
Host smart-4fe11a5a-6222-4d0b-a0ec-3b7f79c30248
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171475103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.3171475103
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.443802314
Short name T741
Test name
Test status
Simulation time 39892326 ps
CPU time 1.16 seconds
Started Jun 26 06:29:44 PM PDT 24
Finished Jun 26 06:29:49 PM PDT 24
Peak memory 199492 kb
Host smart-bfc2c35f-7a5a-45fc-9085-a24d098aa0e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443802314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_csr
_outstanding.443802314
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.2894995410
Short name T700
Test name
Test status
Simulation time 54885535 ps
CPU time 3.02 seconds
Started Jun 26 06:29:43 PM PDT 24
Finished Jun 26 06:29:50 PM PDT 24
Peak memory 199704 kb
Host smart-514908b7-a31d-4aff-8a43-85bfa9ee1114
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894995410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.2894995410
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.1947997690
Short name T147
Test name
Test status
Simulation time 557542859 ps
CPU time 4.36 seconds
Started Jun 26 06:29:33 PM PDT 24
Finished Jun 26 06:29:46 PM PDT 24
Peak memory 199684 kb
Host smart-b17d8fa5-1b2d-4f14-a15b-ae5aeba4de60
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947997690 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.1947997690
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.1758842817
Short name T744
Test name
Test status
Simulation time 690060287 ps
CPU time 2.99 seconds
Started Jun 26 06:29:32 PM PDT 24
Finished Jun 26 06:29:43 PM PDT 24
Peak memory 197576 kb
Host smart-d7bd90d4-e0f2-477d-a315-6fe224d3b42a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758842817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.1758842817
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.1421482322
Short name T71
Test name
Test status
Simulation time 2990258482 ps
CPU time 17.05 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:53 PM PDT 24
Peak memory 199752 kb
Host smart-2fc623cf-db77-480b-a72f-4b4290fcd414
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421482322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.1421482322
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.2780438291
Short name T94
Test name
Test status
Simulation time 43085387 ps
CPU time 1.01 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:31 PM PDT 24
Peak memory 199148 kb
Host smart-ea45a8ea-1d36-4285-9932-79b39555d04c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780438291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.2780438291
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.224922844
Short name T748
Test name
Test status
Simulation time 46629037 ps
CPU time 1.33 seconds
Started Jun 26 06:29:32 PM PDT 24
Finished Jun 26 06:29:42 PM PDT 24
Peak memory 198860 kb
Host smart-7a2d5dd7-4026-426d-9d1e-add82e59deb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224922844 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.224922844
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.2619931919
Short name T719
Test name
Test status
Simulation time 46898089 ps
CPU time 0.83 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:29:39 PM PDT 24
Peak memory 199160 kb
Host smart-ab30b19b-7aa7-48ba-b0fd-1ba593a749aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619931919 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.2619931919
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.1973523894
Short name T746
Test name
Test status
Simulation time 14822082 ps
CPU time 0.6 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 194524 kb
Host smart-389e7a1f-56af-46b5-a084-ccafb8937dff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973523894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.1973523894
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.1372572330
Short name T723
Test name
Test status
Simulation time 84853200 ps
CPU time 1.09 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:32 PM PDT 24
Peak memory 199724 kb
Host smart-a62ac4ad-2a13-4146-b362-648f0e9c2523
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372572330 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.1372572330
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.842972945
Short name T772
Test name
Test status
Simulation time 80890472 ps
CPU time 4.03 seconds
Started Jun 26 06:30:10 PM PDT 24
Finished Jun 26 06:30:15 PM PDT 24
Peak memory 199668 kb
Host smart-aca8dcb9-5f87-4714-b9cf-dae7fa470af5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842972945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.842972945
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.605872508
Short name T677
Test name
Test status
Simulation time 85861090 ps
CPU time 1.69 seconds
Started Jun 26 06:29:22 PM PDT 24
Finished Jun 26 06:29:28 PM PDT 24
Peak memory 199720 kb
Host smart-7196c4cd-6c22-446c-8d51-e9270bb0749e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605872508 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.605872508
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.1529184864
Short name T764
Test name
Test status
Simulation time 12523947 ps
CPU time 0.63 seconds
Started Jun 26 06:29:47 PM PDT 24
Finished Jun 26 06:29:51 PM PDT 24
Peak memory 194472 kb
Host smart-0173c187-4db5-4a63-afec-44a2ef3279c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529184864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.1529184864
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3260196776
Short name T742
Test name
Test status
Simulation time 33234638 ps
CPU time 0.72 seconds
Started Jun 26 06:29:45 PM PDT 24
Finished Jun 26 06:29:49 PM PDT 24
Peak memory 194580 kb
Host smart-e6a12405-e550-4387-9c1b-8dbad2b90024
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260196776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3260196776
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.2229181661
Short name T141
Test name
Test status
Simulation time 13347836 ps
CPU time 0.61 seconds
Started Jun 26 06:29:47 PM PDT 24
Finished Jun 26 06:29:51 PM PDT 24
Peak memory 194724 kb
Host smart-d5e2019b-1600-4e34-a5db-9f64f2c9a5a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229181661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.2229181661
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2325252587
Short name T757
Test name
Test status
Simulation time 16168001 ps
CPU time 0.59 seconds
Started Jun 26 06:29:54 PM PDT 24
Finished Jun 26 06:29:56 PM PDT 24
Peak memory 194468 kb
Host smart-6ee1061d-c7b5-4af2-bbf1-f2e040986ceb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325252587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2325252587
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.3576721140
Short name T737
Test name
Test status
Simulation time 14013994 ps
CPU time 0.57 seconds
Started Jun 26 06:30:13 PM PDT 24
Finished Jun 26 06:30:15 PM PDT 24
Peak memory 194468 kb
Host smart-404594ff-4238-4ad3-940d-2abbd2a1a710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576721140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.3576721140
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.1812626824
Short name T743
Test name
Test status
Simulation time 13435369 ps
CPU time 0.63 seconds
Started Jun 26 06:29:53 PM PDT 24
Finished Jun 26 06:29:55 PM PDT 24
Peak memory 194712 kb
Host smart-d11af95b-dc96-4baa-aa1d-9e1fdf3c34f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812626824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.1812626824
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.957030154
Short name T70
Test name
Test status
Simulation time 28345412 ps
CPU time 0.68 seconds
Started Jun 26 06:29:56 PM PDT 24
Finished Jun 26 06:29:57 PM PDT 24
Peak memory 194548 kb
Host smart-787a8361-86cc-4199-aa2e-1ade98694f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957030154 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.957030154
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.1613286829
Short name T710
Test name
Test status
Simulation time 13581581 ps
CPU time 0.6 seconds
Started Jun 26 06:29:41 PM PDT 24
Finished Jun 26 06:29:47 PM PDT 24
Peak memory 194500 kb
Host smart-060f13ed-ba9e-4959-adde-b69de49fd6da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613286829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.1613286829
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.1483410265
Short name T695
Test name
Test status
Simulation time 13275538 ps
CPU time 0.57 seconds
Started Jun 26 06:29:55 PM PDT 24
Finished Jun 26 06:29:57 PM PDT 24
Peak memory 194584 kb
Host smart-a527a95d-0b3c-437d-a85d-371ccba3100f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483410265 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.1483410265
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2901472659
Short name T702
Test name
Test status
Simulation time 17822477 ps
CPU time 0.58 seconds
Started Jun 26 06:29:43 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 194580 kb
Host smart-9f5ce614-1d64-4414-b996-39b351430013
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901472659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2901472659
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.1594703553
Short name T701
Test name
Test status
Simulation time 228078621 ps
CPU time 3.09 seconds
Started Jun 26 06:29:26 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 199524 kb
Host smart-f9956030-4af1-4c0f-8c80-4833a2e7106a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594703553 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.1594703553
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.4106973331
Short name T726
Test name
Test status
Simulation time 1642854926 ps
CPU time 17.07 seconds
Started Jun 26 06:29:32 PM PDT 24
Finished Jun 26 06:29:57 PM PDT 24
Peak memory 198664 kb
Host smart-54334eef-3d7b-4091-99e6-a78315118cce
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106973331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.4106973331
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.1708350940
Short name T85
Test name
Test status
Simulation time 34188189 ps
CPU time 0.89 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:31 PM PDT 24
Peak memory 199048 kb
Host smart-d6dba224-5207-46ad-9097-fc699ae345a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708350940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.1708350940
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.3104037599
Short name T773
Test name
Test status
Simulation time 18210745202 ps
CPU time 65.15 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:30:40 PM PDT 24
Peak memory 208148 kb
Host smart-88aa7633-7ead-4691-b4e3-7259755e6cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104037599 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.3104037599
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.788577829
Short name T739
Test name
Test status
Simulation time 59407698 ps
CPU time 0.68 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 197216 kb
Host smart-93453e02-c5a7-4fcd-8941-2d46d9a38b33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788577829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.788577829
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.2959397310
Short name T704
Test name
Test status
Simulation time 17148861 ps
CPU time 0.59 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 194520 kb
Host smart-d9fb3f1b-7bb4-4bfd-8a5c-da5bc5ac3a0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959397310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.2959397310
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.3604142435
Short name T753
Test name
Test status
Simulation time 415163989 ps
CPU time 1.72 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:36 PM PDT 24
Peak memory 199572 kb
Host smart-b30738a4-0390-4c00-ae45-a96ec9236ce5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604142435 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.3604142435
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.4229285299
Short name T57
Test name
Test status
Simulation time 26543412 ps
CPU time 1.26 seconds
Started Jun 26 06:29:21 PM PDT 24
Finished Jun 26 06:29:26 PM PDT 24
Peak memory 199640 kb
Host smart-64659447-591a-4e98-8245-53df68e13350
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229285299 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.4229285299
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.2728397337
Short name T675
Test name
Test status
Simulation time 51980485 ps
CPU time 0.61 seconds
Started Jun 26 06:29:36 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 194508 kb
Host smart-8eb139b7-5347-43c7-abb6-8ba7a7034246
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728397337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.2728397337
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.2904581501
Short name T736
Test name
Test status
Simulation time 96792106 ps
CPU time 0.61 seconds
Started Jun 26 06:29:46 PM PDT 24
Finished Jun 26 06:29:50 PM PDT 24
Peak memory 194496 kb
Host smart-b859f4bc-7acd-44de-85a2-87ebbac58b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904581501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.2904581501
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.127133397
Short name T728
Test name
Test status
Simulation time 48975621 ps
CPU time 0.6 seconds
Started Jun 26 06:29:43 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 194536 kb
Host smart-3ab5f66f-5778-45d8-9a5a-0a8135863039
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127133397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.127133397
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.412283327
Short name T727
Test name
Test status
Simulation time 25591008 ps
CPU time 0.61 seconds
Started Jun 26 06:30:02 PM PDT 24
Finished Jun 26 06:30:04 PM PDT 24
Peak memory 194532 kb
Host smart-92a42e89-771b-493a-98d6-b6bd2338d54f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412283327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.412283327
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.1109323985
Short name T673
Test name
Test status
Simulation time 36609521 ps
CPU time 0.58 seconds
Started Jun 26 06:29:41 PM PDT 24
Finished Jun 26 06:29:46 PM PDT 24
Peak memory 194476 kb
Host smart-fbe66f38-a4c3-4d82-9faa-fd630a28cfa9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109323985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.1109323985
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3548408184
Short name T765
Test name
Test status
Simulation time 16340698 ps
CPU time 0.63 seconds
Started Jun 26 06:30:11 PM PDT 24
Finished Jun 26 06:30:13 PM PDT 24
Peak memory 194488 kb
Host smart-e943e386-234e-4c52-993c-f4f0c54535e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548408184 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3548408184
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.871516507
Short name T688
Test name
Test status
Simulation time 16898242 ps
CPU time 0.66 seconds
Started Jun 26 06:29:36 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 194616 kb
Host smart-20bf079f-4a43-4dd4-9cab-2fb58a2b768f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871516507 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.871516507
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2938694559
Short name T763
Test name
Test status
Simulation time 38360155 ps
CPU time 0.6 seconds
Started Jun 26 06:29:52 PM PDT 24
Finished Jun 26 06:29:53 PM PDT 24
Peak memory 194520 kb
Host smart-b4e679a0-0a2d-4bee-88ed-1c829f96aa30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938694559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2938694559
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.485703512
Short name T690
Test name
Test status
Simulation time 16345271 ps
CPU time 0.6 seconds
Started Jun 26 06:29:55 PM PDT 24
Finished Jun 26 06:29:56 PM PDT 24
Peak memory 194612 kb
Host smart-40f2d8e4-2172-44fd-bd59-311cfe80bada
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485703512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.485703512
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.4184728054
Short name T768
Test name
Test status
Simulation time 45196144 ps
CPU time 0.61 seconds
Started Jun 26 06:29:53 PM PDT 24
Finished Jun 26 06:29:55 PM PDT 24
Peak memory 194564 kb
Host smart-a7225ec5-af61-447b-8b48-eafb6d091173
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184728054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.4184728054
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.1516937596
Short name T95
Test name
Test status
Simulation time 1761622732 ps
CPU time 8.34 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:45 PM PDT 24
Peak memory 198544 kb
Host smart-3c0c3c4f-2631-4ace-9e8e-ecc5df9352dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516937596 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.1516937596
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3223761552
Short name T667
Test name
Test status
Simulation time 1124572429 ps
CPU time 15.91 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:53 PM PDT 24
Peak memory 199536 kb
Host smart-6930f54c-f281-4471-b98f-eada523ef224
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223761552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3223761552
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.848087011
Short name T97
Test name
Test status
Simulation time 151615042 ps
CPU time 0.99 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 199184 kb
Host smart-ac8fa501-0a2c-4319-991e-7012cb2391ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848087011 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.848087011
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.2909519395
Short name T715
Test name
Test status
Simulation time 119363190 ps
CPU time 1.4 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 199760 kb
Host smart-289bc103-c16b-4938-8de4-349f86fb3e98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909519395 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.2909519395
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.2058271311
Short name T98
Test name
Test status
Simulation time 47627586 ps
CPU time 0.69 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 197884 kb
Host smart-28676d5a-c8a3-4f9b-8801-97c456684123
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058271311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.2058271311
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.4166743428
Short name T713
Test name
Test status
Simulation time 62188624 ps
CPU time 0.58 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 194520 kb
Host smart-e90f64c0-0dee-4898-bcc6-fdc75b67abae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166743428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.4166743428
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1820672453
Short name T99
Test name
Test status
Simulation time 45486472 ps
CPU time 2.16 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:39 PM PDT 24
Peak memory 199756 kb
Host smart-a1472d68-30f4-4ce3-8f28-3d4fa1467b70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820672453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1820672453
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.837505520
Short name T66
Test name
Test status
Simulation time 438754130 ps
CPU time 2.18 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 199740 kb
Host smart-b5d19f8d-a1fa-43ae-b280-ac516cb8b50c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837505520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.837505520
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.3883765948
Short name T148
Test name
Test status
Simulation time 98539927 ps
CPU time 2.84 seconds
Started Jun 26 06:29:28 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 199684 kb
Host smart-f134a4ae-6f36-4bfe-bfd1-21498cebe6bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883765948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.3883765948
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.1758168589
Short name T703
Test name
Test status
Simulation time 14056189 ps
CPU time 0.61 seconds
Started Jun 26 06:29:46 PM PDT 24
Finished Jun 26 06:29:50 PM PDT 24
Peak memory 194616 kb
Host smart-a9e9e34c-dee2-4314-9a02-eccc768ad64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758168589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.1758168589
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.2413833655
Short name T682
Test name
Test status
Simulation time 20780630 ps
CPU time 0.6 seconds
Started Jun 26 06:29:34 PM PDT 24
Finished Jun 26 06:29:43 PM PDT 24
Peak memory 194680 kb
Host smart-cf8abf44-21c8-49f8-b89b-bd087a8eeb02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413833655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.2413833655
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.1731029456
Short name T140
Test name
Test status
Simulation time 39852571 ps
CPU time 0.64 seconds
Started Jun 26 06:29:47 PM PDT 24
Finished Jun 26 06:29:51 PM PDT 24
Peak memory 194544 kb
Host smart-919a72f4-3eb9-4201-8051-f4cfab136d78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731029456 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.1731029456
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.691753946
Short name T75
Test name
Test status
Simulation time 12995129 ps
CPU time 0.58 seconds
Started Jun 26 06:29:34 PM PDT 24
Finished Jun 26 06:29:43 PM PDT 24
Peak memory 194496 kb
Host smart-2daf3af4-6bab-46e5-8745-9b130716b7fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691753946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.691753946
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.2850868844
Short name T680
Test name
Test status
Simulation time 62099055 ps
CPU time 0.63 seconds
Started Jun 26 06:29:45 PM PDT 24
Finished Jun 26 06:29:50 PM PDT 24
Peak memory 194660 kb
Host smart-60c96e2c-06d4-418d-b0f9-be0a2886b934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850868844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.2850868844
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.1349536062
Short name T670
Test name
Test status
Simulation time 39079310 ps
CPU time 0.66 seconds
Started Jun 26 06:29:34 PM PDT 24
Finished Jun 26 06:29:43 PM PDT 24
Peak memory 194532 kb
Host smart-946c4aa6-9fb5-44c6-9e92-d4fc96b6b3e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349536062 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.1349536062
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.2025044600
Short name T722
Test name
Test status
Simulation time 16723160 ps
CPU time 0.59 seconds
Started Jun 26 06:30:11 PM PDT 24
Finished Jun 26 06:30:13 PM PDT 24
Peak memory 194568 kb
Host smart-aca4f68c-d08a-42ae-9fa6-5f104cc3386b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025044600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.2025044600
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.3975514677
Short name T756
Test name
Test status
Simulation time 24864782 ps
CPU time 0.59 seconds
Started Jun 26 06:29:44 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 194620 kb
Host smart-e2775d98-6425-4368-be80-644cfc997f5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975514677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.3975514677
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.2811836650
Short name T679
Test name
Test status
Simulation time 25570770 ps
CPU time 0.63 seconds
Started Jun 26 06:29:36 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 194592 kb
Host smart-c24c2864-7c74-4a44-ac7c-a659b9a6d4b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811836650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.2811836650
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3813241285
Short name T692
Test name
Test status
Simulation time 26543649 ps
CPU time 0.64 seconds
Started Jun 26 06:29:46 PM PDT 24
Finished Jun 26 06:29:50 PM PDT 24
Peak memory 194504 kb
Host smart-4217c13a-90c0-450d-9b63-c60cbcb0ed73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813241285 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3813241285
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.4218091617
Short name T678
Test name
Test status
Simulation time 75111518 ps
CPU time 1.77 seconds
Started Jun 26 06:29:30 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 199724 kb
Host smart-3dddc537-6784-44e8-a864-36951b3b77f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218091617 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.4218091617
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.1868659337
Short name T103
Test name
Test status
Simulation time 61734108 ps
CPU time 1.03 seconds
Started Jun 26 06:29:32 PM PDT 24
Finished Jun 26 06:29:41 PM PDT 24
Peak memory 199380 kb
Host smart-1ab2a368-2019-4fc5-879c-1f3839890d06
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868659337 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.1868659337
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.1468292409
Short name T762
Test name
Test status
Simulation time 20982529 ps
CPU time 0.62 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 194460 kb
Host smart-9ecc3926-a278-4bf0-8cc7-b890af0f5d8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468292409 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.1468292409
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.4285978433
Short name T738
Test name
Test status
Simulation time 403194962 ps
CPU time 1.68 seconds
Started Jun 26 06:29:24 PM PDT 24
Finished Jun 26 06:29:31 PM PDT 24
Peak memory 199568 kb
Host smart-370543fb-d4c9-414e-95ad-f2c76ae9280e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285978433 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.4285978433
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.2034280141
Short name T729
Test name
Test status
Simulation time 426181654 ps
CPU time 2.58 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 199640 kb
Host smart-50ff41af-4563-4412-a224-ef931568eb80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034280141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.2034280141
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.1942956826
Short name T149
Test name
Test status
Simulation time 87992938 ps
CPU time 1.77 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 199700 kb
Host smart-ddfc29fc-0769-459d-ada1-e86a673348c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942956826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.1942956826
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1629483748
Short name T747
Test name
Test status
Simulation time 88703668 ps
CPU time 1.65 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:39 PM PDT 24
Peak memory 199804 kb
Host smart-b46fa324-0320-4fce-9130-bde0d5884f16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629483748 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1629483748
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.1088438241
Short name T669
Test name
Test status
Simulation time 86720809 ps
CPU time 0.7 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:41 PM PDT 24
Peak memory 197204 kb
Host smart-3d741581-4e4c-49b1-9f37-53580eef0e64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088438241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.1088438241
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.2496645045
Short name T699
Test name
Test status
Simulation time 15330093 ps
CPU time 0.61 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 194520 kb
Host smart-30d7672d-26bc-40a0-bf70-9c62fabbe815
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496645045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.2496645045
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.2595763992
Short name T696
Test name
Test status
Simulation time 24251151 ps
CPU time 1.05 seconds
Started Jun 26 06:29:33 PM PDT 24
Finished Jun 26 06:29:43 PM PDT 24
Peak memory 198368 kb
Host smart-ab3a1dd7-5c84-4582-99bd-67cae8c71548
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595763992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr
_outstanding.2595763992
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3162834054
Short name T63
Test name
Test status
Simulation time 209819009 ps
CPU time 2.94 seconds
Started Jun 26 06:29:23 PM PDT 24
Finished Jun 26 06:29:30 PM PDT 24
Peak memory 199704 kb
Host smart-9c3405be-8dcf-42b4-929d-8ba26c53cfea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162834054 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3162834054
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.4181980719
Short name T143
Test name
Test status
Simulation time 375862548 ps
CPU time 3.86 seconds
Started Jun 26 06:29:25 PM PDT 24
Finished Jun 26 06:29:33 PM PDT 24
Peak memory 199648 kb
Host smart-55992303-84e1-4a87-8466-aa19a95ba8ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181980719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.4181980719
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.572849989
Short name T676
Test name
Test status
Simulation time 32417474 ps
CPU time 1.68 seconds
Started Jun 26 06:29:32 PM PDT 24
Finished Jun 26 06:29:42 PM PDT 24
Peak memory 199840 kb
Host smart-22de238e-28c1-4f47-91ab-35b06ae58b52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572849989 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.572849989
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.3099005644
Short name T760
Test name
Test status
Simulation time 42648686 ps
CPU time 0.67 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 196952 kb
Host smart-43d8e01d-6efb-43d0-8db1-688b4171f7d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099005644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.3099005644
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1726845979
Short name T730
Test name
Test status
Simulation time 36700521 ps
CPU time 0.62 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 194548 kb
Host smart-dad9219b-fc8c-4049-9290-158e51c9da8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726845979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1726845979
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.1651053580
Short name T100
Test name
Test status
Simulation time 119098417 ps
CPU time 2.19 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:42 PM PDT 24
Peak memory 199776 kb
Host smart-7125eef7-abe7-40a8-aee6-e5834bf98fbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651053580 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr
_outstanding.1651053580
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.974061071
Short name T684
Test name
Test status
Simulation time 242422143 ps
CPU time 2.93 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:36 PM PDT 24
Peak memory 199620 kb
Host smart-487fc7b2-4602-4b84-a9ba-66d446615fe7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974061071 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.974061071
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.2557026361
Short name T754
Test name
Test status
Simulation time 188928583 ps
CPU time 3.21 seconds
Started Jun 26 06:29:27 PM PDT 24
Finished Jun 26 06:29:35 PM PDT 24
Peak memory 199648 kb
Host smart-6af3dce5-04e7-454f-85ea-1074612eb7d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557026361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.2557026361
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.3881569062
Short name T64
Test name
Test status
Simulation time 52790536 ps
CPU time 3.45 seconds
Started Jun 26 06:29:39 PM PDT 24
Finished Jun 26 06:29:48 PM PDT 24
Peak memory 199772 kb
Host smart-98282e1a-90d7-40e4-8df2-5dbfe223b9a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881569062 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.3881569062
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.2511826578
Short name T73
Test name
Test status
Simulation time 22202194 ps
CPU time 0.7 seconds
Started Jun 26 06:29:40 PM PDT 24
Finished Jun 26 06:29:46 PM PDT 24
Peak memory 197044 kb
Host smart-67a0778f-b147-4213-a01b-23ecf0d1652e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511826578 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.2511826578
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.473158301
Short name T733
Test name
Test status
Simulation time 66612724 ps
CPU time 0.61 seconds
Started Jun 26 06:29:39 PM PDT 24
Finished Jun 26 06:29:45 PM PDT 24
Peak memory 194500 kb
Host smart-795d15ad-ba13-4cc4-ba20-58065149c045
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473158301 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.473158301
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.1473335164
Short name T697
Test name
Test status
Simulation time 83052074 ps
CPU time 1.77 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:38 PM PDT 24
Peak memory 199772 kb
Host smart-11bbc38b-8f85-45e8-b776-ccae40dcd8f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473335164 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.1473335164
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2200852517
Short name T767
Test name
Test status
Simulation time 764485368 ps
CPU time 2.3 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:41 PM PDT 24
Peak memory 199692 kb
Host smart-e021b291-d34b-49f3-8778-833b5a91c722
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200852517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2200852517
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.3041142891
Short name T39
Test name
Test status
Simulation time 196391023 ps
CPU time 1.89 seconds
Started Jun 26 06:29:44 PM PDT 24
Finished Jun 26 06:29:49 PM PDT 24
Peak memory 199764 kb
Host smart-92162071-0058-4027-b212-a79db041fa33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041142891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.3041142891
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.3353086232
Short name T65
Test name
Test status
Simulation time 32960592 ps
CPU time 2.08 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:38 PM PDT 24
Peak memory 199824 kb
Host smart-bca45dec-d673-496e-9c2a-a8e3c7bdf580
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353086232 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.3353086232
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.4211312924
Short name T761
Test name
Test status
Simulation time 19463503 ps
CPU time 0.75 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:40 PM PDT 24
Peak memory 197928 kb
Host smart-3a215da6-8a98-440b-9bc4-79bd4315ea63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211312924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.4211312924
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.3832784080
Short name T721
Test name
Test status
Simulation time 143591473 ps
CPU time 0.56 seconds
Started Jun 26 06:29:29 PM PDT 24
Finished Jun 26 06:29:37 PM PDT 24
Peak memory 194436 kb
Host smart-bb251b44-63b6-4bd8-a7a3-fa8b0845d159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832784080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.3832784080
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.2806919836
Short name T717
Test name
Test status
Simulation time 325378861 ps
CPU time 1.62 seconds
Started Jun 26 06:29:38 PM PDT 24
Finished Jun 26 06:29:46 PM PDT 24
Peak memory 199652 kb
Host smart-e0bce726-df7a-4506-b262-f995c568fab2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806919836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.2806919836
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.107619158
Short name T714
Test name
Test status
Simulation time 132743145 ps
CPU time 1.78 seconds
Started Jun 26 06:29:52 PM PDT 24
Finished Jun 26 06:29:55 PM PDT 24
Peak memory 199696 kb
Host smart-3f58a43f-60aa-4ce6-8b81-98c18dd7c6c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107619158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.107619158
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.2063997077
Short name T142
Test name
Test status
Simulation time 228798274 ps
CPU time 4.37 seconds
Started Jun 26 06:29:31 PM PDT 24
Finished Jun 26 06:29:44 PM PDT 24
Peak memory 199696 kb
Host smart-a20ae276-af18-4370-b205-07b7b93a69c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063997077 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.2063997077
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.2056195642
Short name T602
Test name
Test status
Simulation time 9291710335 ps
CPU time 1121.63 seconds
Started Jun 26 06:18:07 PM PDT 24
Finished Jun 26 06:36:50 PM PDT 24
Peak memory 769196 kb
Host smart-907d34ad-453f-4a8c-a0b8-37452ee7237b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2056195642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.2056195642
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/0.hmac_error.767732391
Short name T121
Test name
Test status
Simulation time 37696379826 ps
CPU time 125.01 seconds
Started Jun 26 06:18:07 PM PDT 24
Finished Jun 26 06:20:14 PM PDT 24
Peak memory 200108 kb
Host smart-8a81acb0-7748-4a3d-a21e-aef885c799d1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767732391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.767732391
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.78326102
Short name T213
Test name
Test status
Simulation time 1519430794 ps
CPU time 94.63 seconds
Started Jun 26 06:18:04 PM PDT 24
Finished Jun 26 06:19:40 PM PDT 24
Peak memory 200016 kb
Host smart-856e6f5e-cad9-4fcf-9bdd-790a18f6026a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78326102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.78326102
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.4131576009
Short name T37
Test name
Test status
Simulation time 144637320 ps
CPU time 0.82 seconds
Started Jun 26 06:18:10 PM PDT 24
Finished Jun 26 06:18:12 PM PDT 24
Peak memory 218288 kb
Host smart-c5e90c54-dcea-471f-a6aa-151636f69cc6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131576009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.4131576009
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.597305331
Short name T364
Test name
Test status
Simulation time 517589629 ps
CPU time 13.21 seconds
Started Jun 26 06:18:11 PM PDT 24
Finished Jun 26 06:18:26 PM PDT 24
Peak memory 200084 kb
Host smart-5f627e4a-0565-4ec6-a630-b39e34222096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597305331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.597305331
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_test_hmac_vectors.1158010129
Short name T355
Test name
Test status
Simulation time 83668190 ps
CPU time 1.14 seconds
Started Jun 26 06:18:06 PM PDT 24
Finished Jun 26 06:18:08 PM PDT 24
Peak memory 199988 kb
Host smart-62579046-f8bd-479d-82f6-af68c0815207
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158010129 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac_vectors.1158010129
Directory /workspace/0.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.4278033504
Short name T387
Test name
Test status
Simulation time 8768586188 ps
CPU time 515.95 seconds
Started Jun 26 06:18:06 PM PDT 24
Finished Jun 26 06:26:43 PM PDT 24
Peak memory 200004 kb
Host smart-2484b0d0-89c6-4915-94e2-386ab8654f0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4278033504 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.4278033504
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.188773212
Short name T603
Test name
Test status
Simulation time 192866431494 ps
CPU time 1652.44 seconds
Started Jun 26 06:18:07 PM PDT 24
Finished Jun 26 06:45:41 PM PDT 24
Peak memory 216112 kb
Host smart-61f085a3-62c0-4fcd-9d28-9ce5a283a74b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=188773212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.188773212
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.3329461786
Short name T222
Test name
Test status
Simulation time 140752705616 ps
CPU time 1781.31 seconds
Started Jun 26 06:18:07 PM PDT 24
Finished Jun 26 06:47:51 PM PDT 24
Peak memory 214960 kb
Host smart-91d4522b-cd67-40cd-9271-217d619e457c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3329461786 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.3329461786
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.1950615825
Short name T438
Test name
Test status
Simulation time 191204543 ps
CPU time 3.33 seconds
Started Jun 26 06:18:07 PM PDT 24
Finished Jun 26 06:18:12 PM PDT 24
Peak memory 199880 kb
Host smart-a4698979-0c9a-45f0-a7d7-c2abe1bd73a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950615825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.1950615825
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.4038118671
Short name T170
Test name
Test status
Simulation time 37795701 ps
CPU time 0.58 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:18:27 PM PDT 24
Peak memory 196096 kb
Host smart-4a60c63f-2582-4d2a-86a6-a2b6058e833d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038118671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.4038118671
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.3918028715
Short name T347
Test name
Test status
Simulation time 2353607897 ps
CPU time 50.59 seconds
Started Jun 26 06:18:04 PM PDT 24
Finished Jun 26 06:18:56 PM PDT 24
Peak memory 200136 kb
Host smart-7b4e6b39-e397-49de-a68c-8e90811e3624
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3918028715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.3918028715
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.956170488
Short name T201
Test name
Test status
Simulation time 202011850 ps
CPU time 4.17 seconds
Started Jun 26 06:18:07 PM PDT 24
Finished Jun 26 06:18:13 PM PDT 24
Peak memory 200040 kb
Host smart-e5d3ce63-f2b0-4781-a92c-8e7f17120a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956170488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.956170488
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.1591828137
Short name T238
Test name
Test status
Simulation time 3726973739 ps
CPU time 282.83 seconds
Started Jun 26 06:18:05 PM PDT 24
Finished Jun 26 06:22:49 PM PDT 24
Peak memory 640220 kb
Host smart-e5b7b2e5-5dc8-48d1-8967-7283cefe43a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1591828137 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.1591828137
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3129865791
Short name T241
Test name
Test status
Simulation time 8045625077 ps
CPU time 69.4 seconds
Started Jun 26 06:18:06 PM PDT 24
Finished Jun 26 06:19:16 PM PDT 24
Peak memory 200164 kb
Host smart-9e39146c-3f91-4f63-bb6e-c5186e4af744
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129865791 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3129865791
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.2342583238
Short name T587
Test name
Test status
Simulation time 4780887877 ps
CPU time 90.74 seconds
Started Jun 26 06:18:08 PM PDT 24
Finished Jun 26 06:19:40 PM PDT 24
Peak memory 208568 kb
Host smart-fe6a67fa-3dda-4ee6-8849-5615a7cb2176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342583238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.2342583238
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.1654317271
Short name T42
Test name
Test status
Simulation time 424707994 ps
CPU time 1.01 seconds
Started Jun 26 06:18:13 PM PDT 24
Finished Jun 26 06:18:15 PM PDT 24
Peak memory 219388 kb
Host smart-af0caa85-e9b1-4926-b884-d20562206f67
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654317271 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.1654317271
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.2714063924
Short name T263
Test name
Test status
Simulation time 5817490788 ps
CPU time 14.69 seconds
Started Jun 26 06:18:07 PM PDT 24
Finished Jun 26 06:18:23 PM PDT 24
Peak memory 200028 kb
Host smart-474550d3-16ae-492e-81a1-856eb2726816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714063924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.2714063924
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac_vectors.1523855236
Short name T546
Test name
Test status
Simulation time 79776453 ps
CPU time 1.33 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:18:28 PM PDT 24
Peak memory 200012 kb
Host smart-6c4dc25d-6c89-404a-b2fb-670337e57c42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523855236 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac_vectors.1523855236
Directory /workspace/1.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1965069672
Short name T517
Test name
Test status
Simulation time 7831638748 ps
CPU time 441.72 seconds
Started Jun 26 06:18:07 PM PDT 24
Finished Jun 26 06:25:31 PM PDT 24
Peak memory 199960 kb
Host smart-190cf156-1f16-471c-b097-d7b7b089e7cb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1965069672 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1965069672
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.3783931511
Short name T376
Test name
Test status
Simulation time 126835980609 ps
CPU time 1743.63 seconds
Started Jun 26 06:18:11 PM PDT 24
Finished Jun 26 06:47:16 PM PDT 24
Peak memory 215764 kb
Host smart-84ea10ca-05bc-437f-a09a-885ad2fbf280
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3783931511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.3783931511
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.436072855
Short name T157
Test name
Test status
Simulation time 168193927550 ps
CPU time 2158.7 seconds
Started Jun 26 06:18:10 PM PDT 24
Finished Jun 26 06:54:10 PM PDT 24
Peak memory 216388 kb
Host smart-e1530fed-9192-4742-9b0f-bde7ee021600
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=436072855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.436072855
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.1756789577
Short name T250
Test name
Test status
Simulation time 5008719381 ps
CPU time 86.96 seconds
Started Jun 26 06:18:08 PM PDT 24
Finished Jun 26 06:19:37 PM PDT 24
Peak memory 200108 kb
Host smart-3b3c8322-93c5-4c0c-b4c8-b597fd153183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756789577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.1756789577
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.2506546828
Short name T259
Test name
Test status
Simulation time 43560288 ps
CPU time 0.65 seconds
Started Jun 26 06:18:39 PM PDT 24
Finished Jun 26 06:18:42 PM PDT 24
Peak memory 196140 kb
Host smart-dee4f852-cef7-4531-94f1-b34b4c33ba5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506546828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.2506546828
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.2126604644
Short name T80
Test name
Test status
Simulation time 287134143 ps
CPU time 15.25 seconds
Started Jun 26 06:18:39 PM PDT 24
Finished Jun 26 06:18:56 PM PDT 24
Peak memory 200020 kb
Host smart-41f442d6-5182-4705-a54c-a9aec98b7a9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2126604644 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.2126604644
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2460918789
Short name T137
Test name
Test status
Simulation time 968687961 ps
CPU time 52.42 seconds
Started Jun 26 06:18:39 PM PDT 24
Finished Jun 26 06:19:33 PM PDT 24
Peak memory 200140 kb
Host smart-baa47cbf-c2a6-458f-b52c-9c452425f599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460918789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2460918789
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.103353772
Short name T487
Test name
Test status
Simulation time 11570663097 ps
CPU time 738.86 seconds
Started Jun 26 06:18:38 PM PDT 24
Finished Jun 26 06:30:59 PM PDT 24
Peak memory 731992 kb
Host smart-248b7f18-bcd3-4d28-965c-c8e419594cde
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103353772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.103353772
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.4116671493
Short name T251
Test name
Test status
Simulation time 274916344 ps
CPU time 3.25 seconds
Started Jun 26 06:18:38 PM PDT 24
Finished Jun 26 06:18:43 PM PDT 24
Peak memory 199864 kb
Host smart-c247b080-cc42-4b36-a1d8-880e85ac4520
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116671493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.4116671493
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.200402045
Short name T166
Test name
Test status
Simulation time 1923254509 ps
CPU time 17.4 seconds
Started Jun 26 06:18:38 PM PDT 24
Finished Jun 26 06:18:57 PM PDT 24
Peak memory 200116 kb
Host smart-aefcebb5-fea3-467e-bb01-8432d40a0c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200402045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.200402045
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3888098331
Short name T451
Test name
Test status
Simulation time 45537394 ps
CPU time 2.33 seconds
Started Jun 26 06:18:38 PM PDT 24
Finished Jun 26 06:18:42 PM PDT 24
Peak memory 200108 kb
Host smart-188f59d5-b87b-4cb9-bd23-1964a8d27311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888098331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3888098331
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_test_hmac_vectors.1969640027
Short name T557
Test name
Test status
Simulation time 298511280 ps
CPU time 1.23 seconds
Started Jun 26 06:18:38 PM PDT 24
Finished Jun 26 06:18:41 PM PDT 24
Peak memory 200000 kb
Host smart-94f184f9-deb9-4e7e-91c8-b088bf8b0fb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969640027 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac_vectors.1969640027
Directory /workspace/10.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha256_vectors.3992203219
Short name T665
Test name
Test status
Simulation time 50408564585 ps
CPU time 508.98 seconds
Started Jun 26 06:18:36 PM PDT 24
Finished Jun 26 06:27:06 PM PDT 24
Peak memory 200092 kb
Host smart-f49afc91-fb1a-4d46-87ee-4bd5d0819ee1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3992203219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha256_vectors.3992203219
Directory /workspace/10.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha384_vectors.4213235683
Short name T247
Test name
Test status
Simulation time 60787805870 ps
CPU time 1684.65 seconds
Started Jun 26 06:18:39 PM PDT 24
Finished Jun 26 06:46:45 PM PDT 24
Peak memory 208328 kb
Host smart-05a65b61-0968-4a4d-9398-01279017047a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4213235683 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha384_vectors.4213235683
Directory /workspace/10.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha512_vectors.1425943515
Short name T504
Test name
Test status
Simulation time 63015003057 ps
CPU time 1735.2 seconds
Started Jun 26 06:18:37 PM PDT 24
Finished Jun 26 06:47:34 PM PDT 24
Peak memory 215696 kb
Host smart-861cce89-9ba0-4571-8a6d-aa040fa9966c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1425943515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha512_vectors.1425943515
Directory /workspace/10.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.81611794
Short name T578
Test name
Test status
Simulation time 95791382 ps
CPU time 0.95 seconds
Started Jun 26 06:18:37 PM PDT 24
Finished Jun 26 06:18:40 PM PDT 24
Peak memory 198880 kb
Host smart-5e4888f4-9ccc-48c5-a407-18147f3ae56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81611794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.81611794
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_alert_test.2207965767
Short name T459
Test name
Test status
Simulation time 26565336 ps
CPU time 0.64 seconds
Started Jun 26 06:18:42 PM PDT 24
Finished Jun 26 06:18:44 PM PDT 24
Peak memory 196088 kb
Host smart-d660709a-5c3f-4a11-a852-3473d850f255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207965767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.2207965767
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.1171709833
Short name T441
Test name
Test status
Simulation time 2829015858 ps
CPU time 39.02 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:19:26 PM PDT 24
Peak memory 200144 kb
Host smart-9381ae70-688a-4c76-a2af-c3282ae3f009
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1171709833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.1171709833
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3964073956
Short name T530
Test name
Test status
Simulation time 1165538491 ps
CPU time 17.8 seconds
Started Jun 26 06:18:41 PM PDT 24
Finished Jun 26 06:19:00 PM PDT 24
Peak memory 200112 kb
Host smart-c86914d6-f8d1-4c8a-afc0-beb9ef624079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964073956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3964073956
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2030692751
Short name T390
Test name
Test status
Simulation time 2799398367 ps
CPU time 824.05 seconds
Started Jun 26 06:18:45 PM PDT 24
Finished Jun 26 06:32:30 PM PDT 24
Peak memory 703572 kb
Host smart-69494787-ad6d-4d2a-8eb0-23ddbf9a5267
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030692751 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2030692751
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_long_msg.1261283170
Short name T532
Test name
Test status
Simulation time 1321412953 ps
CPU time 40.1 seconds
Started Jun 26 06:18:42 PM PDT 24
Finished Jun 26 06:19:23 PM PDT 24
Peak memory 200092 kb
Host smart-41ef711d-ae6e-4efa-9776-4942016fe66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261283170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.1261283170
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.1904669542
Short name T373
Test name
Test status
Simulation time 224277393 ps
CPU time 11.23 seconds
Started Jun 26 06:18:43 PM PDT 24
Finished Jun 26 06:18:56 PM PDT 24
Peak memory 200116 kb
Host smart-37d80b30-ce33-442e-9bbb-a7ed04a7632d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904669542 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.1904669542
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_test_hmac_vectors.4043956636
Short name T311
Test name
Test status
Simulation time 49833146 ps
CPU time 1.21 seconds
Started Jun 26 06:18:43 PM PDT 24
Finished Jun 26 06:18:46 PM PDT 24
Peak memory 200252 kb
Host smart-2966b37c-b9ce-4c46-9ef7-ffd3633bb084
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043956636 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac_vectors.4043956636
Directory /workspace/11.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha256_vectors.3783258557
Short name T341
Test name
Test status
Simulation time 41777885139 ps
CPU time 447.6 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:26:15 PM PDT 24
Peak memory 200072 kb
Host smart-ba2138bd-4dcb-442e-abf4-1b4d08537733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3783258557 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha256_vectors.3783258557
Directory /workspace/11.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha512_vectors.4029669336
Short name T450
Test name
Test status
Simulation time 59110805985 ps
CPU time 1643.71 seconds
Started Jun 26 06:18:43 PM PDT 24
Finished Jun 26 06:46:09 PM PDT 24
Peak memory 215572 kb
Host smart-7759df93-48db-48fd-855e-b5a41128800d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4029669336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha512_vectors.4029669336
Directory /workspace/11.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.518301387
Short name T610
Test name
Test status
Simulation time 6278678774 ps
CPU time 69.56 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:19:57 PM PDT 24
Peak memory 200160 kb
Host smart-1c527ef5-d2d1-4cc3-9d7a-a7bb9af08fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518301387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.518301387
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.3593084602
Short name T654
Test name
Test status
Simulation time 45715099 ps
CPU time 0.66 seconds
Started Jun 26 06:18:44 PM PDT 24
Finished Jun 26 06:18:46 PM PDT 24
Peak memory 195956 kb
Host smart-6bd1e91a-52c7-42b8-aea5-a2316697f4a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593084602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.3593084602
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1998579817
Short name T111
Test name
Test status
Simulation time 730833620 ps
CPU time 38.34 seconds
Started Jun 26 06:18:45 PM PDT 24
Finished Jun 26 06:19:25 PM PDT 24
Peak memory 200052 kb
Host smart-3146e8f4-47db-4aa8-b2aa-72758ab2439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998579817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1998579817
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.251146333
Short name T412
Test name
Test status
Simulation time 5095781931 ps
CPU time 1461.54 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:43:10 PM PDT 24
Peak memory 760088 kb
Host smart-78eb5791-2469-4d76-a902-e6f727d81408
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251146333 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.251146333
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3459424269
Short name T503
Test name
Test status
Simulation time 64176459496 ps
CPU time 197.04 seconds
Started Jun 26 06:18:47 PM PDT 24
Finished Jun 26 06:22:06 PM PDT 24
Peak memory 200080 kb
Host smart-150d5433-d8f8-4df5-85cd-df702cbb6cd0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459424269 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3459424269
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3229431275
Short name T244
Test name
Test status
Simulation time 6155137022 ps
CPU time 91.42 seconds
Started Jun 26 06:18:47 PM PDT 24
Finished Jun 26 06:20:20 PM PDT 24
Peak memory 200144 kb
Host smart-70a99299-8ae1-4f97-b858-bfb94e417990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229431275 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3229431275
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.3339413732
Short name T613
Test name
Test status
Simulation time 421596408 ps
CPU time 6.49 seconds
Started Jun 26 06:18:44 PM PDT 24
Finished Jun 26 06:18:52 PM PDT 24
Peak memory 200032 kb
Host smart-5b1f98ae-649c-451b-a8b0-c271d6ca3b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339413732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.3339413732
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_test_hmac_vectors.2640983728
Short name T545
Test name
Test status
Simulation time 548534611 ps
CPU time 1.37 seconds
Started Jun 26 06:18:45 PM PDT 24
Finished Jun 26 06:18:47 PM PDT 24
Peak memory 200056 kb
Host smart-09f8e45f-4678-4668-a430-c226b729f961
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640983728 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac_vectors.2640983728
Directory /workspace/12.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha256_vectors.3561259676
Short name T480
Test name
Test status
Simulation time 553016442257 ps
CPU time 514.45 seconds
Started Jun 26 06:18:43 PM PDT 24
Finished Jun 26 06:27:19 PM PDT 24
Peak memory 200076 kb
Host smart-98fd7b79-14de-4cdb-bb19-853b42ab8ad7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3561259676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha256_vectors.3561259676
Directory /workspace/12.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha384_vectors.3647624650
Short name T159
Test name
Test status
Simulation time 66787618368 ps
CPU time 1854.47 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:49:43 PM PDT 24
Peak memory 215676 kb
Host smart-effc5313-295f-47f5-871a-711652ea310d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3647624650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha384_vectors.3647624650
Directory /workspace/12.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha512_vectors.2906561430
Short name T315
Test name
Test status
Simulation time 69565747637 ps
CPU time 1962.95 seconds
Started Jun 26 06:18:44 PM PDT 24
Finished Jun 26 06:51:29 PM PDT 24
Peak memory 216400 kb
Host smart-f59c1211-518e-4555-8171-9f8ab43c3424
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2906561430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha512_vectors.2906561430
Directory /workspace/12.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.2728612024
Short name T242
Test name
Test status
Simulation time 4741790478 ps
CPU time 22.63 seconds
Started Jun 26 06:18:43 PM PDT 24
Finished Jun 26 06:19:07 PM PDT 24
Peak memory 200116 kb
Host smart-51fc7ff8-f6c0-406d-97c9-4e5fc18532ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728612024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.2728612024
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.2669776105
Short name T601
Test name
Test status
Simulation time 47493733 ps
CPU time 0.61 seconds
Started Jun 26 06:18:50 PM PDT 24
Finished Jun 26 06:18:53 PM PDT 24
Peak memory 196136 kb
Host smart-f89bb730-3b08-4b68-92ab-7a63eff6f4a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669776105 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.2669776105
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.2429740726
Short name T20
Test name
Test status
Simulation time 1236876965 ps
CPU time 16.38 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:19:04 PM PDT 24
Peak memory 200100 kb
Host smart-43d0c52f-d7db-4903-ace0-37f33a3982a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429740726 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.2429740726
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.730687446
Short name T588
Test name
Test status
Simulation time 637827835 ps
CPU time 9.38 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:18:57 PM PDT 24
Peak memory 200040 kb
Host smart-42fe94e6-b600-45a5-9173-1775e9e728d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730687446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.730687446
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.19579732
Short name T452
Test name
Test status
Simulation time 2694724197 ps
CPU time 614.23 seconds
Started Jun 26 06:18:44 PM PDT 24
Finished Jun 26 06:29:00 PM PDT 24
Peak memory 680472 kb
Host smart-df7e0f31-ad66-4c70-bce9-5464d46b88fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19579732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.19579732
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.1394848024
Short name T115
Test name
Test status
Simulation time 6644340583 ps
CPU time 98.7 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:20:26 PM PDT 24
Peak memory 200088 kb
Host smart-b00f93d3-0bc8-40d2-b304-00ff3444f556
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394848024 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.1394848024
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.1997169927
Short name T463
Test name
Test status
Simulation time 1834635238 ps
CPU time 18.07 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:19:06 PM PDT 24
Peak memory 200012 kb
Host smart-79b287a9-6aa0-4bc9-a54c-e0f0e7a159d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997169927 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.1997169927
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.3715535049
Short name T219
Test name
Test status
Simulation time 231034847 ps
CPU time 4.61 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:18:52 PM PDT 24
Peak memory 200096 kb
Host smart-3e962b5f-f2ee-475d-9429-dbe93ec09056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715535049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.3715535049
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_test_hmac_vectors.1421563891
Short name T249
Test name
Test status
Simulation time 43495032 ps
CPU time 1.33 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:18:52 PM PDT 24
Peak memory 199924 kb
Host smart-fc30a7f3-f92f-4502-87a1-6cda53d4653d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421563891 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac_vectors.1421563891
Directory /workspace/13.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha256_vectors.1420650559
Short name T339
Test name
Test status
Simulation time 108313307765 ps
CPU time 467.74 seconds
Started Jun 26 06:18:51 PM PDT 24
Finished Jun 26 06:26:41 PM PDT 24
Peak memory 200076 kb
Host smart-56631cc1-81e0-4ab9-b682-7ebf77c6fd40
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1420650559 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha256_vectors.1420650559
Directory /workspace/13.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha384_vectors.2359822387
Short name T516
Test name
Test status
Simulation time 190039087185 ps
CPU time 1750.32 seconds
Started Jun 26 06:18:51 PM PDT 24
Finished Jun 26 06:48:03 PM PDT 24
Peak memory 215604 kb
Host smart-edcceaeb-6ab3-4d4f-a868-a78344e4f203
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2359822387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha384_vectors.2359822387
Directory /workspace/13.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha512_vectors.3987346640
Short name T370
Test name
Test status
Simulation time 111616657066 ps
CPU time 1710.35 seconds
Started Jun 26 06:18:50 PM PDT 24
Finished Jun 26 06:47:23 PM PDT 24
Peak memory 216428 kb
Host smart-52ffe8eb-0081-45ad-9dc1-1673f95eaf2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3987346640 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha512_vectors.3987346640
Directory /workspace/13.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.1918991817
Short name T661
Test name
Test status
Simulation time 545387881 ps
CPU time 24.65 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:19:15 PM PDT 24
Peak memory 200084 kb
Host smart-17d0a16b-5c0f-4e99-b3c9-2e2a1ad13a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918991817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.1918991817
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.509981788
Short name T218
Test name
Test status
Simulation time 14604183 ps
CPU time 0.59 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:18:51 PM PDT 24
Peak memory 195096 kb
Host smart-e249e777-e200-4334-92d8-067021259019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509981788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.509981788
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.4294561711
Short name T400
Test name
Test status
Simulation time 675160930 ps
CPU time 34.14 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:19:24 PM PDT 24
Peak memory 200048 kb
Host smart-6555237e-907d-4ba7-bb12-204f6df9da10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294561711 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.4294561711
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3414140396
Short name T608
Test name
Test status
Simulation time 953759260 ps
CPU time 52.91 seconds
Started Jun 26 06:18:47 PM PDT 24
Finished Jun 26 06:19:41 PM PDT 24
Peak memory 200072 kb
Host smart-fb12cf21-f287-4bf4-ac48-9dfa6d87fcb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414140396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3414140396
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.3686979853
Short name T417
Test name
Test status
Simulation time 7039983114 ps
CPU time 778.94 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:31:50 PM PDT 24
Peak memory 658492 kb
Host smart-a5eb4c48-5fc1-46d6-8da5-9b5a47900139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3686979853 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.3686979853
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.3077985185
Short name T371
Test name
Test status
Simulation time 9310758065 ps
CPU time 127.65 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:20:59 PM PDT 24
Peak memory 200092 kb
Host smart-4cd546c0-21b1-4be8-a44e-7954599bcdc4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077985185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.3077985185
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.1506053316
Short name T269
Test name
Test status
Simulation time 11617790108 ps
CPU time 117.3 seconds
Started Jun 26 06:18:50 PM PDT 24
Finished Jun 26 06:20:50 PM PDT 24
Peak memory 216260 kb
Host smart-2ca67c24-0f20-47c5-8cbc-70db829d62e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506053316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.1506053316
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.374626789
Short name T474
Test name
Test status
Simulation time 753230633 ps
CPU time 7.18 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:18:58 PM PDT 24
Peak memory 200008 kb
Host smart-073cb2ac-9d33-48fd-a196-de4ebd694d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374626789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.374626789
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac_vectors.37544408
Short name T348
Test name
Test status
Simulation time 64152440 ps
CPU time 1.39 seconds
Started Jun 26 06:18:53 PM PDT 24
Finished Jun 26 06:18:55 PM PDT 24
Peak memory 200044 kb
Host smart-08d12704-a620-400e-b677-87cee2bd7926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37544408 -assert nopostpro
c +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac_vectors.37544408
Directory /workspace/14.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha256_vectors.887646741
Short name T434
Test name
Test status
Simulation time 53451021991 ps
CPU time 470.6 seconds
Started Jun 26 06:18:53 PM PDT 24
Finished Jun 26 06:26:44 PM PDT 24
Peak memory 199932 kb
Host smart-61587b5f-765e-4ac1-8554-05c69c03b202
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=887646741 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha256_vectors.887646741
Directory /workspace/14.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha384_vectors.3826439756
Short name T491
Test name
Test status
Simulation time 58589672687 ps
CPU time 1680.14 seconds
Started Jun 26 06:18:51 PM PDT 24
Finished Jun 26 06:46:53 PM PDT 24
Peak memory 215560 kb
Host smart-49a4bd91-077a-484e-99f6-8b10e7ded7b3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3826439756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha384_vectors.3826439756
Directory /workspace/14.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1548110035
Short name T363
Test name
Test status
Simulation time 9739965741 ps
CPU time 42.54 seconds
Started Jun 26 06:19:52 PM PDT 24
Finished Jun 26 06:20:35 PM PDT 24
Peak memory 200136 kb
Host smart-3c1ed7ec-19d2-4f32-82d3-2714c00fdbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548110035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1548110035
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.2629844338
Short name T604
Test name
Test status
Simulation time 33739823 ps
CPU time 0.6 seconds
Started Jun 26 06:18:46 PM PDT 24
Finished Jun 26 06:18:48 PM PDT 24
Peak memory 195076 kb
Host smart-a739b30c-bb50-431e-84a5-2e2dbb540cfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629844338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.2629844338
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.3263020724
Short name T643
Test name
Test status
Simulation time 3896689329 ps
CPU time 19.22 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:19:10 PM PDT 24
Peak memory 200112 kb
Host smart-92d7bbb3-fece-433f-9d3b-34a09161ed00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3263020724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.3263020724
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.2324678835
Short name T410
Test name
Test status
Simulation time 274270980 ps
CPU time 1.88 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:18:52 PM PDT 24
Peak memory 199976 kb
Host smart-d450f356-d77d-45ca-819e-893ef0fcea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324678835 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.2324678835
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.3169396171
Short name T126
Test name
Test status
Simulation time 4362903798 ps
CPU time 1180.87 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:38:31 PM PDT 24
Peak memory 784996 kb
Host smart-af168838-003d-44c6-b6c6-8354b3d6033d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3169396171 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.3169396171
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.845326247
Short name T582
Test name
Test status
Simulation time 973876620 ps
CPU time 12.78 seconds
Started Jun 26 06:18:50 PM PDT 24
Finished Jun 26 06:19:05 PM PDT 24
Peak memory 199936 kb
Host smart-ab63a4bb-07e2-4a16-99a3-4f027595679b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845326247 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.845326247
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.2994388002
Short name T522
Test name
Test status
Simulation time 1745660594 ps
CPU time 31.29 seconds
Started Jun 26 06:18:47 PM PDT 24
Finished Jun 26 06:19:19 PM PDT 24
Peak memory 200068 kb
Host smart-a147b237-e787-4b38-88bd-c5274e1a7a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994388002 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.2994388002
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1465415016
Short name T16
Test name
Test status
Simulation time 983441000 ps
CPU time 14.9 seconds
Started Jun 26 06:18:52 PM PDT 24
Finished Jun 26 06:19:08 PM PDT 24
Peak memory 200032 kb
Host smart-db6bb338-0afc-4cff-821b-16215c9e706e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465415016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1465415016
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_test_hmac_vectors.2147671511
Short name T618
Test name
Test status
Simulation time 68367170 ps
CPU time 1.37 seconds
Started Jun 26 06:18:51 PM PDT 24
Finished Jun 26 06:18:54 PM PDT 24
Peak memory 200072 kb
Host smart-d70a2cc7-03a0-4a37-93e2-cadbef11c0aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147671511 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac_vectors.2147671511
Directory /workspace/15.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha256_vectors.697395974
Short name T554
Test name
Test status
Simulation time 40219530835 ps
CPU time 517.67 seconds
Started Jun 26 06:18:53 PM PDT 24
Finished Jun 26 06:27:32 PM PDT 24
Peak memory 200072 kb
Host smart-22ca13ae-e1d6-46d2-ae36-a0dc0240c36b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=697395974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha256_vectors.697395974
Directory /workspace/15.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha384_vectors.272080031
Short name T489
Test name
Test status
Simulation time 132189304309 ps
CPU time 1811.11 seconds
Started Jun 26 06:18:49 PM PDT 24
Finished Jun 26 06:49:02 PM PDT 24
Peak memory 215508 kb
Host smart-e768a660-38dd-4e59-bb54-7f32122acabf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=272080031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha384_vectors.272080031
Directory /workspace/15.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha512_vectors.644972527
Short name T327
Test name
Test status
Simulation time 54097851236 ps
CPU time 1468.55 seconds
Started Jun 26 06:18:50 PM PDT 24
Finished Jun 26 06:43:20 PM PDT 24
Peak memory 216456 kb
Host smart-e902d3b6-7287-41e4-bc6a-bc43c5c08299
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=644972527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha512_vectors.644972527
Directory /workspace/15.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.4052593376
Short name T272
Test name
Test status
Simulation time 1000094012 ps
CPU time 4.59 seconds
Started Jun 26 06:18:53 PM PDT 24
Finished Jun 26 06:18:58 PM PDT 24
Peak memory 199892 kb
Host smart-db81c8bb-0763-40fe-b41e-f365d0d100d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052593376 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.4052593376
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.1565325536
Short name T509
Test name
Test status
Simulation time 12801985 ps
CPU time 0.6 seconds
Started Jun 26 06:18:58 PM PDT 24
Finished Jun 26 06:18:59 PM PDT 24
Peak memory 196136 kb
Host smart-ee0c291c-e8c2-47ee-affa-ef7b4f83c6f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565325536 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.1565325536
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.2719803393
Short name T456
Test name
Test status
Simulation time 756674693 ps
CPU time 33.63 seconds
Started Jun 26 06:18:58 PM PDT 24
Finished Jun 26 06:19:32 PM PDT 24
Peak memory 199900 kb
Host smart-2683092e-ecf8-416c-90f3-74a796ddfb09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2719803393 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.2719803393
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.2418348412
Short name T535
Test name
Test status
Simulation time 442378102 ps
CPU time 24.61 seconds
Started Jun 26 06:18:58 PM PDT 24
Finished Jun 26 06:19:24 PM PDT 24
Peak memory 200016 kb
Host smart-7c9fb64b-b931-46a6-acee-ab20f8bdf51c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418348412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.2418348412
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.3542068885
Short name T337
Test name
Test status
Simulation time 6876057138 ps
CPU time 409.34 seconds
Started Jun 26 06:18:57 PM PDT 24
Finished Jun 26 06:25:47 PM PDT 24
Peak memory 646796 kb
Host smart-11913432-d54d-400d-bf42-c00b65c6b4b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3542068885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.3542068885
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.4140154064
Short name T248
Test name
Test status
Simulation time 30162552250 ps
CPU time 44.22 seconds
Started Jun 26 06:18:55 PM PDT 24
Finished Jun 26 06:19:40 PM PDT 24
Peak memory 200040 kb
Host smart-69fb8301-fa1f-42e6-b3d0-1817514654bc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140154064 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.4140154064
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.3058565326
Short name T333
Test name
Test status
Simulation time 15528578881 ps
CPU time 96.27 seconds
Started Jun 26 06:18:54 PM PDT 24
Finished Jun 26 06:20:31 PM PDT 24
Peak memory 200156 kb
Host smart-28df461e-bb3a-4d09-a541-97bf5705cf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058565326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.3058565326
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.132080118
Short name T515
Test name
Test status
Simulation time 160665614 ps
CPU time 6.7 seconds
Started Jun 26 06:18:51 PM PDT 24
Finished Jun 26 06:18:59 PM PDT 24
Peak memory 200060 kb
Host smart-b6c1f94c-6894-4f1b-880f-123ee4f301ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132080118 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.132080118
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.1739432990
Short name T622
Test name
Test status
Simulation time 10591420634 ps
CPU time 44.58 seconds
Started Jun 26 06:18:54 PM PDT 24
Finished Jun 26 06:19:40 PM PDT 24
Peak memory 216528 kb
Host smart-b4dca165-c9e1-4b3b-9d33-d45bcc5154f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739432990 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.1739432990
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac_vectors.2219921938
Short name T343
Test name
Test status
Simulation time 300357159 ps
CPU time 1.41 seconds
Started Jun 26 06:18:55 PM PDT 24
Finished Jun 26 06:18:57 PM PDT 24
Peak memory 200276 kb
Host smart-7a546dda-62cd-4e98-a39f-2d54fb71ffc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219921938 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac_vectors.2219921938
Directory /workspace/16.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha256_vectors.3095749545
Short name T204
Test name
Test status
Simulation time 137930674455 ps
CPU time 471.49 seconds
Started Jun 26 06:18:54 PM PDT 24
Finished Jun 26 06:26:47 PM PDT 24
Peak memory 200048 kb
Host smart-941a7b9f-a2ed-412e-92fc-4c50b0f6e1b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3095749545 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha256_vectors.3095749545
Directory /workspace/16.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha384_vectors.1045708525
Short name T271
Test name
Test status
Simulation time 161185646031 ps
CPU time 1980.42 seconds
Started Jun 26 06:18:55 PM PDT 24
Finished Jun 26 06:51:57 PM PDT 24
Peak memory 216004 kb
Host smart-087076a1-cf69-431b-930d-f2361578f5fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1045708525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha384_vectors.1045708525
Directory /workspace/16.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha512_vectors.1535220955
Short name T316
Test name
Test status
Simulation time 122977084952 ps
CPU time 1579.5 seconds
Started Jun 26 06:18:58 PM PDT 24
Finished Jun 26 06:45:18 PM PDT 24
Peak memory 216292 kb
Host smart-8d7fbabc-f3ea-45e7-a172-ea3a8cc38e62
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1535220955 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha512_vectors.1535220955
Directory /workspace/16.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.3944820491
Short name T382
Test name
Test status
Simulation time 1060343754 ps
CPU time 8.66 seconds
Started Jun 26 06:18:56 PM PDT 24
Finished Jun 26 06:19:05 PM PDT 24
Peak memory 200052 kb
Host smart-516f3ba2-6523-44b4-b96d-20d5138cb9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944820491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.3944820491
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.1605694246
Short name T33
Test name
Test status
Simulation time 12026343 ps
CPU time 0.59 seconds
Started Jun 26 06:19:07 PM PDT 24
Finished Jun 26 06:19:09 PM PDT 24
Peak memory 195816 kb
Host smart-db8f2ad9-c68d-4f75-b216-0246be11ce47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605694246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.1605694246
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.248777505
Short name T23
Test name
Test status
Simulation time 1050604667 ps
CPU time 13.62 seconds
Started Jun 26 06:18:54 PM PDT 24
Finished Jun 26 06:19:09 PM PDT 24
Peak memory 200108 kb
Host smart-cfd6cd75-a822-4f8a-9284-bc38ffd9d8a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=248777505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.248777505
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.3067840267
Short name T291
Test name
Test status
Simulation time 1870845875 ps
CPU time 27.07 seconds
Started Jun 26 06:18:56 PM PDT 24
Finished Jun 26 06:19:24 PM PDT 24
Peak memory 200100 kb
Host smart-8333f64f-632e-4f4f-8351-015b96ccd7d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067840267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.3067840267
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.2108319144
Short name T399
Test name
Test status
Simulation time 6710814634 ps
CPU time 946.94 seconds
Started Jun 26 06:18:55 PM PDT 24
Finished Jun 26 06:34:43 PM PDT 24
Peak memory 729568 kb
Host smart-92d26aa7-a51f-4327-92a2-fe254578bb49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2108319144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.2108319144
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.555111389
Short name T124
Test name
Test status
Simulation time 3321189854 ps
CPU time 174.87 seconds
Started Jun 26 06:18:58 PM PDT 24
Finished Jun 26 06:21:53 PM PDT 24
Peak memory 200124 kb
Host smart-780aea1d-a27f-459a-a69c-247f22ba133f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555111389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.555111389
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.3351166994
Short name T309
Test name
Test status
Simulation time 1008044818 ps
CPU time 15.44 seconds
Started Jun 26 06:18:56 PM PDT 24
Finished Jun 26 06:19:13 PM PDT 24
Peak memory 199992 kb
Host smart-1834c679-e6f4-4421-9989-deb2d9d04255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351166994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.3351166994
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2470692771
Short name T183
Test name
Test status
Simulation time 279345678 ps
CPU time 4.68 seconds
Started Jun 26 06:18:56 PM PDT 24
Finished Jun 26 06:19:01 PM PDT 24
Peak memory 200068 kb
Host smart-762e311d-6902-4f91-950e-c41031790361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470692771 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2470692771
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac_vectors.2426122329
Short name T629
Test name
Test status
Simulation time 33477164 ps
CPU time 1.25 seconds
Started Jun 26 06:19:07 PM PDT 24
Finished Jun 26 06:19:10 PM PDT 24
Peak memory 200004 kb
Host smart-52647596-1f44-479a-bde7-bb4b101b1bcb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426122329 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac_vectors.2426122329
Directory /workspace/17.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha256_vectors.1516678359
Short name T233
Test name
Test status
Simulation time 73629519819 ps
CPU time 428.31 seconds
Started Jun 26 06:18:56 PM PDT 24
Finished Jun 26 06:26:05 PM PDT 24
Peak memory 200084 kb
Host smart-3d6e7852-68ea-4120-af51-9c7cbf40239a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1516678359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha256_vectors.1516678359
Directory /workspace/17.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha384_vectors.467211056
Short name T652
Test name
Test status
Simulation time 461427917094 ps
CPU time 1869.99 seconds
Started Jun 26 06:19:02 PM PDT 24
Finished Jun 26 06:50:13 PM PDT 24
Peak memory 216500 kb
Host smart-add63dd0-d12f-41ac-b57b-1c2dce9bd689
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=467211056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha384_vectors.467211056
Directory /workspace/17.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha512_vectors.1172517613
Short name T611
Test name
Test status
Simulation time 88462048590 ps
CPU time 1824.56 seconds
Started Jun 26 06:19:02 PM PDT 24
Finished Jun 26 06:49:28 PM PDT 24
Peak memory 216192 kb
Host smart-71496421-1012-46d2-b737-4f579d2973a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1172517613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha512_vectors.1172517613
Directory /workspace/17.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.3074179764
Short name T464
Test name
Test status
Simulation time 1627292856 ps
CPU time 54.13 seconds
Started Jun 26 06:18:56 PM PDT 24
Finished Jun 26 06:19:51 PM PDT 24
Peak memory 200048 kb
Host smart-aa2eefd2-68e3-4cda-8cbd-82dff02e6729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074179764 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.3074179764
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.3521262903
Short name T273
Test name
Test status
Simulation time 13221224 ps
CPU time 0.6 seconds
Started Jun 26 06:19:02 PM PDT 24
Finished Jun 26 06:19:04 PM PDT 24
Peak memory 195864 kb
Host smart-f06a636d-8ac8-4b24-8856-4efe51fe30a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521262903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.3521262903
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2928584870
Short name T297
Test name
Test status
Simulation time 7361803548 ps
CPU time 45.39 seconds
Started Jun 26 06:19:03 PM PDT 24
Finished Jun 26 06:19:50 PM PDT 24
Peak memory 216516 kb
Host smart-b788b1b7-eb7f-4c67-9735-d62bedf4580e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928584870 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2928584870
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.3102390878
Short name T265
Test name
Test status
Simulation time 1201622939 ps
CPU time 61.01 seconds
Started Jun 26 06:19:03 PM PDT 24
Finished Jun 26 06:20:06 PM PDT 24
Peak memory 200020 kb
Host smart-91286cdc-bf3c-4cb0-95b8-e603140ca484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102390878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.3102390878
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.335905036
Short name T409
Test name
Test status
Simulation time 283956802 ps
CPU time 87.45 seconds
Started Jun 26 06:19:02 PM PDT 24
Finished Jun 26 06:20:30 PM PDT 24
Peak memory 443456 kb
Host smart-730723f2-a68c-4ab1-9c1b-35f42be1c1d4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=335905036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.335905036
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.1596618534
Short name T116
Test name
Test status
Simulation time 1422412739 ps
CPU time 75.37 seconds
Started Jun 26 06:19:03 PM PDT 24
Finished Jun 26 06:20:20 PM PDT 24
Peak memory 200068 kb
Host smart-e48cbdc0-cf85-4990-91b8-b70b4b9bceed
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596618534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.1596618534
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.973700531
Short name T214
Test name
Test status
Simulation time 1986147151 ps
CPU time 61.1 seconds
Started Jun 26 06:19:03 PM PDT 24
Finished Jun 26 06:20:05 PM PDT 24
Peak memory 199968 kb
Host smart-8613053a-10f8-49d7-9014-26ece3cf9437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973700531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.973700531
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.321953506
Short name T620
Test name
Test status
Simulation time 3987936325 ps
CPU time 18.91 seconds
Started Jun 26 06:19:01 PM PDT 24
Finished Jun 26 06:19:20 PM PDT 24
Peak memory 200136 kb
Host smart-591ad6c3-3ba1-4365-9d9c-adbbf555aebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321953506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.321953506
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_test_hmac_vectors.2346989277
Short name T329
Test name
Test status
Simulation time 386785129 ps
CPU time 1.14 seconds
Started Jun 26 06:19:02 PM PDT 24
Finished Jun 26 06:19:04 PM PDT 24
Peak memory 199980 kb
Host smart-9d377a98-d9bf-4f1b-9456-4dbc421dc517
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346989277 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac_vectors.2346989277
Directory /workspace/18.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha256_vectors.2096953766
Short name T565
Test name
Test status
Simulation time 6489200113 ps
CPU time 386.19 seconds
Started Jun 26 06:19:03 PM PDT 24
Finished Jun 26 06:25:31 PM PDT 24
Peak memory 200000 kb
Host smart-4683a613-d7fe-4dc1-8b0c-f529243c8473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2096953766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha256_vectors.2096953766
Directory /workspace/18.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha384_vectors.3388503243
Short name T596
Test name
Test status
Simulation time 66153116895 ps
CPU time 1894.66 seconds
Started Jun 26 06:19:04 PM PDT 24
Finished Jun 26 06:50:41 PM PDT 24
Peak memory 215536 kb
Host smart-ade03801-7d5d-4200-b0bd-d285fa4530e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3388503243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha384_vectors.3388503243
Directory /workspace/18.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha512_vectors.3061386651
Short name T666
Test name
Test status
Simulation time 309428354971 ps
CPU time 2135.56 seconds
Started Jun 26 06:19:05 PM PDT 24
Finished Jun 26 06:54:42 PM PDT 24
Peak memory 215492 kb
Host smart-c999a5d4-bb8e-4a10-bff4-fde85f435d3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3061386651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha512_vectors.3061386651
Directory /workspace/18.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.3678857602
Short name T220
Test name
Test status
Simulation time 518470822 ps
CPU time 4.06 seconds
Started Jun 26 06:19:02 PM PDT 24
Finished Jun 26 06:19:08 PM PDT 24
Peak memory 199956 kb
Host smart-51ae10c0-7e7f-4dea-be57-472c5b678d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678857602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.3678857602
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.2318787951
Short name T178
Test name
Test status
Simulation time 25006889 ps
CPU time 0.59 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:19:16 PM PDT 24
Peak memory 195072 kb
Host smart-5c35ee70-b7c0-429c-b478-0c1a8f1dfa31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318787951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.2318787951
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.873472529
Short name T644
Test name
Test status
Simulation time 4383499937 ps
CPU time 64.45 seconds
Started Jun 26 06:19:07 PM PDT 24
Finished Jun 26 06:20:13 PM PDT 24
Peak memory 200132 kb
Host smart-606aee34-1f01-4ff6-85ba-d01cab8706d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873472529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.873472529
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.2361964026
Short name T408
Test name
Test status
Simulation time 2348059704 ps
CPU time 469.46 seconds
Started Jun 26 06:19:03 PM PDT 24
Finished Jun 26 06:26:54 PM PDT 24
Peak memory 707520 kb
Host smart-56bca6b1-ec15-454d-9084-e44ea50f281b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2361964026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.2361964026
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_error.3302688438
Short name T278
Test name
Test status
Simulation time 8231450414 ps
CPU time 133.08 seconds
Started Jun 26 06:19:01 PM PDT 24
Finished Jun 26 06:21:15 PM PDT 24
Peak memory 200088 kb
Host smart-1bc86e41-fd1f-465e-955b-f4afa18dd3c9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302688438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3302688438
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/default/19.hmac_long_msg.1967703665
Short name T549
Test name
Test status
Simulation time 23827656003 ps
CPU time 119.16 seconds
Started Jun 26 06:19:00 PM PDT 24
Finished Jun 26 06:21:01 PM PDT 24
Peak memory 216508 kb
Host smart-2506a057-4f73-4f06-a46d-16b59e6023b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967703665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.1967703665
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.2967268378
Short name T165
Test name
Test status
Simulation time 2968611684 ps
CPU time 16.85 seconds
Started Jun 26 06:19:04 PM PDT 24
Finished Jun 26 06:19:22 PM PDT 24
Peak memory 200148 kb
Host smart-c28adaf3-1867-47a4-baf0-453bf811ee4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967268378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.2967268378
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_test_hmac_vectors.1353235085
Short name T227
Test name
Test status
Simulation time 285344558 ps
CPU time 1.11 seconds
Started Jun 26 06:19:13 PM PDT 24
Finished Jun 26 06:19:15 PM PDT 24
Peak memory 199632 kb
Host smart-2e88cbb8-6dbc-473c-946e-98436598e832
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353235085 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac_vectors.1353235085
Directory /workspace/19.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha256_vectors.1141700344
Short name T295
Test name
Test status
Simulation time 243249418674 ps
CPU time 483.04 seconds
Started Jun 26 06:19:02 PM PDT 24
Finished Jun 26 06:27:06 PM PDT 24
Peak memory 200108 kb
Host smart-c97e0409-3659-44e3-9025-e667a1a0a213
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1141700344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha256_vectors.1141700344
Directory /workspace/19.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha384_vectors.4162694670
Short name T50
Test name
Test status
Simulation time 132206978508 ps
CPU time 1982.08 seconds
Started Jun 26 06:19:05 PM PDT 24
Finished Jun 26 06:52:08 PM PDT 24
Peak memory 216268 kb
Host smart-644331fc-8f25-4a1e-ac04-bd5a9d4e3357
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4162694670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha384_vectors.4162694670
Directory /workspace/19.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha512_vectors.2801442037
Short name T477
Test name
Test status
Simulation time 127593227013 ps
CPU time 1673.97 seconds
Started Jun 26 06:19:16 PM PDT 24
Finished Jun 26 06:47:12 PM PDT 24
Peak memory 215504 kb
Host smart-2302c401-50d3-488e-8193-5375b87ffc43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2801442037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha512_vectors.2801442037
Directory /workspace/19.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.2837988705
Short name T647
Test name
Test status
Simulation time 234856013 ps
CPU time 4.83 seconds
Started Jun 26 06:19:01 PM PDT 24
Finished Jun 26 06:19:06 PM PDT 24
Peak memory 200104 kb
Host smart-1dbac28a-0ed3-4615-a83b-af3a4d78430c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837988705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.2837988705
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.704420639
Short name T314
Test name
Test status
Simulation time 19463504 ps
CPU time 0.62 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:18:27 PM PDT 24
Peak memory 196844 kb
Host smart-20b87093-acfc-4280-9d53-e76fa974754b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704420639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.704420639
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.1137902336
Short name T630
Test name
Test status
Simulation time 633440009 ps
CPU time 32.53 seconds
Started Jun 26 06:18:12 PM PDT 24
Finished Jun 26 06:18:46 PM PDT 24
Peak memory 200080 kb
Host smart-e31322d1-be7f-4bff-8a3b-18b9ae06ff6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137902336 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.1137902336
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.2407042674
Short name T179
Test name
Test status
Simulation time 232245559 ps
CPU time 3.79 seconds
Started Jun 26 06:18:11 PM PDT 24
Finished Jun 26 06:18:16 PM PDT 24
Peak memory 199992 kb
Host smart-8fd3dc93-463c-4af3-b8cf-f2cd0fc5dad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407042674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.2407042674
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2299293263
Short name T469
Test name
Test status
Simulation time 1911929649 ps
CPU time 458.07 seconds
Started Jun 26 06:18:13 PM PDT 24
Finished Jun 26 06:25:52 PM PDT 24
Peak memory 656548 kb
Host smart-61749ea4-e386-4154-861b-68d54236f779
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2299293263 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2299293263
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.4293901907
Short name T236
Test name
Test status
Simulation time 10663446447 ps
CPU time 188.46 seconds
Started Jun 26 06:18:10 PM PDT 24
Finished Jun 26 06:21:19 PM PDT 24
Peak memory 199960 kb
Host smart-7cf8d837-25af-4d2a-88a9-269363078b36
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293901907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.4293901907
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.3701166297
Short name T607
Test name
Test status
Simulation time 6172428486 ps
CPU time 58.14 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:19:24 PM PDT 24
Peak memory 200076 kb
Host smart-a24726a7-f54f-4771-b7cd-74c86e554b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701166297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.3701166297
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.4046453844
Short name T43
Test name
Test status
Simulation time 160102602 ps
CPU time 1.01 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:18:28 PM PDT 24
Peak memory 219260 kb
Host smart-2c89fbeb-d61f-4681-88c3-0894f18b6d69
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046453844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.4046453844
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.2704417948
Short name T635
Test name
Test status
Simulation time 330420021 ps
CPU time 4.87 seconds
Started Jun 26 06:18:12 PM PDT 24
Finished Jun 26 06:18:18 PM PDT 24
Peak memory 199992 kb
Host smart-434b0624-0e94-4e1d-8a6b-b9560a06dc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704417948 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.2704417948
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac_vectors.1959615509
Short name T194
Test name
Test status
Simulation time 82083513 ps
CPU time 1.37 seconds
Started Jun 26 06:18:11 PM PDT 24
Finished Jun 26 06:18:13 PM PDT 24
Peak memory 200068 kb
Host smart-6e4bff61-55c8-4bea-b167-9956da6dacf4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959615509 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac_vectors.1959615509
Directory /workspace/2.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.3957236828
Short name T628
Test name
Test status
Simulation time 7332006989 ps
CPU time 426.46 seconds
Started Jun 26 06:18:11 PM PDT 24
Finished Jun 26 06:25:19 PM PDT 24
Peak memory 200120 kb
Host smart-3f8c85d3-bc7c-4444-b444-4687da2224af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3957236828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.3957236828
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.1748650232
Short name T340
Test name
Test status
Simulation time 54878015474 ps
CPU time 1768.98 seconds
Started Jun 26 06:18:11 PM PDT 24
Finished Jun 26 06:47:42 PM PDT 24
Peak memory 215576 kb
Host smart-63eb7d89-bddb-49c6-9692-89540ec7fbfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1748650232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.1748650232
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.976440607
Short name T228
Test name
Test status
Simulation time 28322299957 ps
CPU time 1517.68 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:43:45 PM PDT 24
Peak memory 216016 kb
Host smart-c26ee386-744e-46d5-8559-9ce11f104476
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=976440607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.976440607
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.664688387
Short name T556
Test name
Test status
Simulation time 5630503906 ps
CPU time 39.13 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:19:06 PM PDT 24
Peak memory 200100 kb
Host smart-8b196b7f-8541-4a49-abb4-da3f602cb0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664688387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.664688387
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.2086972985
Short name T224
Test name
Test status
Simulation time 12876390 ps
CPU time 0.59 seconds
Started Jun 26 06:19:15 PM PDT 24
Finished Jun 26 06:19:17 PM PDT 24
Peak memory 196104 kb
Host smart-70ab3490-2f53-4c70-865b-ca765f3d7cb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086972985 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.2086972985
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.961543793
Short name T358
Test name
Test status
Simulation time 2335068171 ps
CPU time 28.95 seconds
Started Jun 26 06:19:10 PM PDT 24
Finished Jun 26 06:19:42 PM PDT 24
Peak memory 200064 kb
Host smart-87955e7f-d3a6-4d8e-b899-0bcaacfc63e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=961543793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.961543793
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.1239496882
Short name T414
Test name
Test status
Simulation time 314380077 ps
CPU time 16.38 seconds
Started Jun 26 06:19:11 PM PDT 24
Finished Jun 26 06:19:30 PM PDT 24
Peak memory 200024 kb
Host smart-4aa99c37-e6ae-4fe3-84d7-71a637c0a3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239496882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.1239496882
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.76118173
Short name T659
Test name
Test status
Simulation time 7585020142 ps
CPU time 489.95 seconds
Started Jun 26 06:19:08 PM PDT 24
Finished Jun 26 06:27:19 PM PDT 24
Peak memory 674776 kb
Host smart-9cef64e4-158b-4507-a321-7973adcbe2f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=76118173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.76118173
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.1484131474
Short name T345
Test name
Test status
Simulation time 1900934959 ps
CPU time 26.83 seconds
Started Jun 26 06:19:10 PM PDT 24
Finished Jun 26 06:19:39 PM PDT 24
Peak memory 199988 kb
Host smart-905ed243-6783-4ce6-b763-1b1743d1257d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484131474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.1484131474
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1519438059
Short name T114
Test name
Test status
Simulation time 2227617435 ps
CPU time 10.16 seconds
Started Jun 26 06:19:09 PM PDT 24
Finished Jun 26 06:19:21 PM PDT 24
Peak memory 200080 kb
Host smart-3d99c93d-64e0-40a9-83a1-79a0645692ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519438059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1519438059
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.176484206
Short name T202
Test name
Test status
Simulation time 233078558 ps
CPU time 10.3 seconds
Started Jun 26 06:19:09 PM PDT 24
Finished Jun 26 06:19:21 PM PDT 24
Peak memory 200016 kb
Host smart-7c3ba328-52fd-43ea-afa7-57d319359e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176484206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.176484206
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac_vectors.539776101
Short name T200
Test name
Test status
Simulation time 319879168 ps
CPU time 1.41 seconds
Started Jun 26 06:19:09 PM PDT 24
Finished Jun 26 06:19:13 PM PDT 24
Peak memory 200068 kb
Host smart-0c4c019a-4e1e-4e0e-b759-da1f5aa60dc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539776101 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac_vectors.539776101
Directory /workspace/20.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha256_vectors.3927553629
Short name T472
Test name
Test status
Simulation time 182869949997 ps
CPU time 535.86 seconds
Started Jun 26 06:19:16 PM PDT 24
Finished Jun 26 06:28:14 PM PDT 24
Peak memory 200060 kb
Host smart-b296cade-1f6a-4520-bd07-3d4abec28d8e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3927553629 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha256_vectors.3927553629
Directory /workspace/20.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha384_vectors.2014268906
Short name T642
Test name
Test status
Simulation time 460991952190 ps
CPU time 1914.93 seconds
Started Jun 26 06:19:11 PM PDT 24
Finished Jun 26 06:51:08 PM PDT 24
Peak memory 216428 kb
Host smart-d0509410-3c57-4085-91ba-f4f75946be83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2014268906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha384_vectors.2014268906
Directory /workspace/20.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha512_vectors.3767100740
Short name T641
Test name
Test status
Simulation time 44590648366 ps
CPU time 1819.31 seconds
Started Jun 26 06:19:12 PM PDT 24
Finished Jun 26 06:49:33 PM PDT 24
Peak memory 215604 kb
Host smart-416fe71e-1285-4391-9ad3-3a4347c22cd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3767100740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha512_vectors.3767100740
Directory /workspace/20.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.3586505061
Short name T496
Test name
Test status
Simulation time 869449383 ps
CPU time 25.46 seconds
Started Jun 26 06:19:07 PM PDT 24
Finished Jun 26 06:19:34 PM PDT 24
Peak memory 200084 kb
Host smart-f2260af6-3c5b-4136-bb91-421ee96e9977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586505061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.3586505061
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.1656295329
Short name T188
Test name
Test status
Simulation time 18826686 ps
CPU time 0.6 seconds
Started Jun 26 06:19:08 PM PDT 24
Finished Jun 26 06:19:11 PM PDT 24
Peak memory 196192 kb
Host smart-fcbc5d1a-8014-4955-a701-7e53387a6822
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656295329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.1656295329
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1424825874
Short name T541
Test name
Test status
Simulation time 232632896 ps
CPU time 8.96 seconds
Started Jun 26 06:19:15 PM PDT 24
Finished Jun 26 06:19:26 PM PDT 24
Peak memory 200020 kb
Host smart-2953a339-f06d-440a-9163-fe479ac8c0dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1424825874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1424825874
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.1214152367
Short name T455
Test name
Test status
Simulation time 3674682829 ps
CPU time 46.03 seconds
Started Jun 26 06:19:10 PM PDT 24
Finished Jun 26 06:19:58 PM PDT 24
Peak memory 200144 kb
Host smart-5fe07bb6-6399-4f94-b9ab-5a0544dace7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214152367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.1214152367
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.983042233
Short name T289
Test name
Test status
Simulation time 2107274792 ps
CPU time 538.55 seconds
Started Jun 26 06:19:07 PM PDT 24
Finished Jun 26 06:28:07 PM PDT 24
Peak memory 660208 kb
Host smart-cd43e44b-9951-4013-be97-621eb30718ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=983042233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.983042233
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.3004446912
Short name T392
Test name
Test status
Simulation time 11621837355 ps
CPU time 29.26 seconds
Started Jun 26 06:19:12 PM PDT 24
Finished Jun 26 06:19:43 PM PDT 24
Peak memory 200120 kb
Host smart-9ad11b75-5c43-43fd-a9ab-cce19f29dfa9
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004446912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.3004446912
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1907459284
Short name T290
Test name
Test status
Simulation time 3315898488 ps
CPU time 50.47 seconds
Started Jun 26 06:19:16 PM PDT 24
Finished Jun 26 06:20:08 PM PDT 24
Peak memory 200208 kb
Host smart-b27d2a6e-a817-47ba-9683-a3073d40b0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907459284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1907459284
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.2654858939
Short name T433
Test name
Test status
Simulation time 375292625 ps
CPU time 4.7 seconds
Started Jun 26 06:19:11 PM PDT 24
Finished Jun 26 06:19:17 PM PDT 24
Peak memory 200080 kb
Host smart-d389e92a-4067-40c2-b9f0-db737f53560e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654858939 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.2654858939
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_test_hmac_vectors.1176887459
Short name T664
Test name
Test status
Simulation time 297798138 ps
CPU time 1.3 seconds
Started Jun 26 06:19:10 PM PDT 24
Finished Jun 26 06:19:13 PM PDT 24
Peak memory 199956 kb
Host smart-68eaedd4-1abb-4211-9048-10d9c28fda06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176887459 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac_vectors.1176887459
Directory /workspace/21.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha256_vectors.397106587
Short name T245
Test name
Test status
Simulation time 16165162338 ps
CPU time 429.78 seconds
Started Jun 26 06:19:08 PM PDT 24
Finished Jun 26 06:26:19 PM PDT 24
Peak memory 200112 kb
Host smart-3b0a4771-7625-4588-ba43-3b2c1f8fac98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=397106587 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha256_vectors.397106587
Directory /workspace/21.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha384_vectors.135330296
Short name T425
Test name
Test status
Simulation time 31116570958 ps
CPU time 1717.29 seconds
Started Jun 26 06:19:08 PM PDT 24
Finished Jun 26 06:47:47 PM PDT 24
Peak memory 215628 kb
Host smart-d3e5587b-2aeb-4c90-82d9-aebf325950e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=135330296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha384_vectors.135330296
Directory /workspace/21.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha512_vectors.2759285947
Short name T385
Test name
Test status
Simulation time 65130674737 ps
CPU time 1667.02 seconds
Started Jun 26 06:19:11 PM PDT 24
Finished Jun 26 06:47:00 PM PDT 24
Peak memory 215688 kb
Host smart-6063b16c-2d68-465a-b06c-b700bceec809
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2759285947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha512_vectors.2759285947
Directory /workspace/21.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3015792384
Short name T105
Test name
Test status
Simulation time 5933716256 ps
CPU time 69.82 seconds
Started Jun 26 06:19:13 PM PDT 24
Finished Jun 26 06:20:24 PM PDT 24
Peak memory 200052 kb
Host smart-bdb8ac60-b176-4e8e-9012-917893c62f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015792384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3015792384
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.419722996
Short name T483
Test name
Test status
Simulation time 19232054 ps
CPU time 0.65 seconds
Started Jun 26 06:19:06 PM PDT 24
Finished Jun 26 06:19:08 PM PDT 24
Peak memory 196872 kb
Host smart-16c3ccdb-0878-4d77-a2e3-3ba76b5b9e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419722996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.419722996
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3123174907
Short name T5
Test name
Test status
Simulation time 249712520 ps
CPU time 7 seconds
Started Jun 26 06:19:10 PM PDT 24
Finished Jun 26 06:19:20 PM PDT 24
Peak memory 200032 kb
Host smart-7c4cfaf1-0a98-40cf-8cad-9eb6e1624747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3123174907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3123174907
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2660935689
Short name T507
Test name
Test status
Simulation time 658873272 ps
CPU time 15.26 seconds
Started Jun 26 06:19:09 PM PDT 24
Finished Jun 26 06:19:26 PM PDT 24
Peak memory 199988 kb
Host smart-d3ac644f-fd88-40a3-8cc6-f958225007a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660935689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2660935689
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.2981021737
Short name T616
Test name
Test status
Simulation time 1527133254 ps
CPU time 317.81 seconds
Started Jun 26 06:19:11 PM PDT 24
Finished Jun 26 06:24:31 PM PDT 24
Peak memory 455832 kb
Host smart-ab9b607e-3bed-4c5c-89bb-b0e4e7bbc099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2981021737 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.2981021737
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.2509412855
Short name T486
Test name
Test status
Simulation time 1735913293 ps
CPU time 97.78 seconds
Started Jun 26 06:19:09 PM PDT 24
Finished Jun 26 06:20:49 PM PDT 24
Peak memory 200096 kb
Host smart-601e66db-d4e6-4d05-8fd7-da8a603e8361
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509412855 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.2509412855
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.2775977930
Short name T254
Test name
Test status
Simulation time 26593031488 ps
CPU time 51.37 seconds
Started Jun 26 06:19:16 PM PDT 24
Finished Jun 26 06:20:09 PM PDT 24
Peak memory 200168 kb
Host smart-3cabbfe3-0e40-48d7-8c29-509630ebb7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775977930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.2775977930
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2248703496
Short name T424
Test name
Test status
Simulation time 1706538977 ps
CPU time 15.81 seconds
Started Jun 26 06:19:08 PM PDT 24
Finished Jun 26 06:19:25 PM PDT 24
Peak memory 200036 kb
Host smart-a16c3e29-d941-4f30-ae58-b332215e1242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248703496 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2248703496
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac_vectors.1098067669
Short name T320
Test name
Test status
Simulation time 60857141 ps
CPU time 1.16 seconds
Started Jun 26 06:19:09 PM PDT 24
Finished Jun 26 06:19:12 PM PDT 24
Peak memory 199904 kb
Host smart-c0134025-65aa-48e6-a446-9487415a1fa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098067669 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac_vectors.1098067669
Directory /workspace/22.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha256_vectors.2083040871
Short name T318
Test name
Test status
Simulation time 42452434180 ps
CPU time 515.66 seconds
Started Jun 26 06:19:10 PM PDT 24
Finished Jun 26 06:27:48 PM PDT 24
Peak memory 200008 kb
Host smart-bc36ddbc-5c16-4362-86f0-e6d3b94354de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2083040871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha256_vectors.2083040871
Directory /workspace/22.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/23.hmac_alert_test.1475512307
Short name T430
Test name
Test status
Simulation time 47765675 ps
CPU time 0.59 seconds
Started Jun 26 06:19:16 PM PDT 24
Finished Jun 26 06:19:18 PM PDT 24
Peak memory 196876 kb
Host smart-83d7b643-5cc0-414b-b81c-4c1c6af37e8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475512307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.1475512307
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.1046257705
Short name T19
Test name
Test status
Simulation time 1535601261 ps
CPU time 39.55 seconds
Started Jun 26 06:19:15 PM PDT 24
Finished Jun 26 06:19:57 PM PDT 24
Peak memory 200076 kb
Host smart-fe22b7f8-654f-4300-b33a-dcdc0a9d44a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1046257705 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.1046257705
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.1180984815
Short name T542
Test name
Test status
Simulation time 903221413 ps
CPU time 49.44 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:20:04 PM PDT 24
Peak memory 200028 kb
Host smart-52cea28c-3ff2-4743-b5eb-afd0c3df0a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180984815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.1180984815
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3019200033
Short name T627
Test name
Test status
Simulation time 2024486317 ps
CPU time 432.82 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:26:29 PM PDT 24
Peak memory 661772 kb
Host smart-ece498ce-cb54-4ffe-a276-c2fbe080afc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3019200033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3019200033
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.3762507926
Short name T589
Test name
Test status
Simulation time 23602535844 ps
CPU time 67.78 seconds
Started Jun 26 06:19:16 PM PDT 24
Finished Jun 26 06:20:26 PM PDT 24
Peak memory 200048 kb
Host smart-5caab85f-605c-4179-a7f1-211b11058bb6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762507926 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.3762507926
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.4228793621
Short name T198
Test name
Test status
Simulation time 1012247519 ps
CPU time 18.06 seconds
Started Jun 26 06:19:11 PM PDT 24
Finished Jun 26 06:19:31 PM PDT 24
Peak memory 200080 kb
Host smart-3a947880-a08a-48db-ac27-243408e1ae5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228793621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.4228793621
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.284125235
Short name T579
Test name
Test status
Simulation time 44550948 ps
CPU time 1.84 seconds
Started Jun 26 06:19:12 PM PDT 24
Finished Jun 26 06:19:16 PM PDT 24
Peak memory 200004 kb
Host smart-2b7b7f10-5726-4710-abaa-c4d627360a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284125235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.284125235
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_test_hmac_vectors.1553592917
Short name T306
Test name
Test status
Simulation time 71899987 ps
CPU time 1.32 seconds
Started Jun 26 06:19:17 PM PDT 24
Finished Jun 26 06:19:19 PM PDT 24
Peak memory 200000 kb
Host smart-65657443-f7b0-415d-a024-30854b257b27
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553592917 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac_vectors.1553592917
Directory /workspace/23.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha256_vectors.3282833245
Short name T303
Test name
Test status
Simulation time 13211968331 ps
CPU time 375.5 seconds
Started Jun 26 06:19:18 PM PDT 24
Finished Jun 26 06:25:34 PM PDT 24
Peak memory 200044 kb
Host smart-9ced2453-d714-44db-9623-33a33472be21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3282833245 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha256_vectors.3282833245
Directory /workspace/23.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha384_vectors.1293756166
Short name T195
Test name
Test status
Simulation time 626685022880 ps
CPU time 1806.43 seconds
Started Jun 26 06:19:13 PM PDT 24
Finished Jun 26 06:49:21 PM PDT 24
Peak memory 215952 kb
Host smart-148f5caf-3373-4561-beb2-1ea15e78a808
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1293756166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha384_vectors.1293756166
Directory /workspace/23.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha512_vectors.875332839
Short name T523
Test name
Test status
Simulation time 518863070862 ps
CPU time 1967.3 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:52:03 PM PDT 24
Peak memory 215772 kb
Host smart-622e31a5-fbff-4df1-81a7-eb0782a06e83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=875332839 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha512_vectors.875332839
Directory /workspace/23.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.3384270572
Short name T77
Test name
Test status
Simulation time 23351658588 ps
CPU time 62.25 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:20:17 PM PDT 24
Peak memory 200124 kb
Host smart-f4165b27-b781-411b-ba98-0f75681e0f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384270572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.3384270572
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.2752896186
Short name T208
Test name
Test status
Simulation time 14085029 ps
CPU time 0.63 seconds
Started Jun 26 06:19:15 PM PDT 24
Finished Jun 26 06:19:17 PM PDT 24
Peak memory 195796 kb
Host smart-f4726ecb-14e7-46ab-939d-e36bc4f36ad8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752896186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.2752896186
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2607285177
Short name T411
Test name
Test status
Simulation time 918703562 ps
CPU time 34.54 seconds
Started Jun 26 06:19:16 PM PDT 24
Finished Jun 26 06:19:52 PM PDT 24
Peak memory 200040 kb
Host smart-99eef76f-f72f-4dda-ada2-14142b78c121
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2607285177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2607285177
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.2503379055
Short name T26
Test name
Test status
Simulation time 670818268 ps
CPU time 7.38 seconds
Started Jun 26 06:19:15 PM PDT 24
Finished Jun 26 06:19:24 PM PDT 24
Peak memory 200008 kb
Host smart-d01a0280-4df7-42fe-8f34-506e376a8198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503379055 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.2503379055
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.2701015838
Short name T232
Test name
Test status
Simulation time 44712910 ps
CPU time 0.8 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:19:17 PM PDT 24
Peak memory 198224 kb
Host smart-43dc99d7-1016-4fda-846f-31e410503039
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2701015838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.2701015838
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.1327862297
Short name T174
Test name
Test status
Simulation time 4471870898 ps
CPU time 78.27 seconds
Started Jun 26 06:19:17 PM PDT 24
Finished Jun 26 06:20:37 PM PDT 24
Peak memory 200128 kb
Host smart-69f671bf-1166-48de-b57c-95f32de397be
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327862297 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.1327862297
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1016885121
Short name T528
Test name
Test status
Simulation time 6304246534 ps
CPU time 77.82 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:20:33 PM PDT 24
Peak memory 200048 kb
Host smart-1cc32ec1-8a65-44ad-b208-9386649d88a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016885121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1016885121
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.1308771238
Short name T639
Test name
Test status
Simulation time 2227891557 ps
CPU time 14.67 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:19:30 PM PDT 24
Peak memory 200308 kb
Host smart-0723e89e-1694-4565-b5e8-5e2720bb7875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308771238 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.1308771238
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_stress_all.842143180
Short name T600
Test name
Test status
Simulation time 5407600190 ps
CPU time 1072.67 seconds
Started Jun 26 06:19:16 PM PDT 24
Finished Jun 26 06:37:11 PM PDT 24
Peak memory 719140 kb
Host smart-157bf1af-2427-4625-8546-b5482dfc7258
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842143180 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.842143180
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_test_hmac_vectors.2438480496
Short name T592
Test name
Test status
Simulation time 141260249 ps
CPU time 1.09 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:19:17 PM PDT 24
Peak memory 199980 kb
Host smart-5dc91059-c469-4e1b-a42b-8580c213544c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438480496 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac_vectors.2438480496
Directory /workspace/24.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha256_vectors.2628195858
Short name T4
Test name
Test status
Simulation time 156522410601 ps
CPU time 498.63 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:27:35 PM PDT 24
Peak memory 199948 kb
Host smart-a79390ac-7260-4944-8bad-065f09f81c6f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2628195858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha256_vectors.2628195858
Directory /workspace/24.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha384_vectors.1339968873
Short name T276
Test name
Test status
Simulation time 110138555538 ps
CPU time 1828.89 seconds
Started Jun 26 06:19:15 PM PDT 24
Finished Jun 26 06:49:46 PM PDT 24
Peak memory 215940 kb
Host smart-a60b8322-4770-4ec5-934a-d9b2a910ad69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1339968873 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha384_vectors.1339968873
Directory /workspace/24.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha512_vectors.274579373
Short name T520
Test name
Test status
Simulation time 106044040713 ps
CPU time 1546.7 seconds
Started Jun 26 06:19:15 PM PDT 24
Finished Jun 26 06:45:04 PM PDT 24
Peak memory 215536 kb
Host smart-77e33203-2529-4aa2-b127-7a827287a9a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=274579373 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha512_vectors.274579373
Directory /workspace/24.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.1922108675
Short name T17
Test name
Test status
Simulation time 2392259151 ps
CPU time 34.63 seconds
Started Jun 26 06:19:13 PM PDT 24
Finished Jun 26 06:19:49 PM PDT 24
Peak memory 200132 kb
Host smart-b8a063e7-3cf9-4000-ab92-3708cb6509cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922108675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.1922108675
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.4018976534
Short name T176
Test name
Test status
Simulation time 12163770 ps
CPU time 0.61 seconds
Started Jun 26 06:19:20 PM PDT 24
Finished Jun 26 06:19:21 PM PDT 24
Peak memory 195736 kb
Host smart-15b9dbc9-8b83-437b-9905-033313cd9d8e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018976534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.4018976534
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.965212712
Short name T7
Test name
Test status
Simulation time 488353216 ps
CPU time 23.11 seconds
Started Jun 26 06:19:16 PM PDT 24
Finished Jun 26 06:19:41 PM PDT 24
Peak memory 200032 kb
Host smart-f5b9b982-2633-4e5d-a9e4-ffb376e19cd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=965212712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.965212712
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.4031489810
Short name T631
Test name
Test status
Simulation time 7206425750 ps
CPU time 65.37 seconds
Started Jun 26 06:19:18 PM PDT 24
Finished Jun 26 06:20:24 PM PDT 24
Peak memory 200152 kb
Host smart-60e26fee-6917-4198-9872-dcb88fbd613b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031489810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.4031489810
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.3177065759
Short name T605
Test name
Test status
Simulation time 9393860186 ps
CPU time 654.42 seconds
Started Jun 26 06:19:11 PM PDT 24
Finished Jun 26 06:30:08 PM PDT 24
Peak memory 734112 kb
Host smart-9e4ab962-7d92-496f-97df-5e67b61f7630
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3177065759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.3177065759
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.2295185836
Short name T199
Test name
Test status
Simulation time 5766598054 ps
CPU time 5.49 seconds
Started Jun 26 06:19:15 PM PDT 24
Finished Jun 26 06:19:22 PM PDT 24
Peak memory 200016 kb
Host smart-31896534-79e6-40bb-bf03-c8f435c4f99b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295185836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.2295185836
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.3450069075
Short name T454
Test name
Test status
Simulation time 4178573001 ps
CPU time 59.72 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:20:15 PM PDT 24
Peak memory 200164 kb
Host smart-7656886e-04c4-45a0-97fa-a7d8aa09b54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450069075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.3450069075
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.456746736
Short name T651
Test name
Test status
Simulation time 614947796 ps
CPU time 5.06 seconds
Started Jun 26 06:19:17 PM PDT 24
Finished Jun 26 06:19:23 PM PDT 24
Peak memory 200028 kb
Host smart-aa7f3b13-e26a-43e5-b1da-92378fa52e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456746736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.456746736
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_test_hmac_vectors.622633925
Short name T284
Test name
Test status
Simulation time 170311820 ps
CPU time 1.19 seconds
Started Jun 26 06:19:23 PM PDT 24
Finished Jun 26 06:19:26 PM PDT 24
Peak memory 199936 kb
Host smart-cf5f1296-1c0c-4f81-b776-b3bedf5ff18f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622633925 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac_vectors.622633925
Directory /workspace/25.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha256_vectors.3317932588
Short name T493
Test name
Test status
Simulation time 108487108622 ps
CPU time 444.79 seconds
Started Jun 26 06:19:16 PM PDT 24
Finished Jun 26 06:26:42 PM PDT 24
Peak memory 200080 kb
Host smart-70b637fa-0e8d-4991-98fb-0ddeb5e68eef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3317932588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha256_vectors.3317932588
Directory /workspace/25.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha384_vectors.2621059539
Short name T593
Test name
Test status
Simulation time 211156967373 ps
CPU time 1940.37 seconds
Started Jun 26 06:19:22 PM PDT 24
Finished Jun 26 06:51:45 PM PDT 24
Peak memory 216232 kb
Host smart-82bb1548-947f-4741-99f7-1f23e1309a67
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2621059539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha384_vectors.2621059539
Directory /workspace/25.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha512_vectors.411918116
Short name T360
Test name
Test status
Simulation time 134640261773 ps
CPU time 1861.95 seconds
Started Jun 26 06:19:24 PM PDT 24
Finished Jun 26 06:50:29 PM PDT 24
Peak memory 216476 kb
Host smart-96124e69-cde5-423b-a181-5ae05b5312b7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=411918116 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha512_vectors.411918116
Directory /workspace/25.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.2489921847
Short name T655
Test name
Test status
Simulation time 458429647 ps
CPU time 5.05 seconds
Started Jun 26 06:19:14 PM PDT 24
Finished Jun 26 06:19:20 PM PDT 24
Peak memory 200088 kb
Host smart-30942269-3d52-4ab3-a922-695e4996007f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489921847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.2489921847
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.2015831924
Short name T612
Test name
Test status
Simulation time 22985878 ps
CPU time 0.58 seconds
Started Jun 26 06:19:25 PM PDT 24
Finished Jun 26 06:19:29 PM PDT 24
Peak memory 195684 kb
Host smart-2826c263-0dd4-4d7a-9e97-f3fee72987b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015831924 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.2015831924
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.691583331
Short name T657
Test name
Test status
Simulation time 808214449 ps
CPU time 19.01 seconds
Started Jun 26 06:19:22 PM PDT 24
Finished Jun 26 06:19:44 PM PDT 24
Peak memory 200036 kb
Host smart-d698be01-6a98-4b06-84eb-22217f86937d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=691583331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.691583331
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.665572963
Short name T177
Test name
Test status
Simulation time 8300778874 ps
CPU time 58.04 seconds
Started Jun 26 06:19:23 PM PDT 24
Finished Jun 26 06:20:24 PM PDT 24
Peak memory 200140 kb
Host smart-61a38d79-488b-4b1d-81ec-18d347b11aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665572963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.665572963
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.2784937397
Short name T332
Test name
Test status
Simulation time 819626571 ps
CPU time 213.3 seconds
Started Jun 26 06:19:23 PM PDT 24
Finished Jun 26 06:22:58 PM PDT 24
Peak memory 653080 kb
Host smart-6fd6ae6a-7a1d-4ce9-b272-e5acf561da66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784937397 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.2784937397
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.4066510623
Short name T125
Test name
Test status
Simulation time 2779847050 ps
CPU time 82.8 seconds
Started Jun 26 06:19:21 PM PDT 24
Finished Jun 26 06:20:46 PM PDT 24
Peak memory 200136 kb
Host smart-1cf6addc-6660-4530-990a-da8d84b7eb0b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066510623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.4066510623
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.3122341316
Short name T357
Test name
Test status
Simulation time 11738355059 ps
CPU time 56.66 seconds
Started Jun 26 06:19:24 PM PDT 24
Finished Jun 26 06:20:23 PM PDT 24
Peak memory 200176 kb
Host smart-f8d14a37-d358-43a2-95b7-822dcc1920a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122341316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.3122341316
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.1769439072
Short name T511
Test name
Test status
Simulation time 104068245 ps
CPU time 1.55 seconds
Started Jun 26 06:19:21 PM PDT 24
Finished Jun 26 06:19:25 PM PDT 24
Peak memory 200064 kb
Host smart-840d2c26-af8c-4bbb-a02f-c3ba1cacf0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769439072 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.1769439072
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_test_hmac_vectors.3480932234
Short name T381
Test name
Test status
Simulation time 82264189 ps
CPU time 1.05 seconds
Started Jun 26 06:19:25 PM PDT 24
Finished Jun 26 06:19:29 PM PDT 24
Peak memory 199840 kb
Host smart-ed29642a-a179-4e4b-afa2-2efb3c583867
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480932234 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac_vectors.3480932234
Directory /workspace/26.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha256_vectors.1758106138
Short name T396
Test name
Test status
Simulation time 72672123499 ps
CPU time 523.26 seconds
Started Jun 26 06:19:22 PM PDT 24
Finished Jun 26 06:28:07 PM PDT 24
Peak memory 200008 kb
Host smart-c17ce0df-beb9-4e30-9fe4-b5fed92d488e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1758106138 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha256_vectors.1758106138
Directory /workspace/26.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha384_vectors.1380332822
Short name T426
Test name
Test status
Simulation time 156044836903 ps
CPU time 1975.48 seconds
Started Jun 26 06:19:21 PM PDT 24
Finished Jun 26 06:52:19 PM PDT 24
Peak memory 215852 kb
Host smart-987fdcd6-458c-4406-b653-df9f0f56e359
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1380332822 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha384_vectors.1380332822
Directory /workspace/26.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha512_vectors.306018322
Short name T590
Test name
Test status
Simulation time 126383484515 ps
CPU time 1778.13 seconds
Started Jun 26 06:19:22 PM PDT 24
Finished Jun 26 06:49:02 PM PDT 24
Peak memory 215388 kb
Host smart-60f2821b-087b-4752-abd5-1c3fb966001c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=306018322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha512_vectors.306018322
Directory /workspace/26.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/27.hmac_alert_test.4034714890
Short name T325
Test name
Test status
Simulation time 13519075 ps
CPU time 0.62 seconds
Started Jun 26 06:19:23 PM PDT 24
Finished Jun 26 06:19:26 PM PDT 24
Peak memory 195076 kb
Host smart-e89e8687-91f2-40a1-8da1-33db7f3d2f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034714890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.4034714890
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.2269309890
Short name T465
Test name
Test status
Simulation time 853937931 ps
CPU time 42.55 seconds
Started Jun 26 06:19:23 PM PDT 24
Finished Jun 26 06:20:08 PM PDT 24
Peak memory 199740 kb
Host smart-f8c3ba6a-9d10-4553-98a9-4c47cd2336d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2269309890 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.2269309890
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.3818211541
Short name T336
Test name
Test status
Simulation time 119732831 ps
CPU time 3.21 seconds
Started Jun 26 06:19:24 PM PDT 24
Finished Jun 26 06:19:30 PM PDT 24
Peak memory 200060 kb
Host smart-fcd2abd3-ea6e-429c-9548-7cb4603cfda3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818211541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.3818211541
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.4238300643
Short name T485
Test name
Test status
Simulation time 2957192504 ps
CPU time 434.06 seconds
Started Jun 26 06:19:24 PM PDT 24
Finished Jun 26 06:26:42 PM PDT 24
Peak memory 688584 kb
Host smart-260c9d83-8d43-4779-a23b-dc6d591d64c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4238300643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.4238300643
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3294161885
Short name T279
Test name
Test status
Simulation time 9870939957 ps
CPU time 90.61 seconds
Started Jun 26 06:19:23 PM PDT 24
Finished Jun 26 06:20:57 PM PDT 24
Peak memory 200124 kb
Host smart-d27453d7-0b4d-4b9a-80ce-4f0347638c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294161885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3294161885
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1147232917
Short name T307
Test name
Test status
Simulation time 634571482 ps
CPU time 7.38 seconds
Started Jun 26 06:19:22 PM PDT 24
Finished Jun 26 06:19:31 PM PDT 24
Peak memory 200052 kb
Host smart-e0ddc4a6-4ff9-4ae5-bdea-4057d9ef2ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147232917 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1147232917
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_test_hmac_vectors.3206130815
Short name T270
Test name
Test status
Simulation time 194423382 ps
CPU time 1.16 seconds
Started Jun 26 06:19:19 PM PDT 24
Finished Jun 26 06:19:21 PM PDT 24
Peak memory 200036 kb
Host smart-91179292-fe1e-49b5-b2eb-83e2b1f69e88
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206130815 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac_vectors.3206130815
Directory /workspace/27.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha256_vectors.3589630173
Short name T292
Test name
Test status
Simulation time 25736192568 ps
CPU time 452.4 seconds
Started Jun 26 06:19:24 PM PDT 24
Finished Jun 26 06:27:00 PM PDT 24
Peak memory 200092 kb
Host smart-0a52b365-ccf9-4ad8-ab7c-37f0377ac5e1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3589630173 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha256_vectors.3589630173
Directory /workspace/27.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha384_vectors.2248918358
Short name T626
Test name
Test status
Simulation time 114702419702 ps
CPU time 2129.05 seconds
Started Jun 26 06:19:25 PM PDT 24
Finished Jun 26 06:54:57 PM PDT 24
Peak memory 215356 kb
Host smart-978849df-e5ea-4e50-9c4a-31fc17fd22a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2248918358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha384_vectors.2248918358
Directory /workspace/27.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha512_vectors.3801981140
Short name T264
Test name
Test status
Simulation time 110516208632 ps
CPU time 2107.6 seconds
Started Jun 26 06:19:25 PM PDT 24
Finished Jun 26 06:54:36 PM PDT 24
Peak memory 215344 kb
Host smart-887c02f0-a237-450d-a2f8-595714146820
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3801981140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha512_vectors.3801981140
Directory /workspace/27.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.1866379457
Short name T574
Test name
Test status
Simulation time 17448920752 ps
CPU time 66.77 seconds
Started Jun 26 06:19:21 PM PDT 24
Finished Jun 26 06:20:29 PM PDT 24
Peak memory 200120 kb
Host smart-7a6a2fc1-fea1-43c9-afb6-a71560c75527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866379457 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.1866379457
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.3672288139
Short name T322
Test name
Test status
Simulation time 47079011 ps
CPU time 0.62 seconds
Started Jun 26 06:19:28 PM PDT 24
Finished Jun 26 06:19:31 PM PDT 24
Peak memory 195112 kb
Host smart-a27e0506-ddc9-49af-897c-9eefda8f502b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672288139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.3672288139
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.2742341069
Short name T366
Test name
Test status
Simulation time 96564137 ps
CPU time 6.44 seconds
Started Jun 26 06:19:23 PM PDT 24
Finished Jun 26 06:19:31 PM PDT 24
Peak memory 199684 kb
Host smart-cc0c4abd-3237-48d9-b4b1-4fa2445cdd23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2742341069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.2742341069
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3876169361
Short name T598
Test name
Test status
Simulation time 12275938570 ps
CPU time 71.89 seconds
Started Jun 26 06:19:24 PM PDT 24
Finished Jun 26 06:20:38 PM PDT 24
Peak memory 200152 kb
Host smart-e4512bd1-1698-4332-a582-0664e3bea1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876169361 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3876169361
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1196369162
Short name T384
Test name
Test status
Simulation time 4127266109 ps
CPU time 1100.01 seconds
Started Jun 26 06:19:25 PM PDT 24
Finished Jun 26 06:37:48 PM PDT 24
Peak memory 754164 kb
Host smart-94362a82-e1bc-4f44-8062-6f8f3135be8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1196369162 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1196369162
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.1352724520
Short name T591
Test name
Test status
Simulation time 6233992658 ps
CPU time 90.81 seconds
Started Jun 26 06:19:23 PM PDT 24
Finished Jun 26 06:20:56 PM PDT 24
Peak memory 200136 kb
Host smart-95fde15f-2f64-4bb7-98c4-a4a6b49783b1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352724520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.1352724520
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.2596991659
Short name T575
Test name
Test status
Simulation time 560473686 ps
CPU time 34.18 seconds
Started Jun 26 06:19:23 PM PDT 24
Finished Jun 26 06:20:00 PM PDT 24
Peak memory 200112 kb
Host smart-4d3385f5-12f6-4fa4-b811-4b165c07600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596991659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.2596991659
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.1302578671
Short name T282
Test name
Test status
Simulation time 1113219234 ps
CPU time 6.12 seconds
Started Jun 26 06:19:25 PM PDT 24
Finished Jun 26 06:19:34 PM PDT 24
Peak memory 200016 kb
Host smart-e893d30b-70aa-4e63-9eef-79f487ae537a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302578671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.1302578671
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_test_hmac_vectors.2118235622
Short name T15
Test name
Test status
Simulation time 33942819 ps
CPU time 1.34 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:19:31 PM PDT 24
Peak memory 200052 kb
Host smart-1a35156d-c17c-49eb-a514-61c5d7235e6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118235622 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac_vectors.2118235622
Directory /workspace/28.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha256_vectors.1801192104
Short name T444
Test name
Test status
Simulation time 59364988832 ps
CPU time 550.78 seconds
Started Jun 26 06:19:26 PM PDT 24
Finished Jun 26 06:28:40 PM PDT 24
Peak memory 200076 kb
Host smart-cbe65f04-9053-4bfe-b47a-42bed7f727bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1801192104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha256_vectors.1801192104
Directory /workspace/28.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha384_vectors.1043100459
Short name T625
Test name
Test status
Simulation time 175209360151 ps
CPU time 1824.85 seconds
Started Jun 26 06:19:30 PM PDT 24
Finished Jun 26 06:49:57 PM PDT 24
Peak memory 216420 kb
Host smart-da0296a8-78a3-4c77-8483-f2b91326604b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1043100459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha384_vectors.1043100459
Directory /workspace/28.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha512_vectors.1896886935
Short name T646
Test name
Test status
Simulation time 36574795955 ps
CPU time 2054.02 seconds
Started Jun 26 06:19:26 PM PDT 24
Finished Jun 26 06:53:44 PM PDT 24
Peak memory 208208 kb
Host smart-4be538b8-73dd-40d7-82ce-153f4677d606
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1896886935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha512_vectors.1896886935
Directory /workspace/28.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.2282068979
Short name T568
Test name
Test status
Simulation time 719962735 ps
CPU time 34.39 seconds
Started Jun 26 06:19:23 PM PDT 24
Finished Jun 26 06:19:59 PM PDT 24
Peak memory 200304 kb
Host smart-2bdae409-7211-4f04-958c-a8c86f2cb404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282068979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.2282068979
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1742543878
Short name T296
Test name
Test status
Simulation time 47088713 ps
CPU time 0.63 seconds
Started Jun 26 06:19:28 PM PDT 24
Finished Jun 26 06:19:31 PM PDT 24
Peak memory 196832 kb
Host smart-4135f7e6-d336-4f6e-aaa8-2a7437f4f1b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742543878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1742543878
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.941596419
Short name T255
Test name
Test status
Simulation time 747227088 ps
CPU time 14.44 seconds
Started Jun 26 06:19:26 PM PDT 24
Finished Jun 26 06:19:43 PM PDT 24
Peak memory 200032 kb
Host smart-5af5ec69-d580-4c60-bb71-4645a2f6a88c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=941596419 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.941596419
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.44580108
Short name T569
Test name
Test status
Simulation time 959331901 ps
CPU time 54.71 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:20:24 PM PDT 24
Peak memory 200012 kb
Host smart-9852ef7e-0796-4a1f-bb11-49a519c2fe17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44580108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.44580108
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_error.3507853208
Short name T231
Test name
Test status
Simulation time 740732485 ps
CPU time 13.91 seconds
Started Jun 26 06:19:28 PM PDT 24
Finished Jun 26 06:19:44 PM PDT 24
Peak memory 200208 kb
Host smart-17b6f4f5-a9b5-4a31-94c8-29c2a2e78fda
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507853208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.3507853208
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.963872159
Short name T538
Test name
Test status
Simulation time 18505744271 ps
CPU time 131.63 seconds
Started Jun 26 06:19:30 PM PDT 24
Finished Jun 26 06:21:43 PM PDT 24
Peak memory 200196 kb
Host smart-dd66b7b1-8390-44c7-a2d8-89c8952a6a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963872159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.963872159
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.1182326355
Short name T526
Test name
Test status
Simulation time 134942853 ps
CPU time 6.6 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:19:36 PM PDT 24
Peak memory 200036 kb
Host smart-df4fe719-3fbb-4621-84a0-a69699beec4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182326355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.1182326355
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_test_hmac_vectors.1250378819
Short name T225
Test name
Test status
Simulation time 213372121 ps
CPU time 1.2 seconds
Started Jun 26 06:19:30 PM PDT 24
Finished Jun 26 06:19:33 PM PDT 24
Peak memory 200072 kb
Host smart-9146bc17-2563-4d14-a273-024ae9a4aa60
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250378819 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac_vectors.1250378819
Directory /workspace/29.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha256_vectors.3250233158
Short name T551
Test name
Test status
Simulation time 31463099235 ps
CPU time 462.13 seconds
Started Jun 26 06:19:26 PM PDT 24
Finished Jun 26 06:27:12 PM PDT 24
Peak memory 200056 kb
Host smart-82934fa0-5f20-4193-923a-ff108eaec676
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3250233158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha256_vectors.3250233158
Directory /workspace/29.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha384_vectors.3802410598
Short name T619
Test name
Test status
Simulation time 124204039077 ps
CPU time 1700.69 seconds
Started Jun 26 06:19:25 PM PDT 24
Finished Jun 26 06:47:49 PM PDT 24
Peak memory 216432 kb
Host smart-fd43d358-e71d-491e-81c2-d0879e1a9757
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3802410598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha384_vectors.3802410598
Directory /workspace/29.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha512_vectors.3783527410
Short name T12
Test name
Test status
Simulation time 533951445675 ps
CPU time 1900.65 seconds
Started Jun 26 06:19:29 PM PDT 24
Finished Jun 26 06:51:12 PM PDT 24
Peak memory 215476 kb
Host smart-8e110731-eda5-446e-9aeb-9f41b8d81221
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3783527410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha512_vectors.3783527410
Directory /workspace/29.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.926831235
Short name T466
Test name
Test status
Simulation time 44947433391 ps
CPU time 70.83 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:20:40 PM PDT 24
Peak memory 198720 kb
Host smart-139199d5-1da9-4d89-8f19-0548f0973fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926831235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.926831235
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.186603829
Short name T609
Test name
Test status
Simulation time 15786412 ps
CPU time 0.59 seconds
Started Jun 26 06:18:21 PM PDT 24
Finished Jun 26 06:18:24 PM PDT 24
Peak memory 196848 kb
Host smart-13fe1238-2f69-4f49-bc8b-11ca92a91de5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186603829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.186603829
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.2865704608
Short name T81
Test name
Test status
Simulation time 1082818733 ps
CPU time 37.76 seconds
Started Jun 26 06:18:21 PM PDT 24
Finished Jun 26 06:19:00 PM PDT 24
Peak memory 200072 kb
Host smart-ffcd9f2d-832a-4ec9-b943-6b01798c2248
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2865704608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.2865704608
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.3364868860
Short name T577
Test name
Test status
Simulation time 156757142 ps
CPU time 8.39 seconds
Started Jun 26 06:18:20 PM PDT 24
Finished Jun 26 06:18:29 PM PDT 24
Peak memory 199892 kb
Host smart-6a28691b-5ae6-4822-9b0c-3664bf15233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364868860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.3364868860
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.1827744675
Short name T234
Test name
Test status
Simulation time 4833959880 ps
CPU time 153.84 seconds
Started Jun 26 06:18:18 PM PDT 24
Finished Jun 26 06:20:52 PM PDT 24
Peak memory 612552 kb
Host smart-3ed5269a-0477-4ad4-a771-c00c00f00ff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1827744675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.1827744675
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.324801947
Short name T122
Test name
Test status
Simulation time 2403706332 ps
CPU time 31.7 seconds
Started Jun 26 06:18:19 PM PDT 24
Finished Jun 26 06:18:52 PM PDT 24
Peak memory 200140 kb
Host smart-2699a801-abf7-47ef-bc8a-c8848a963967
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324801947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.324801947
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.1434063279
Short name T391
Test name
Test status
Simulation time 1389861326 ps
CPU time 89.4 seconds
Started Jun 26 06:18:18 PM PDT 24
Finished Jun 26 06:19:48 PM PDT 24
Peak memory 200128 kb
Host smart-78442873-8ff4-4996-bbf4-fdb15f01964c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434063279 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.1434063279
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.3393197388
Short name T576
Test name
Test status
Simulation time 673799779 ps
CPU time 8.51 seconds
Started Jun 26 06:18:13 PM PDT 24
Finished Jun 26 06:18:22 PM PDT 24
Peak memory 200088 kb
Host smart-5358db6b-4c53-4c4f-8785-f7c17a39e3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393197388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.3393197388
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_test_hmac_vectors.1456070426
Short name T237
Test name
Test status
Simulation time 317336573 ps
CPU time 1.42 seconds
Started Jun 26 06:18:19 PM PDT 24
Finished Jun 26 06:18:21 PM PDT 24
Peak memory 199684 kb
Host smart-cfa147ea-c371-471d-8000-9d30f9dc811a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456070426 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac_vectors.1456070426
Directory /workspace/3.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.2390907296
Short name T527
Test name
Test status
Simulation time 38504908388 ps
CPU time 498.59 seconds
Started Jun 26 06:18:17 PM PDT 24
Finished Jun 26 06:26:36 PM PDT 24
Peak memory 199908 kb
Host smart-687a02f3-1550-40ce-bb4b-aa7eaa840e8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2390907296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.2390907296
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.3565394236
Short name T498
Test name
Test status
Simulation time 30710288133 ps
CPU time 1762.41 seconds
Started Jun 26 06:18:21 PM PDT 24
Finished Jun 26 06:47:45 PM PDT 24
Peak memory 215956 kb
Host smart-f135ec02-1064-4dd3-b364-b6cf022aebd4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3565394236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.3565394236
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.2558095332
Short name T260
Test name
Test status
Simulation time 92663748189 ps
CPU time 1682.94 seconds
Started Jun 26 06:18:19 PM PDT 24
Finished Jun 26 06:46:23 PM PDT 24
Peak memory 216100 kb
Host smart-3b657a8a-35a9-41d2-ba09-591e39f407eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2558095332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.2558095332
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.1588954871
Short name T634
Test name
Test status
Simulation time 2860788367 ps
CPU time 39.69 seconds
Started Jun 26 06:18:18 PM PDT 24
Finished Jun 26 06:18:58 PM PDT 24
Peak memory 200100 kb
Host smart-e585f4c6-c21f-46ab-af1f-1ec001a7fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588954871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.1588954871
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/default/30.hmac_alert_test.93324572
Short name T293
Test name
Test status
Simulation time 35885609 ps
CPU time 0.59 seconds
Started Jun 26 06:19:28 PM PDT 24
Finished Jun 26 06:19:31 PM PDT 24
Peak memory 195060 kb
Host smart-5fcab69e-77c5-4888-a2ef-74af5edbe770
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93324572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.93324572
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.573874828
Short name T580
Test name
Test status
Simulation time 609964051 ps
CPU time 8.77 seconds
Started Jun 26 06:19:28 PM PDT 24
Finished Jun 26 06:19:39 PM PDT 24
Peak memory 200040 kb
Host smart-74cc45d5-4a27-4cdc-8050-3d00f29e3878
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=573874828 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.573874828
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.1487504916
Short name T476
Test name
Test status
Simulation time 950268093 ps
CPU time 52.15 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:20:22 PM PDT 24
Peak memory 200044 kb
Host smart-62bd08d8-253f-4476-81b3-bd98dacaca33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487504916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.1487504916
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.1117290974
Short name T446
Test name
Test status
Simulation time 19172191538 ps
CPU time 1108.84 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:37:59 PM PDT 24
Peak memory 724564 kb
Host smart-5004f80d-b818-4895-9a70-1a6fc15c79fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1117290974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.1117290974
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.4065021860
Short name T235
Test name
Test status
Simulation time 3947676592 ps
CPU time 55.1 seconds
Started Jun 26 06:19:30 PM PDT 24
Finished Jun 26 06:20:27 PM PDT 24
Peak memory 200132 kb
Host smart-1d5d68da-dce2-4db6-8d85-d36d3f463efd
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065021860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.4065021860
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.356432561
Short name T154
Test name
Test status
Simulation time 4994452865 ps
CPU time 84.05 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:20:54 PM PDT 24
Peak memory 198696 kb
Host smart-252eab75-b600-4bcd-aaf0-ff927431c307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356432561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.356432561
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.4255931312
Short name T460
Test name
Test status
Simulation time 711185168 ps
CPU time 7.99 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:19:38 PM PDT 24
Peak memory 200088 kb
Host smart-82b75ca4-3c03-4b29-9ce3-dd8d8fc06678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255931312 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.4255931312
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_test_hmac_vectors.1970326317
Short name T506
Test name
Test status
Simulation time 129289421 ps
CPU time 1.48 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:19:31 PM PDT 24
Peak memory 200040 kb
Host smart-875e764f-0915-4ccb-b176-cda56d04fb99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970326317 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac_vectors.1970326317
Directory /workspace/30.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha256_vectors.1195028139
Short name T431
Test name
Test status
Simulation time 217036672817 ps
CPU time 494.48 seconds
Started Jun 26 06:19:28 PM PDT 24
Finished Jun 26 06:27:45 PM PDT 24
Peak memory 200120 kb
Host smart-37091fe5-68a1-4226-aece-bc348eb60855
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1195028139 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha256_vectors.1195028139
Directory /workspace/30.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha384_vectors.3387262872
Short name T405
Test name
Test status
Simulation time 116602725489 ps
CPU time 2041.38 seconds
Started Jun 26 06:19:28 PM PDT 24
Finished Jun 26 06:53:32 PM PDT 24
Peak memory 216220 kb
Host smart-b39f15ba-c4ec-4de0-a5f6-66f1fef90224
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3387262872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha384_vectors.3387262872
Directory /workspace/30.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha512_vectors.3546815488
Short name T422
Test name
Test status
Simulation time 157863542348 ps
CPU time 1885.77 seconds
Started Jun 26 06:19:30 PM PDT 24
Finished Jun 26 06:50:58 PM PDT 24
Peak memory 216480 kb
Host smart-963ced69-ab83-4c45-8b3f-702da24f47ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3546815488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha512_vectors.3546815488
Directory /workspace/30.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.848184141
Short name T108
Test name
Test status
Simulation time 5344777229 ps
CPU time 81.9 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:20:52 PM PDT 24
Peak memory 200320 kb
Host smart-177f0b76-8d9b-46a7-9ae0-01bd8b19360e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848184141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.848184141
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.3872935488
Short name T205
Test name
Test status
Simulation time 49030557 ps
CPU time 0.63 seconds
Started Jun 26 06:19:35 PM PDT 24
Finished Jun 26 06:19:37 PM PDT 24
Peak memory 196100 kb
Host smart-dafb6f34-4bcc-45c8-8397-44f5f2666c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872935488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.3872935488
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.524204681
Short name T571
Test name
Test status
Simulation time 204445815 ps
CPU time 7.79 seconds
Started Jun 26 06:19:25 PM PDT 24
Finished Jun 26 06:19:36 PM PDT 24
Peak memory 199996 kb
Host smart-0b8a28e4-9f4a-48af-87d0-57896eda1ab3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524204681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.524204681
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.3798703516
Short name T52
Test name
Test status
Simulation time 65927160 ps
CPU time 2.15 seconds
Started Jun 26 06:19:30 PM PDT 24
Finished Jun 26 06:19:34 PM PDT 24
Peak memory 199964 kb
Host smart-ddb6a0ff-9318-4da9-88d8-9f0451579426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798703516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.3798703516
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.2206766455
Short name T529
Test name
Test status
Simulation time 8026981722 ps
CPU time 988.06 seconds
Started Jun 26 06:19:25 PM PDT 24
Finished Jun 26 06:35:57 PM PDT 24
Peak memory 750872 kb
Host smart-781ecea4-80ec-4a11-8a84-ce6b75a51786
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206766455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.2206766455
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3184280136
Short name T181
Test name
Test status
Simulation time 4666888866 ps
CPU time 9.03 seconds
Started Jun 26 06:19:26 PM PDT 24
Finished Jun 26 06:19:38 PM PDT 24
Peak memory 199996 kb
Host smart-43974abe-77f8-47e4-8fb8-efff7d873e69
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184280136 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3184280136
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.1688881807
Short name T171
Test name
Test status
Simulation time 2646163998 ps
CPU time 51.56 seconds
Started Jun 26 06:19:28 PM PDT 24
Finished Jun 26 06:20:22 PM PDT 24
Peak memory 200100 kb
Host smart-569d1a18-b5b0-49bb-bd35-e36edc762f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688881807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.1688881807
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.171560211
Short name T510
Test name
Test status
Simulation time 585860375 ps
CPU time 5.85 seconds
Started Jun 26 06:19:27 PM PDT 24
Finished Jun 26 06:19:35 PM PDT 24
Peak memory 200004 kb
Host smart-55260b60-af43-4a22-8b49-54adcc385ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171560211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.171560211
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_test_hmac_vectors.2466155378
Short name T443
Test name
Test status
Simulation time 454931635 ps
CPU time 1.38 seconds
Started Jun 26 06:19:33 PM PDT 24
Finished Jun 26 06:19:36 PM PDT 24
Peak memory 199984 kb
Host smart-a06833cc-fd84-4ee8-9ed8-9f527f0f273f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466155378 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac_vectors.2466155378
Directory /workspace/31.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha256_vectors.4127863908
Short name T447
Test name
Test status
Simulation time 56506184087 ps
CPU time 487.35 seconds
Started Jun 26 06:19:31 PM PDT 24
Finished Jun 26 06:27:39 PM PDT 24
Peak memory 200088 kb
Host smart-39ea940c-d7d8-4e50-af70-0e72948a230e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4127863908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha256_vectors.4127863908
Directory /workspace/31.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha384_vectors.3351653264
Short name T217
Test name
Test status
Simulation time 203609181721 ps
CPU time 1748.66 seconds
Started Jun 26 06:19:24 PM PDT 24
Finished Jun 26 06:48:37 PM PDT 24
Peak memory 215456 kb
Host smart-53d0b2bb-2772-4d0d-be01-8a630ca24c69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3351653264 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha384_vectors.3351653264
Directory /workspace/31.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha512_vectors.1066662652
Short name T354
Test name
Test status
Simulation time 705273386949 ps
CPU time 2165.35 seconds
Started Jun 26 06:19:33 PM PDT 24
Finished Jun 26 06:55:40 PM PDT 24
Peak memory 208328 kb
Host smart-ff0756f3-5936-44cd-8580-a3a3d0f9074f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1066662652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha512_vectors.1066662652
Directory /workspace/31.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.1299945375
Short name T109
Test name
Test status
Simulation time 1674312510 ps
CPU time 71.53 seconds
Started Jun 26 06:19:25 PM PDT 24
Finished Jun 26 06:20:40 PM PDT 24
Peak memory 199956 kb
Host smart-2b026a5e-f0b6-44a5-8c72-17c2e54051a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299945375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.1299945375
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.1102933847
Short name T310
Test name
Test status
Simulation time 31957015 ps
CPU time 0.66 seconds
Started Jun 26 06:19:33 PM PDT 24
Finished Jun 26 06:19:35 PM PDT 24
Peak memory 195772 kb
Host smart-c0eee8e7-0da7-4471-97da-61e821ad451f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102933847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.1102933847
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.2600799765
Short name T22
Test name
Test status
Simulation time 1101018630 ps
CPU time 49.03 seconds
Started Jun 26 06:19:32 PM PDT 24
Finished Jun 26 06:20:22 PM PDT 24
Peak memory 200100 kb
Host smart-9238a345-0cac-441c-a232-b5f7cfe0c580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2600799765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.2600799765
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.3895159899
Short name T437
Test name
Test status
Simulation time 818357760 ps
CPU time 6.14 seconds
Started Jun 26 06:19:32 PM PDT 24
Finished Jun 26 06:19:40 PM PDT 24
Peak memory 200012 kb
Host smart-a3803ce6-c3ef-4c8c-9729-dacbe623f360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895159899 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.3895159899
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.2254689046
Short name T246
Test name
Test status
Simulation time 4701731959 ps
CPU time 1325.84 seconds
Started Jun 26 06:19:33 PM PDT 24
Finished Jun 26 06:41:41 PM PDT 24
Peak memory 775820 kb
Host smart-7c7e5301-1c8e-47a4-ab8c-cb34adb93feb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254689046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.2254689046
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.2473819607
Short name T120
Test name
Test status
Simulation time 1702794597 ps
CPU time 23.32 seconds
Started Jun 26 06:19:35 PM PDT 24
Finished Jun 26 06:19:59 PM PDT 24
Peak memory 200012 kb
Host smart-c43dc2ed-25de-42ff-ac3f-268adb771047
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473819607 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.2473819607
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.2413457288
Short name T46
Test name
Test status
Simulation time 23961943073 ps
CPU time 114.26 seconds
Started Jun 26 06:19:33 PM PDT 24
Finished Jun 26 06:21:29 PM PDT 24
Peak memory 216512 kb
Host smart-29009225-8c2f-482d-b96b-24d4ed31460d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413457288 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.2413457288
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.4033720881
Short name T566
Test name
Test status
Simulation time 998071668 ps
CPU time 11.54 seconds
Started Jun 26 06:19:33 PM PDT 24
Finished Jun 26 06:19:45 PM PDT 24
Peak memory 200080 kb
Host smart-968164c8-7c26-4276-adcd-a94b973d4722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033720881 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.4033720881
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac_vectors.4291414323
Short name T570
Test name
Test status
Simulation time 431526926 ps
CPU time 1.39 seconds
Started Jun 26 06:19:35 PM PDT 24
Finished Jun 26 06:19:38 PM PDT 24
Peak memory 199988 kb
Host smart-86c29e1a-456b-47d8-b9a2-4ff435ec1526
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291414323 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac_vectors.4291414323
Directory /workspace/32.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha384_vectors.2846893843
Short name T300
Test name
Test status
Simulation time 59181209217 ps
CPU time 1668.08 seconds
Started Jun 26 06:19:34 PM PDT 24
Finished Jun 26 06:47:24 PM PDT 24
Peak memory 215496 kb
Host smart-193bc523-4cbb-4310-b263-6d7e4b734cee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2846893843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha384_vectors.2846893843
Directory /workspace/32.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha512_vectors.3639515663
Short name T448
Test name
Test status
Simulation time 33078066701 ps
CPU time 1817.21 seconds
Started Jun 26 06:19:32 PM PDT 24
Finished Jun 26 06:49:51 PM PDT 24
Peak memory 215072 kb
Host smart-5ca07468-bdc1-4c64-bca2-99ac09011569
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3639515663 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha512_vectors.3639515663
Directory /workspace/32.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2660419969
Short name T107
Test name
Test status
Simulation time 2483164765 ps
CPU time 38.37 seconds
Started Jun 26 06:19:36 PM PDT 24
Finished Jun 26 06:20:15 PM PDT 24
Peak memory 200116 kb
Host smart-5dad2e60-8661-42c5-9a78-077a4f549131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660419969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2660419969
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.4048210642
Short name T229
Test name
Test status
Simulation time 36383349 ps
CPU time 0.57 seconds
Started Jun 26 06:19:36 PM PDT 24
Finished Jun 26 06:19:37 PM PDT 24
Peak memory 195116 kb
Host smart-732ae3cb-ff2a-488f-99d9-bc3ac2fc15eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048210642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.4048210642
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3742369005
Short name T335
Test name
Test status
Simulation time 2841134402 ps
CPU time 37.07 seconds
Started Jun 26 06:19:35 PM PDT 24
Finished Jun 26 06:20:13 PM PDT 24
Peak memory 200388 kb
Host smart-df59cdbd-3b9d-4c6e-a6a9-143f6fa87926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3742369005 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3742369005
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.182047505
Short name T267
Test name
Test status
Simulation time 2402732635 ps
CPU time 5.21 seconds
Started Jun 26 06:19:32 PM PDT 24
Finished Jun 26 06:19:39 PM PDT 24
Peak memory 200160 kb
Host smart-3a9c428c-96d2-4577-a1a0-966c9ba560db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182047505 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.182047505
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.799741295
Short name T494
Test name
Test status
Simulation time 10587036054 ps
CPU time 786.99 seconds
Started Jun 26 06:19:36 PM PDT 24
Finished Jun 26 06:32:44 PM PDT 24
Peak memory 736656 kb
Host smart-26db691c-8b4f-4243-a3e0-dc4afe704fb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=799741295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.799741295
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1673983367
Short name T112
Test name
Test status
Simulation time 4871991647 ps
CPU time 85.97 seconds
Started Jun 26 06:19:34 PM PDT 24
Finished Jun 26 06:21:02 PM PDT 24
Peak memory 200104 kb
Host smart-07442829-09ec-4265-9694-76b90cd3dcbb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673983367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1673983367
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.1604509634
Short name T500
Test name
Test status
Simulation time 1961802303 ps
CPU time 118.42 seconds
Started Jun 26 06:19:34 PM PDT 24
Finished Jun 26 06:21:34 PM PDT 24
Peak memory 200136 kb
Host smart-6211bf81-697f-4d58-9575-ef50cf2d4756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604509634 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.1604509634
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.1941664655
Short name T313
Test name
Test status
Simulation time 234960735 ps
CPU time 3.58 seconds
Started Jun 26 06:19:36 PM PDT 24
Finished Jun 26 06:19:40 PM PDT 24
Peak memory 200076 kb
Host smart-04b7de42-d7ec-4df4-9857-a22b1f4e7188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941664655 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.1941664655
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.4266229590
Short name T478
Test name
Test status
Simulation time 49504225885 ps
CPU time 805.38 seconds
Started Jun 26 06:19:39 PM PDT 24
Finished Jun 26 06:33:06 PM PDT 24
Peak memory 668908 kb
Host smart-645c94a2-3683-432b-8edc-894352c74b39
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266229590 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.4266229590
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac_vectors.3760226666
Short name T350
Test name
Test status
Simulation time 168844104 ps
CPU time 1.5 seconds
Started Jun 26 06:19:34 PM PDT 24
Finished Jun 26 06:19:37 PM PDT 24
Peak memory 200088 kb
Host smart-f0099dbb-f7ec-4804-8684-6e16d65477e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3760226666 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac_vectors.3760226666
Directory /workspace/33.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha256_vectors.917134880
Short name T328
Test name
Test status
Simulation time 40038032787 ps
CPU time 503.67 seconds
Started Jun 26 06:19:30 PM PDT 24
Finished Jun 26 06:27:55 PM PDT 24
Peak memory 200072 kb
Host smart-4cebae79-c762-4617-8767-0b52088ca341
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=917134880 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha256_vectors.917134880
Directory /workspace/33.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha384_vectors.2497409427
Short name T559
Test name
Test status
Simulation time 88456709541 ps
CPU time 1681.37 seconds
Started Jun 26 06:19:31 PM PDT 24
Finished Jun 26 06:47:34 PM PDT 24
Peak memory 216104 kb
Host smart-e8b2cb37-4f6f-4e00-8a2f-7e532966e62f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2497409427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha384_vectors.2497409427
Directory /workspace/33.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha512_vectors.2207646094
Short name T594
Test name
Test status
Simulation time 65434434090 ps
CPU time 1743.15 seconds
Started Jun 26 06:19:34 PM PDT 24
Finished Jun 26 06:48:39 PM PDT 24
Peak memory 216448 kb
Host smart-a33a1659-5702-4bcc-b380-dd79c8342e0c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2207646094 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha512_vectors.2207646094
Directory /workspace/33.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.3307994125
Short name T649
Test name
Test status
Simulation time 8644428139 ps
CPU time 34.66 seconds
Started Jun 26 06:19:33 PM PDT 24
Finished Jun 26 06:20:10 PM PDT 24
Peak memory 200076 kb
Host smart-8c9463a4-f792-4bf6-adea-ca9256653599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307994125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.3307994125
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.3722703374
Short name T632
Test name
Test status
Simulation time 39795916 ps
CPU time 0.62 seconds
Started Jun 26 06:19:39 PM PDT 24
Finished Jun 26 06:19:41 PM PDT 24
Peak memory 195880 kb
Host smart-cffd77db-4e54-4324-8e2f-ac1e120150d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722703374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.3722703374
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.4249948369
Short name T277
Test name
Test status
Simulation time 314686528 ps
CPU time 15.57 seconds
Started Jun 26 06:19:39 PM PDT 24
Finished Jun 26 06:19:56 PM PDT 24
Peak memory 199988 kb
Host smart-84336ae2-dae3-4f7f-923b-35d51f2ae4e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4249948369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.4249948369
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.3342992035
Short name T653
Test name
Test status
Simulation time 32790770801 ps
CPU time 43.02 seconds
Started Jun 26 06:19:40 PM PDT 24
Finished Jun 26 06:20:25 PM PDT 24
Peak memory 200180 kb
Host smart-27fbea96-6f24-4abd-8827-e3934500b3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342992035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.3342992035
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.1901790412
Short name T175
Test name
Test status
Simulation time 2560134133 ps
CPU time 538.21 seconds
Started Jun 26 06:19:38 PM PDT 24
Finished Jun 26 06:28:37 PM PDT 24
Peak memory 715424 kb
Host smart-e2f5fd7c-f4d5-4e1b-a5f3-48654a570aa8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1901790412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.1901790412
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.3263765795
Short name T123
Test name
Test status
Simulation time 27476667587 ps
CPU time 94.31 seconds
Started Jun 26 06:19:40 PM PDT 24
Finished Jun 26 06:21:16 PM PDT 24
Peak memory 200100 kb
Host smart-165c9885-6a82-4220-9d42-f7649ecfde91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263765795 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.3263765795
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.1117061770
Short name T378
Test name
Test status
Simulation time 18792136964 ps
CPU time 71.6 seconds
Started Jun 26 06:19:41 PM PDT 24
Finished Jun 26 06:20:54 PM PDT 24
Peak memory 200156 kb
Host smart-8445e400-43d6-4fc0-8cff-135a335d3eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117061770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.1117061770
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.66354682
Short name T153
Test name
Test status
Simulation time 423459037 ps
CPU time 8.75 seconds
Started Jun 26 06:19:38 PM PDT 24
Finished Jun 26 06:19:48 PM PDT 24
Peak memory 200104 kb
Host smart-760033ec-647d-428e-b1d4-19c76f4435b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66354682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.66354682
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_test_hmac_vectors.520677955
Short name T190
Test name
Test status
Simulation time 58386368 ps
CPU time 1.14 seconds
Started Jun 26 06:19:37 PM PDT 24
Finished Jun 26 06:19:39 PM PDT 24
Peak memory 199920 kb
Host smart-dedaf4c7-2522-4813-b854-320297b14657
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520677955 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac_vectors.520677955
Directory /workspace/34.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha256_vectors.3123574283
Short name T49
Test name
Test status
Simulation time 8153509423 ps
CPU time 458.14 seconds
Started Jun 26 06:19:42 PM PDT 24
Finished Jun 26 06:27:20 PM PDT 24
Peak memory 200092 kb
Host smart-8866e3e7-74f4-43b7-be8f-f25c9078da20
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3123574283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha256_vectors.3123574283
Directory /workspace/34.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha384_vectors.4140876965
Short name T257
Test name
Test status
Simulation time 130823998312 ps
CPU time 1743.52 seconds
Started Jun 26 06:19:40 PM PDT 24
Finished Jun 26 06:48:45 PM PDT 24
Peak memory 216040 kb
Host smart-c383aabb-bb80-483e-a015-10fa0ec6bc81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4140876965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha384_vectors.4140876965
Directory /workspace/34.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha512_vectors.2827187593
Short name T11
Test name
Test status
Simulation time 291804518275 ps
CPU time 1968.69 seconds
Started Jun 26 06:19:40 PM PDT 24
Finished Jun 26 06:52:30 PM PDT 24
Peak memory 215624 kb
Host smart-484f133c-6d68-47f5-8380-7811c8a3cc30
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2827187593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha512_vectors.2827187593
Directory /workspace/34.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.4144313546
Short name T615
Test name
Test status
Simulation time 41059788169 ps
CPU time 85.23 seconds
Started Jun 26 06:19:39 PM PDT 24
Finished Jun 26 06:21:06 PM PDT 24
Peak memory 200124 kb
Host smart-bc40da54-21de-4f75-bd36-1a22d2f07bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144313546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.4144313546
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.1169379577
Short name T423
Test name
Test status
Simulation time 20830983 ps
CPU time 0.57 seconds
Started Jun 26 06:19:50 PM PDT 24
Finished Jun 26 06:19:52 PM PDT 24
Peak memory 196708 kb
Host smart-4001105c-44da-452e-9b0f-722f8532654d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169379577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.1169379577
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.4126590092
Short name T488
Test name
Test status
Simulation time 957645314 ps
CPU time 45.62 seconds
Started Jun 26 06:19:39 PM PDT 24
Finished Jun 26 06:20:26 PM PDT 24
Peak memory 200060 kb
Host smart-37988137-c954-45ac-82cc-097baf10b36f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126590092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.4126590092
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.1230887602
Short name T518
Test name
Test status
Simulation time 4928216280 ps
CPU time 10.11 seconds
Started Jun 26 06:19:38 PM PDT 24
Finished Jun 26 06:19:50 PM PDT 24
Peak memory 200048 kb
Host smart-67ce7112-cf44-4c04-bbf1-766155e8c42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230887602 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.1230887602
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.1335027742
Short name T429
Test name
Test status
Simulation time 27210988 ps
CPU time 0.81 seconds
Started Jun 26 06:19:38 PM PDT 24
Finished Jun 26 06:19:41 PM PDT 24
Peak memory 198880 kb
Host smart-6cbc1148-65ed-4b6c-88cd-b0ac6b7e83be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1335027742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.1335027742
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1448072798
Short name T31
Test name
Test status
Simulation time 26101318084 ps
CPU time 179.93 seconds
Started Jun 26 06:19:38 PM PDT 24
Finished Jun 26 06:22:39 PM PDT 24
Peak memory 200176 kb
Host smart-0188ec83-d3c2-4d04-bcd6-1a754a02b3d6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448072798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1448072798
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1457120953
Short name T268
Test name
Test status
Simulation time 6253375789 ps
CPU time 96.07 seconds
Started Jun 26 06:19:41 PM PDT 24
Finished Jun 26 06:21:18 PM PDT 24
Peak memory 200136 kb
Host smart-bc01e6b1-40b8-4b87-a5c6-fe1d46597e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457120953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1457120953
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.3627142709
Short name T442
Test name
Test status
Simulation time 222348811 ps
CPU time 4.3 seconds
Started Jun 26 06:19:42 PM PDT 24
Finished Jun 26 06:19:47 PM PDT 24
Peak memory 200048 kb
Host smart-0eb08a85-dbba-4409-8ed1-a671d7ea5840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627142709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.3627142709
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac_vectors.3711498428
Short name T334
Test name
Test status
Simulation time 878077349 ps
CPU time 1.15 seconds
Started Jun 26 06:19:46 PM PDT 24
Finished Jun 26 06:19:48 PM PDT 24
Peak memory 199960 kb
Host smart-431be185-59ef-419b-b2af-5b46074dcfdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711498428 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac_vectors.3711498428
Directory /workspace/35.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha256_vectors.4059327211
Short name T286
Test name
Test status
Simulation time 83320837557 ps
CPU time 566.73 seconds
Started Jun 26 06:19:45 PM PDT 24
Finished Jun 26 06:29:13 PM PDT 24
Peak memory 200108 kb
Host smart-5c1bbd92-fa96-46e0-ad4a-ae52544a68ae
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4059327211 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha256_vectors.4059327211
Directory /workspace/35.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha384_vectors.813012650
Short name T537
Test name
Test status
Simulation time 28093908649 ps
CPU time 1611.7 seconds
Started Jun 26 06:19:47 PM PDT 24
Finished Jun 26 06:46:40 PM PDT 24
Peak memory 215760 kb
Host smart-aa163e2f-11cf-4196-b9c8-75da9afe9fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=813012650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha384_vectors.813012650
Directory /workspace/35.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha512_vectors.2435594080
Short name T536
Test name
Test status
Simulation time 469663678385 ps
CPU time 1802.21 seconds
Started Jun 26 06:19:47 PM PDT 24
Finished Jun 26 06:49:50 PM PDT 24
Peak memory 216012 kb
Host smart-34e88eb3-bde4-47ce-a1d7-b25dfa53a26d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2435594080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha512_vectors.2435594080
Directory /workspace/35.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.2724918008
Short name T581
Test name
Test status
Simulation time 7004934159 ps
CPU time 77.07 seconds
Started Jun 26 06:19:44 PM PDT 24
Finished Jun 26 06:21:02 PM PDT 24
Peak memory 200188 kb
Host smart-0118bf52-26e1-4646-bf03-234cd1997d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724918008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.2724918008
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.3585539906
Short name T312
Test name
Test status
Simulation time 46637913 ps
CPU time 0.58 seconds
Started Jun 26 06:19:46 PM PDT 24
Finished Jun 26 06:19:48 PM PDT 24
Peak memory 195732 kb
Host smart-048b4b58-e667-4e01-9d8f-3094517ffea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585539906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.3585539906
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.517350234
Short name T633
Test name
Test status
Simulation time 528301411 ps
CPU time 25.42 seconds
Started Jun 26 06:19:45 PM PDT 24
Finished Jun 26 06:20:11 PM PDT 24
Peak memory 200092 kb
Host smart-076a80b2-8fe9-4acf-9a19-5d0c66e30c75
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=517350234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.517350234
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.1740668646
Short name T132
Test name
Test status
Simulation time 2802422579 ps
CPU time 40.32 seconds
Started Jun 26 06:19:46 PM PDT 24
Finished Jun 26 06:20:27 PM PDT 24
Peak memory 200140 kb
Host smart-b0688770-4327-4320-9d0d-860789cc5497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740668646 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.1740668646
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.2222691908
Short name T351
Test name
Test status
Simulation time 1418647658 ps
CPU time 135.46 seconds
Started Jun 26 06:19:45 PM PDT 24
Finished Jun 26 06:22:01 PM PDT 24
Peak memory 438584 kb
Host smart-5a2ce6d9-4346-4f43-a738-1c27df3520e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2222691908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.2222691908
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.2282158671
Short name T540
Test name
Test status
Simulation time 611524310 ps
CPU time 32.69 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:20:24 PM PDT 24
Peak memory 199852 kb
Host smart-1ee01f11-87c0-41d1-937e-43ab17ee7dde
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282158671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.2282158671
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.4211876442
Short name T407
Test name
Test status
Simulation time 9647362105 ps
CPU time 53.38 seconds
Started Jun 26 06:19:47 PM PDT 24
Finished Jun 26 06:20:41 PM PDT 24
Peak memory 200112 kb
Host smart-e2793195-fc99-493c-ae28-493a20ddf74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211876442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.4211876442
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.189263210
Short name T418
Test name
Test status
Simulation time 513282295 ps
CPU time 7.5 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:19:59 PM PDT 24
Peak memory 199900 kb
Host smart-9b2bbfdd-acb6-4b68-a773-71e637acbb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189263210 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.189263210
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.58927095
Short name T572
Test name
Test status
Simulation time 2440963470 ps
CPU time 20.37 seconds
Started Jun 26 06:19:47 PM PDT 24
Finished Jun 26 06:20:08 PM PDT 24
Peak memory 200108 kb
Host smart-77822b1d-1903-44bf-ab76-0776e39055ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58927095 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.58927095
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac_vectors.2640621288
Short name T319
Test name
Test status
Simulation time 52994778 ps
CPU time 1.17 seconds
Started Jun 26 06:19:44 PM PDT 24
Finished Jun 26 06:19:46 PM PDT 24
Peak memory 199788 kb
Host smart-35109e9e-a8d8-400a-930b-6c3d51a702ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640621288 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac_vectors.2640621288
Directory /workspace/36.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha256_vectors.4254181125
Short name T457
Test name
Test status
Simulation time 27513675490 ps
CPU time 388.44 seconds
Started Jun 26 06:19:46 PM PDT 24
Finished Jun 26 06:26:15 PM PDT 24
Peak memory 200104 kb
Host smart-aa91b236-8058-4743-a5bb-1d39d17c5d05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4254181125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha256_vectors.4254181125
Directory /workspace/36.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha384_vectors.2667361789
Short name T158
Test name
Test status
Simulation time 137271861585 ps
CPU time 1802.85 seconds
Started Jun 26 06:19:46 PM PDT 24
Finished Jun 26 06:49:50 PM PDT 24
Peak memory 216044 kb
Host smart-e8e0575d-e57b-4cae-9d3c-c08e5d766aba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2667361789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha384_vectors.2667361789
Directory /workspace/36.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha512_vectors.796156746
Short name T479
Test name
Test status
Simulation time 263003044770 ps
CPU time 1912.94 seconds
Started Jun 26 06:19:46 PM PDT 24
Finished Jun 26 06:51:40 PM PDT 24
Peak memory 215520 kb
Host smart-a00ed41d-accf-4253-8115-1b4a96b3ca83
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=796156746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha512_vectors.796156746
Directory /workspace/36.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.1702999874
Short name T110
Test name
Test status
Simulation time 2519693498 ps
CPU time 53.19 seconds
Started Jun 26 06:19:46 PM PDT 24
Finished Jun 26 06:20:40 PM PDT 24
Peak memory 200152 kb
Host smart-af31f484-e068-4478-bd74-ba3a72cc858c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702999874 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.1702999874
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.891967085
Short name T164
Test name
Test status
Simulation time 13868563 ps
CPU time 0.64 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:19:52 PM PDT 24
Peak memory 195928 kb
Host smart-eead3eee-deaf-4f50-a5ef-6de550b66731
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891967085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.891967085
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3800847878
Short name T82
Test name
Test status
Simulation time 623026413 ps
CPU time 30.24 seconds
Started Jun 26 06:19:45 PM PDT 24
Finished Jun 26 06:20:16 PM PDT 24
Peak memory 200072 kb
Host smart-3005fb4c-2cd9-4099-a28a-02aa2059503d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3800847878 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3800847878
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.2072971216
Short name T191
Test name
Test status
Simulation time 2203277005 ps
CPU time 11.46 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:20:04 PM PDT 24
Peak memory 200084 kb
Host smart-3632d39d-21e0-4351-ba17-9420e872cdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072971216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.2072971216
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2772105353
Short name T223
Test name
Test status
Simulation time 8777924623 ps
CPU time 560.5 seconds
Started Jun 26 06:19:44 PM PDT 24
Finished Jun 26 06:29:05 PM PDT 24
Peak memory 675280 kb
Host smart-4e5a5cb3-8557-44d9-91b0-9ed399660aaa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2772105353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2772105353
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2129548257
Short name T470
Test name
Test status
Simulation time 6726699740 ps
CPU time 89.78 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:21:22 PM PDT 24
Peak memory 200104 kb
Host smart-ba8b038d-f128-433b-bf81-1fec5cac7fa5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129548257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2129548257
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.2564172437
Short name T47
Test name
Test status
Simulation time 3663051084 ps
CPU time 19.87 seconds
Started Jun 26 06:19:45 PM PDT 24
Finished Jun 26 06:20:06 PM PDT 24
Peak memory 200188 kb
Host smart-64839bb3-b907-4c38-8745-53611276ed8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564172437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.2564172437
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.1300466700
Short name T564
Test name
Test status
Simulation time 1418000602 ps
CPU time 11.58 seconds
Started Jun 26 06:19:47 PM PDT 24
Finished Jun 26 06:19:59 PM PDT 24
Peak memory 200048 kb
Host smart-0ddd3de3-2f9f-4641-b0f2-ff3342a1c1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300466700 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.1300466700
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac_vectors.113076080
Short name T185
Test name
Test status
Simulation time 229498774 ps
CPU time 1.29 seconds
Started Jun 26 06:19:56 PM PDT 24
Finished Jun 26 06:19:58 PM PDT 24
Peak memory 199864 kb
Host smart-2939cf0d-c098-4d63-9e6e-f79e298942c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113076080 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac_vectors.113076080
Directory /workspace/37.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha256_vectors.3366324057
Short name T323
Test name
Test status
Simulation time 83274465183 ps
CPU time 568.04 seconds
Started Jun 26 06:19:50 PM PDT 24
Finished Jun 26 06:29:19 PM PDT 24
Peak memory 200008 kb
Host smart-acfba8ea-3513-4f9a-b72e-cc948ef905d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3366324057 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha256_vectors.3366324057
Directory /workspace/37.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha384_vectors.2958691338
Short name T401
Test name
Test status
Simulation time 154339217876 ps
CPU time 1997.6 seconds
Started Jun 26 06:19:50 PM PDT 24
Finished Jun 26 06:53:09 PM PDT 24
Peak memory 215388 kb
Host smart-b0b5789c-24d5-4899-84f0-a3fe2110b399
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2958691338 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha384_vectors.2958691338
Directory /workspace/37.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha512_vectors.3356640204
Short name T656
Test name
Test status
Simulation time 26965389188 ps
CPU time 1543.76 seconds
Started Jun 26 06:19:52 PM PDT 24
Finished Jun 26 06:45:37 PM PDT 24
Peak memory 216108 kb
Host smart-889c134a-947a-42c7-8ae6-bfbd39891213
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3356640204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha512_vectors.3356640204
Directory /workspace/37.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2301955440
Short name T167
Test name
Test status
Simulation time 22422024745 ps
CPU time 79.62 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:21:12 PM PDT 24
Peak memory 200168 kb
Host smart-4ece1b12-b041-4f00-b67d-f8395181ed02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301955440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2301955440
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.427671274
Short name T525
Test name
Test status
Simulation time 39396222 ps
CPU time 0.59 seconds
Started Jun 26 06:19:52 PM PDT 24
Finished Jun 26 06:19:54 PM PDT 24
Peak memory 196064 kb
Host smart-f85b0023-72bf-41e2-93cd-f4e5dc35791c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427671274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.427671274
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.185404186
Short name T356
Test name
Test status
Simulation time 1459004999 ps
CPU time 25.22 seconds
Started Jun 26 06:20:54 PM PDT 24
Finished Jun 26 06:21:20 PM PDT 24
Peak memory 200064 kb
Host smart-ade12f91-a180-40cd-b0ad-21498b5e1951
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=185404186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.185404186
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.1888989115
Short name T304
Test name
Test status
Simulation time 431207478 ps
CPU time 6.68 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:19:58 PM PDT 24
Peak memory 200104 kb
Host smart-d59e32ac-4e19-4ebd-87c9-4150d7d2e802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888989115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.1888989115
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3517910241
Short name T367
Test name
Test status
Simulation time 4129840251 ps
CPU time 1072.68 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:37:45 PM PDT 24
Peak memory 692776 kb
Host smart-da78eff5-af96-4f19-a055-bf75f90b9f8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3517910241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3517910241
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3935767756
Short name T555
Test name
Test status
Simulation time 1314987169 ps
CPU time 7.78 seconds
Started Jun 26 06:19:56 PM PDT 24
Finished Jun 26 06:20:05 PM PDT 24
Peak memory 199756 kb
Host smart-9ab98f3c-872e-4509-8446-17e72adc51f7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935767756 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3935767756
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3711674074
Short name T404
Test name
Test status
Simulation time 2777248317 ps
CPU time 124.12 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:21:56 PM PDT 24
Peak memory 200168 kb
Host smart-23e2e0ac-6d93-4237-8ec9-20f8bf1f3d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711674074 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3711674074
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.1991296223
Short name T206
Test name
Test status
Simulation time 35276001 ps
CPU time 1.66 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:19:54 PM PDT 24
Peak memory 200048 kb
Host smart-ec044dfe-86cc-4481-8915-9125295c9df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991296223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.1991296223
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1180271123
Short name T62
Test name
Test status
Simulation time 29968902335 ps
CPU time 1820.27 seconds
Started Jun 26 06:19:50 PM PDT 24
Finished Jun 26 06:50:11 PM PDT 24
Peak memory 734700 kb
Host smart-ab6df2d9-5078-4818-9186-46ee9c91c0be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180271123 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1180271123
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac_vectors.2553688763
Short name T53
Test name
Test status
Simulation time 37789530 ps
CPU time 1.43 seconds
Started Jun 26 06:19:52 PM PDT 24
Finished Jun 26 06:19:55 PM PDT 24
Peak memory 200000 kb
Host smart-24da6419-3bb5-4db1-a428-65b16a984ef2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553688763 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac_vectors.2553688763
Directory /workspace/38.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha256_vectors.2913447448
Short name T505
Test name
Test status
Simulation time 30428251300 ps
CPU time 456.18 seconds
Started Jun 26 06:19:51 PM PDT 24
Finished Jun 26 06:27:29 PM PDT 24
Peak memory 200096 kb
Host smart-f3821360-cc6a-4592-b8d6-ac291e1173ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2913447448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha256_vectors.2913447448
Directory /workspace/38.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha384_vectors.849131610
Short name T192
Test name
Test status
Simulation time 154704585362 ps
CPU time 1771.39 seconds
Started Jun 26 06:19:50 PM PDT 24
Finished Jun 26 06:49:22 PM PDT 24
Peak memory 215540 kb
Host smart-8a1d503a-b5a4-4460-8553-6e8844d3bcc6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=849131610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha384_vectors.849131610
Directory /workspace/38.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha512_vectors.2398116281
Short name T499
Test name
Test status
Simulation time 106847900805 ps
CPU time 1876.5 seconds
Started Jun 26 06:19:56 PM PDT 24
Finished Jun 26 06:51:14 PM PDT 24
Peak memory 215292 kb
Host smart-dfd3db94-58be-438b-8975-7389252d3093
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2398116281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha512_vectors.2398116281
Directory /workspace/38.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.3974150044
Short name T495
Test name
Test status
Simulation time 3592852162 ps
CPU time 24.23 seconds
Started Jun 26 06:19:52 PM PDT 24
Finished Jun 26 06:20:17 PM PDT 24
Peak memory 200132 kb
Host smart-ed1418ce-ad2e-4bd5-98c7-58063864a6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974150044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.3974150044
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.4115653196
Short name T432
Test name
Test status
Simulation time 11627223 ps
CPU time 0.61 seconds
Started Jun 26 06:19:59 PM PDT 24
Finished Jun 26 06:20:02 PM PDT 24
Peak memory 196888 kb
Host smart-24f98525-46c2-4dbe-8fbf-14d9d8574bb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115653196 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.4115653196
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.456950779
Short name T471
Test name
Test status
Simulation time 3978588451 ps
CPU time 46.09 seconds
Started Jun 26 06:19:52 PM PDT 24
Finished Jun 26 06:20:39 PM PDT 24
Peak memory 200116 kb
Host smart-79d1273f-f704-4ad4-a456-31e65d3df775
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456950779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.456950779
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.311273622
Short name T372
Test name
Test status
Simulation time 14190307607 ps
CPU time 47.36 seconds
Started Jun 26 06:19:57 PM PDT 24
Finished Jun 26 06:20:45 PM PDT 24
Peak memory 200148 kb
Host smart-63e94b66-2388-490e-a28d-7b7c6bd29077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311273622 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.311273622
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_datapath_stress.3656957600
Short name T139
Test name
Test status
Simulation time 2311061414 ps
CPU time 654.24 seconds
Started Jun 26 06:19:58 PM PDT 24
Finished Jun 26 06:30:54 PM PDT 24
Peak memory 667284 kb
Host smart-33ab11eb-8ad1-47f4-b090-8f60215e5226
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656957600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.3656957600
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/39.hmac_error.1784540111
Short name T266
Test name
Test status
Simulation time 125982639777 ps
CPU time 154.55 seconds
Started Jun 26 06:19:58 PM PDT 24
Finished Jun 26 06:22:34 PM PDT 24
Peak memory 200080 kb
Host smart-c7e1ad6e-517d-46d7-ab85-7571ed5c28d7
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784540111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.1784540111
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.3958342226
Short name T636
Test name
Test status
Simulation time 2260439121 ps
CPU time 33.96 seconds
Started Jun 26 06:19:55 PM PDT 24
Finished Jun 26 06:20:30 PM PDT 24
Peak memory 200160 kb
Host smart-b3edddb8-7891-463c-a896-accffd6455be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958342226 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.3958342226
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2615484973
Short name T161
Test name
Test status
Simulation time 1185075843 ps
CPU time 10.55 seconds
Started Jun 26 06:19:52 PM PDT 24
Finished Jun 26 06:20:04 PM PDT 24
Peak memory 200260 kb
Host smart-483d6525-2cae-48cf-894b-ea406e035a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615484973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2615484973
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_test_hmac_vectors.1550999837
Short name T349
Test name
Test status
Simulation time 66788440 ps
CPU time 1.02 seconds
Started Jun 26 06:19:58 PM PDT 24
Finished Jun 26 06:20:00 PM PDT 24
Peak memory 199812 kb
Host smart-985e49dd-7be4-44f1-9aca-e56a3e34cc9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550999837 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac_vectors.1550999837
Directory /workspace/39.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha256_vectors.3893984642
Short name T10
Test name
Test status
Simulation time 61339709731 ps
CPU time 440.54 seconds
Started Jun 26 06:20:00 PM PDT 24
Finished Jun 26 06:27:22 PM PDT 24
Peak memory 200088 kb
Host smart-660affdd-89f2-4b3f-8ede-ad9e1ba68cce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3893984642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha256_vectors.3893984642
Directory /workspace/39.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha384_vectors.1848537092
Short name T317
Test name
Test status
Simulation time 738082598504 ps
CPU time 2094 seconds
Started Jun 26 06:19:58 PM PDT 24
Finished Jun 26 06:54:53 PM PDT 24
Peak memory 208408 kb
Host smart-beee437b-d5d9-4e02-9a37-f8b961a1093b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1848537092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha384_vectors.1848537092
Directory /workspace/39.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha512_vectors.2140550947
Short name T413
Test name
Test status
Simulation time 598320445219 ps
CPU time 1984.05 seconds
Started Jun 26 06:19:57 PM PDT 24
Finished Jun 26 06:53:02 PM PDT 24
Peak memory 216020 kb
Host smart-d8b02f88-5068-4ab8-9c19-ea65d095abeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2140550947 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha512_vectors.2140550947
Directory /workspace/39.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.3104978740
Short name T106
Test name
Test status
Simulation time 1380569646 ps
CPU time 68.42 seconds
Started Jun 26 06:19:58 PM PDT 24
Finished Jun 26 06:21:07 PM PDT 24
Peak memory 200012 kb
Host smart-42b1804e-46cf-4d87-b3d0-7eb8b1d3d644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104978740 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.3104978740
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4162999102
Short name T216
Test name
Test status
Simulation time 24232981 ps
CPU time 0.61 seconds
Started Jun 26 06:18:18 PM PDT 24
Finished Jun 26 06:18:20 PM PDT 24
Peak memory 196180 kb
Host smart-00e6c160-5143-4df7-81c7-f3864f9050d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162999102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4162999102
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.3828101617
Short name T331
Test name
Test status
Simulation time 1165540290 ps
CPU time 27.15 seconds
Started Jun 26 06:18:19 PM PDT 24
Finished Jun 26 06:18:47 PM PDT 24
Peak memory 200060 kb
Host smart-f3f93ff9-9f45-4ae7-922b-185bdd2bf18e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3828101617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.3828101617
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2728881637
Short name T458
Test name
Test status
Simulation time 2269398618 ps
CPU time 9.76 seconds
Started Jun 26 06:18:19 PM PDT 24
Finished Jun 26 06:18:30 PM PDT 24
Peak memory 200148 kb
Host smart-d408d322-b220-45db-bdf1-749ae23d71ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728881637 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2728881637
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2306773586
Short name T567
Test name
Test status
Simulation time 1682463816 ps
CPU time 480.77 seconds
Started Jun 26 06:18:20 PM PDT 24
Finished Jun 26 06:26:22 PM PDT 24
Peak memory 670196 kb
Host smart-26b8523c-6a5d-4bca-b4d4-ac3e71105537
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2306773586 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2306773586
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3748364905
Short name T117
Test name
Test status
Simulation time 12204152846 ps
CPU time 174 seconds
Started Jun 26 06:18:16 PM PDT 24
Finished Jun 26 06:21:11 PM PDT 24
Peak memory 200128 kb
Host smart-6a4cc16e-dd94-43d7-8157-36b816ea6354
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748364905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3748364905
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.370846558
Short name T173
Test name
Test status
Simulation time 38279624 ps
CPU time 2.26 seconds
Started Jun 26 06:18:19 PM PDT 24
Finished Jun 26 06:18:22 PM PDT 24
Peak memory 199952 kb
Host smart-f4abc52c-83e3-40a8-9594-0b994796d926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370846558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.370846558
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.238379665
Short name T44
Test name
Test status
Simulation time 144141230 ps
CPU time 1.01 seconds
Started Jun 26 06:18:22 PM PDT 24
Finished Jun 26 06:18:24 PM PDT 24
Peak memory 219236 kb
Host smart-de703d64-1997-48aa-b035-52687b248d93
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238379665 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.238379665
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.4069953893
Short name T359
Test name
Test status
Simulation time 786701605 ps
CPU time 12.92 seconds
Started Jun 26 06:18:19 PM PDT 24
Finished Jun 26 06:18:33 PM PDT 24
Peak memory 199972 kb
Host smart-d40343c9-de19-40fa-8607-856bb919623c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069953893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.4069953893
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_test_hmac_vectors.3983713675
Short name T397
Test name
Test status
Simulation time 60728819 ps
CPU time 1.2 seconds
Started Jun 26 06:18:19 PM PDT 24
Finished Jun 26 06:18:21 PM PDT 24
Peak memory 199980 kb
Host smart-7694735c-f833-4363-9267-d837cda0adee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983713675 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac_vectors.3983713675
Directory /workspace/4.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.3781532722
Short name T492
Test name
Test status
Simulation time 16739402429 ps
CPU time 487.49 seconds
Started Jun 26 06:18:20 PM PDT 24
Finished Jun 26 06:26:29 PM PDT 24
Peak memory 200044 kb
Host smart-5ddb2c2a-4c1a-4255-adc9-3efa0db9ba11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3781532722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.3781532722
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.1358077478
Short name T586
Test name
Test status
Simulation time 28924295451 ps
CPU time 1625.48 seconds
Started Jun 26 06:18:21 PM PDT 24
Finished Jun 26 06:45:28 PM PDT 24
Peak memory 215704 kb
Host smart-31670196-922a-46c4-a580-fc2262779136
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1358077478 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.1358077478
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.2722691837
Short name T640
Test name
Test status
Simulation time 61231671540 ps
CPU time 1716.19 seconds
Started Jun 26 06:18:17 PM PDT 24
Finished Jun 26 06:46:54 PM PDT 24
Peak memory 215456 kb
Host smart-c43a77da-1a90-47ca-be20-a6c8c248bfef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2722691837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.2722691837
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.3338445651
Short name T299
Test name
Test status
Simulation time 606131359 ps
CPU time 4.59 seconds
Started Jun 26 06:18:20 PM PDT 24
Finished Jun 26 06:18:27 PM PDT 24
Peak memory 200060 kb
Host smart-017b800b-4874-450c-9321-1ca917e52e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338445651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.3338445651
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.2884486858
Short name T212
Test name
Test status
Simulation time 23516716 ps
CPU time 0.69 seconds
Started Jun 26 06:20:02 PM PDT 24
Finished Jun 26 06:20:03 PM PDT 24
Peak memory 196864 kb
Host smart-51979953-615d-41a5-a2f8-1134e3ab85bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884486858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.2884486858
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.2486086830
Short name T342
Test name
Test status
Simulation time 5059041898 ps
CPU time 59.96 seconds
Started Jun 26 06:19:59 PM PDT 24
Finished Jun 26 06:21:01 PM PDT 24
Peak memory 216476 kb
Host smart-cea8b051-a713-45e6-9b83-9d66537805ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486086830 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.2486086830
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.4052563715
Short name T561
Test name
Test status
Simulation time 2198533017 ps
CPU time 8.25 seconds
Started Jun 26 06:19:59 PM PDT 24
Finished Jun 26 06:20:09 PM PDT 24
Peak memory 200132 kb
Host smart-d5697f37-bebb-40e0-bed4-17c66a5a83e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052563715 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.4052563715
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.3747473095
Short name T650
Test name
Test status
Simulation time 4028821256 ps
CPU time 1022.6 seconds
Started Jun 26 06:19:57 PM PDT 24
Finished Jun 26 06:37:01 PM PDT 24
Peak memory 756848 kb
Host smart-050d65d2-1897-43ba-bc19-121fb194b9e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747473095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.3747473095
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.2170859359
Short name T658
Test name
Test status
Simulation time 1021162376 ps
CPU time 19.38 seconds
Started Jun 26 06:19:56 PM PDT 24
Finished Jun 26 06:20:17 PM PDT 24
Peak memory 199868 kb
Host smart-53dd4188-206b-4dbf-b54b-6b149b66ec4f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170859359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.2170859359
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.2858595762
Short name T402
Test name
Test status
Simulation time 514483123 ps
CPU time 17.25 seconds
Started Jun 26 06:20:00 PM PDT 24
Finished Jun 26 06:20:19 PM PDT 24
Peak memory 200060 kb
Host smart-dd4b6b8b-8ee0-4ed2-9ea8-b7da48973978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858595762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.2858595762
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.3001461025
Short name T189
Test name
Test status
Simulation time 342773067 ps
CPU time 3.24 seconds
Started Jun 26 06:19:59 PM PDT 24
Finished Jun 26 06:20:04 PM PDT 24
Peak memory 200008 kb
Host smart-dd7fbdea-d4bd-4b32-827b-20d3f41c37f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001461025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.3001461025
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_test_hmac_vectors.748097386
Short name T302
Test name
Test status
Simulation time 116918874 ps
CPU time 1.3 seconds
Started Jun 26 06:19:58 PM PDT 24
Finished Jun 26 06:20:00 PM PDT 24
Peak memory 200052 kb
Host smart-99954f76-197b-45bb-93ec-8e94ab87f20c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748097386 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac_vectors.748097386
Directory /workspace/40.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha256_vectors.1570365158
Short name T369
Test name
Test status
Simulation time 179582063251 ps
CPU time 464.84 seconds
Started Jun 26 06:19:59 PM PDT 24
Finished Jun 26 06:27:46 PM PDT 24
Peak memory 200096 kb
Host smart-36eb84f9-a8d4-42f3-98e9-8cf53943fe36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1570365158 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha256_vectors.1570365158
Directory /workspace/40.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha384_vectors.3833813190
Short name T519
Test name
Test status
Simulation time 161282162517 ps
CPU time 1967.66 seconds
Started Jun 26 06:19:56 PM PDT 24
Finished Jun 26 06:52:45 PM PDT 24
Peak memory 216204 kb
Host smart-dd62ff69-e673-4edb-98c7-c3b425337a5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3833813190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha384_vectors.3833813190
Directory /workspace/40.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha512_vectors.861791452
Short name T2
Test name
Test status
Simulation time 105503333361 ps
CPU time 1912.53 seconds
Started Jun 26 06:19:58 PM PDT 24
Finished Jun 26 06:51:51 PM PDT 24
Peak memory 215164 kb
Host smart-4bec291f-140d-424a-863f-e2895cf07d76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=861791452 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha512_vectors.861791452
Directory /workspace/40.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.30991281
Short name T48
Test name
Test status
Simulation time 7908933001 ps
CPU time 30.06 seconds
Started Jun 26 06:19:58 PM PDT 24
Finished Jun 26 06:20:30 PM PDT 24
Peak memory 200096 kb
Host smart-780459ef-176c-4b3a-9771-48d1c200c637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30991281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.30991281
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.237124004
Short name T197
Test name
Test status
Simulation time 39762261 ps
CPU time 0.6 seconds
Started Jun 26 06:20:09 PM PDT 24
Finished Jun 26 06:20:10 PM PDT 24
Peak memory 195100 kb
Host smart-aedb73eb-2087-472e-a5f1-10f89aa2acc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237124004 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.237124004
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.4078106676
Short name T21
Test name
Test status
Simulation time 142733917 ps
CPU time 2.19 seconds
Started Jun 26 06:20:06 PM PDT 24
Finished Jun 26 06:20:09 PM PDT 24
Peak memory 199988 kb
Host smart-0965bec4-c933-45a4-a111-7bfaf08a793a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4078106676 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.4078106676
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.70926381
Short name T138
Test name
Test status
Simulation time 5118668988 ps
CPU time 19.65 seconds
Started Jun 26 06:20:09 PM PDT 24
Finished Jun 26 06:20:30 PM PDT 24
Peak memory 200056 kb
Host smart-da3a255f-ce6f-4a6e-b306-9ee0f9fc17c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70926381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.70926381
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.458121662
Short name T375
Test name
Test status
Simulation time 662361187 ps
CPU time 188 seconds
Started Jun 26 06:20:11 PM PDT 24
Finished Jun 26 06:23:20 PM PDT 24
Peak memory 629260 kb
Host smart-0374c225-71f5-4528-b988-8e89063c6004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=458121662 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.458121662
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.408504614
Short name T558
Test name
Test status
Simulation time 4093012370 ps
CPU time 97.57 seconds
Started Jun 26 06:20:06 PM PDT 24
Finished Jun 26 06:21:44 PM PDT 24
Peak memory 200160 kb
Host smart-abe92fee-7fc8-4b54-a38b-0933ce498c44
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408504614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.408504614
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.1812380903
Short name T637
Test name
Test status
Simulation time 16569482937 ps
CPU time 84.67 seconds
Started Jun 26 06:19:56 PM PDT 24
Finished Jun 26 06:21:22 PM PDT 24
Peak memory 200112 kb
Host smart-36edbee5-83e6-4bdd-bf8f-edf9e14d38a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812380903 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.1812380903
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.3803603906
Short name T209
Test name
Test status
Simulation time 218103014 ps
CPU time 4.52 seconds
Started Jun 26 06:20:02 PM PDT 24
Finished Jun 26 06:20:07 PM PDT 24
Peak memory 200028 kb
Host smart-b6ac551c-1b47-40bd-90a6-d10e5139b162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803603906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.3803603906
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_test_hmac_vectors.4195823847
Short name T324
Test name
Test status
Simulation time 221173543 ps
CPU time 1.29 seconds
Started Jun 26 06:20:06 PM PDT 24
Finished Jun 26 06:20:08 PM PDT 24
Peak memory 200056 kb
Host smart-803b2326-157f-457d-bfb4-2debabb2dd0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195823847 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac_vectors.4195823847
Directory /workspace/41.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha256_vectors.3532551172
Short name T662
Test name
Test status
Simulation time 30831625786 ps
CPU time 441.59 seconds
Started Jun 26 06:20:04 PM PDT 24
Finished Jun 26 06:27:27 PM PDT 24
Peak memory 200048 kb
Host smart-7db0245c-dc59-4e04-aa62-19bb4a60272d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3532551172 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha256_vectors.3532551172
Directory /workspace/41.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha384_vectors.2196885408
Short name T562
Test name
Test status
Simulation time 177803025815 ps
CPU time 2192.69 seconds
Started Jun 26 06:20:04 PM PDT 24
Finished Jun 26 06:56:38 PM PDT 24
Peak memory 215984 kb
Host smart-fa5b4a72-dc82-4dee-864c-f4b7658765c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2196885408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha384_vectors.2196885408
Directory /workspace/41.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha512_vectors.3482316916
Short name T453
Test name
Test status
Simulation time 855607207546 ps
CPU time 1980.72 seconds
Started Jun 26 06:20:04 PM PDT 24
Finished Jun 26 06:53:06 PM PDT 24
Peak memory 215532 kb
Host smart-22329d2d-28af-4692-bf75-e4d28693e065
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3482316916 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha512_vectors.3482316916
Directory /workspace/41.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2731837261
Short name T440
Test name
Test status
Simulation time 3813277995 ps
CPU time 47.59 seconds
Started Jun 26 06:20:03 PM PDT 24
Finished Jun 26 06:20:51 PM PDT 24
Peak memory 200120 kb
Host smart-0ef482b0-e174-4c89-9c70-aa43fd02c6b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731837261 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2731837261
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.245932765
Short name T552
Test name
Test status
Simulation time 41077014 ps
CPU time 0.63 seconds
Started Jun 26 06:20:12 PM PDT 24
Finished Jun 26 06:20:14 PM PDT 24
Peak memory 196896 kb
Host smart-ce7e295a-5dc9-48ce-91c8-b900c13381d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245932765 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.245932765
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.2201654626
Short name T285
Test name
Test status
Simulation time 273510103 ps
CPU time 10.41 seconds
Started Jun 26 06:20:02 PM PDT 24
Finished Jun 26 06:20:13 PM PDT 24
Peak memory 200028 kb
Host smart-6318293a-e930-4df3-9934-3200b55c3bc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2201654626 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.2201654626
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.2924555865
Short name T614
Test name
Test status
Simulation time 6440968802 ps
CPU time 49.88 seconds
Started Jun 26 06:20:04 PM PDT 24
Finished Jun 26 06:20:55 PM PDT 24
Peak memory 200140 kb
Host smart-3b557cc1-09a9-4024-9322-197e0f5e89da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924555865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.2924555865
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1629325350
Short name T428
Test name
Test status
Simulation time 1814769787 ps
CPU time 481.8 seconds
Started Jun 26 06:20:04 PM PDT 24
Finished Jun 26 06:28:07 PM PDT 24
Peak memory 666136 kb
Host smart-043691d9-0f3b-438a-8816-b666e2f91aae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1629325350 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1629325350
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.484823282
Short name T182
Test name
Test status
Simulation time 1408137902 ps
CPU time 19.74 seconds
Started Jun 26 06:20:10 PM PDT 24
Finished Jun 26 06:20:31 PM PDT 24
Peak memory 200024 kb
Host smart-219cce52-09cf-4453-aeff-f920fae00982
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484823282 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.484823282
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1672335284
Short name T274
Test name
Test status
Simulation time 123568684 ps
CPU time 7.12 seconds
Started Jun 26 06:20:05 PM PDT 24
Finished Jun 26 06:20:13 PM PDT 24
Peak memory 199992 kb
Host smart-1290fb00-36c8-487d-9ee4-8d388c6d0e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672335284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1672335284
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.1551680223
Short name T521
Test name
Test status
Simulation time 1695420111 ps
CPU time 9.13 seconds
Started Jun 26 06:20:03 PM PDT 24
Finished Jun 26 06:20:13 PM PDT 24
Peak memory 200096 kb
Host smart-95b988a8-bb5a-4665-b5fa-a839d0aacf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551680223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.1551680223
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac_vectors.283131707
Short name T346
Test name
Test status
Simulation time 75749050 ps
CPU time 1.45 seconds
Started Jun 26 06:20:11 PM PDT 24
Finished Jun 26 06:20:14 PM PDT 24
Peak memory 199996 kb
Host smart-a54731b9-b1be-47e6-9620-83608fe9b636
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283131707 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac_vectors.283131707
Directory /workspace/42.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha256_vectors.1869498069
Short name T280
Test name
Test status
Simulation time 34544912044 ps
CPU time 469.99 seconds
Started Jun 26 06:20:10 PM PDT 24
Finished Jun 26 06:28:01 PM PDT 24
Peak memory 200068 kb
Host smart-02c252e1-b462-4c1d-8541-90e30597d51c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1869498069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha256_vectors.1869498069
Directory /workspace/42.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha384_vectors.3037854792
Short name T305
Test name
Test status
Simulation time 53833205518 ps
CPU time 1482.82 seconds
Started Jun 26 06:20:05 PM PDT 24
Finished Jun 26 06:44:49 PM PDT 24
Peak memory 215988 kb
Host smart-6fe32057-ec46-4a37-9bc0-27e8a3c7d193
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3037854792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha384_vectors.3037854792
Directory /workspace/42.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha512_vectors.365185465
Short name T544
Test name
Test status
Simulation time 105153067520 ps
CPU time 1903.08 seconds
Started Jun 26 06:20:01 PM PDT 24
Finished Jun 26 06:51:46 PM PDT 24
Peak memory 215580 kb
Host smart-80b00ca2-9cdd-4654-82d2-85f4ad47c41f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=365185465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha512_vectors.365185465
Directory /workspace/42.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.3627891666
Short name T361
Test name
Test status
Simulation time 4327671896 ps
CPU time 61.08 seconds
Started Jun 26 06:20:02 PM PDT 24
Finished Jun 26 06:21:04 PM PDT 24
Peak memory 200144 kb
Host smart-8ef9b48e-0c28-4bd1-97f2-c900c2e4311d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627891666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.3627891666
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.2832351438
Short name T210
Test name
Test status
Simulation time 127574057 ps
CPU time 0.59 seconds
Started Jun 26 06:20:12 PM PDT 24
Finished Jun 26 06:20:15 PM PDT 24
Peak memory 195788 kb
Host smart-9fa0c7b8-a49f-4daa-ad33-4e49a54e115c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832351438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.2832351438
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.3137194423
Short name T156
Test name
Test status
Simulation time 848639857 ps
CPU time 37.46 seconds
Started Jun 26 06:20:15 PM PDT 24
Finished Jun 26 06:20:53 PM PDT 24
Peak memory 200040 kb
Host smart-cc53f727-b205-456d-8bb3-4f5ebd25be45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3137194423 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.3137194423
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.3995477811
Short name T136
Test name
Test status
Simulation time 60572633 ps
CPU time 1.75 seconds
Started Jun 26 06:20:13 PM PDT 24
Finished Jun 26 06:20:17 PM PDT 24
Peak memory 199964 kb
Host smart-7c76dc09-30e7-474e-8d8f-1d848eff14a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995477811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.3995477811
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_error.1616766957
Short name T119
Test name
Test status
Simulation time 35946125090 ps
CPU time 83.83 seconds
Started Jun 26 06:20:18 PM PDT 24
Finished Jun 26 06:21:43 PM PDT 24
Peak memory 199956 kb
Host smart-aea1a64e-4a4a-438b-9673-355b87dc99aa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616766957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.1616766957
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.44509893
Short name T533
Test name
Test status
Simulation time 3861094917 ps
CPU time 72.29 seconds
Started Jun 26 06:20:13 PM PDT 24
Finished Jun 26 06:21:28 PM PDT 24
Peak memory 199912 kb
Host smart-2b8f0e75-35fb-4cd8-88ec-b007dde9fef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44509893 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.44509893
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.3552249037
Short name T262
Test name
Test status
Simulation time 166110896 ps
CPU time 7.47 seconds
Started Jun 26 06:20:14 PM PDT 24
Finished Jun 26 06:20:23 PM PDT 24
Peak memory 200088 kb
Host smart-815488ea-3678-43c1-8bc6-1ac7d3ef457b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552249037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.3552249037
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac_vectors.1150973673
Short name T215
Test name
Test status
Simulation time 30844670 ps
CPU time 1.2 seconds
Started Jun 26 06:20:11 PM PDT 24
Finished Jun 26 06:20:13 PM PDT 24
Peak memory 199944 kb
Host smart-fd0d054c-4417-4cfd-8f31-a6c4dfa2d554
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150973673 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac_vectors.1150973673
Directory /workspace/43.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha256_vectors.656213124
Short name T193
Test name
Test status
Simulation time 36625381768 ps
CPU time 457.67 seconds
Started Jun 26 06:20:11 PM PDT 24
Finished Jun 26 06:27:51 PM PDT 24
Peak memory 200056 kb
Host smart-68e2d0cc-6937-4d5d-98ac-5572dcdc9a06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=656213124 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha256_vectors.656213124
Directory /workspace/43.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha384_vectors.1382547804
Short name T645
Test name
Test status
Simulation time 30643517967 ps
CPU time 1666.34 seconds
Started Jun 26 06:20:12 PM PDT 24
Finished Jun 26 06:48:01 PM PDT 24
Peak memory 216120 kb
Host smart-b7a4024d-ec46-477a-8391-261e30fd3d47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1382547804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha384_vectors.1382547804
Directory /workspace/43.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha512_vectors.2352878129
Short name T512
Test name
Test status
Simulation time 193097066677 ps
CPU time 1676.39 seconds
Started Jun 26 06:20:12 PM PDT 24
Finished Jun 26 06:48:11 PM PDT 24
Peak memory 215676 kb
Host smart-b020cd4d-b1f8-4eca-9952-62504700cf06
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2352878129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha512_vectors.2352878129
Directory /workspace/43.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1490580624
Short name T252
Test name
Test status
Simulation time 1581140317 ps
CPU time 30.47 seconds
Started Jun 26 06:20:13 PM PDT 24
Finished Jun 26 06:20:46 PM PDT 24
Peak memory 200084 kb
Host smart-b3e986da-445a-496c-b558-07573ca62739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490580624 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1490580624
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.1858913449
Short name T482
Test name
Test status
Simulation time 17082297 ps
CPU time 0.57 seconds
Started Jun 26 06:20:11 PM PDT 24
Finished Jun 26 06:20:14 PM PDT 24
Peak memory 195084 kb
Host smart-b0c34148-78a6-4aab-88ec-97d7cefa44b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858913449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.1858913449
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.773353961
Short name T83
Test name
Test status
Simulation time 439183547 ps
CPU time 20.23 seconds
Started Jun 26 06:20:10 PM PDT 24
Finished Jun 26 06:20:32 PM PDT 24
Peak memory 200080 kb
Host smart-79e00ba9-cc62-49a9-a819-e8f224052323
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773353961 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.773353961
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.3111486181
Short name T386
Test name
Test status
Simulation time 2053297292 ps
CPU time 29.37 seconds
Started Jun 26 06:20:13 PM PDT 24
Finished Jun 26 06:20:44 PM PDT 24
Peak memory 200076 kb
Host smart-89471ee9-5b13-4899-8df9-d6df57eb3e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111486181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.3111486181
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.1118735103
Short name T368
Test name
Test status
Simulation time 4818721201 ps
CPU time 1413.49 seconds
Started Jun 26 06:20:12 PM PDT 24
Finished Jun 26 06:43:48 PM PDT 24
Peak memory 812048 kb
Host smart-25a5b558-a9b2-415e-bea9-725275295a79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1118735103 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.1118735103
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_long_msg.2435381422
Short name T13
Test name
Test status
Simulation time 9439206596 ps
CPU time 61.49 seconds
Started Jun 26 06:20:12 PM PDT 24
Finished Jun 26 06:21:16 PM PDT 24
Peak memory 200140 kb
Host smart-5c8a0762-b241-4f91-90ad-a6c508a73697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435381422 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.2435381422
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.3585718583
Short name T513
Test name
Test status
Simulation time 735641923 ps
CPU time 9.57 seconds
Started Jun 26 06:20:13 PM PDT 24
Finished Jun 26 06:20:25 PM PDT 24
Peak memory 199768 kb
Host smart-08e08dd0-3674-49de-91f3-8b3f36544f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585718583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.3585718583
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_test_hmac_vectors.3902816114
Short name T585
Test name
Test status
Simulation time 124004184 ps
CPU time 1.29 seconds
Started Jun 26 06:20:12 PM PDT 24
Finished Jun 26 06:20:16 PM PDT 24
Peak memory 200016 kb
Host smart-b5fca8b4-f373-4e45-b2b7-49cf00ac3ec1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902816114 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac_vectors.3902816114
Directory /workspace/44.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha256_vectors.1209529477
Short name T163
Test name
Test status
Simulation time 35508675684 ps
CPU time 521.49 seconds
Started Jun 26 06:20:12 PM PDT 24
Finished Jun 26 06:28:56 PM PDT 24
Peak memory 200060 kb
Host smart-ec2da41b-503b-4228-9191-32b26df72f89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1209529477 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha256_vectors.1209529477
Directory /workspace/44.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha384_vectors.1354545656
Short name T180
Test name
Test status
Simulation time 102200212687 ps
CPU time 1887.91 seconds
Started Jun 26 06:20:10 PM PDT 24
Finished Jun 26 06:51:39 PM PDT 24
Peak memory 215888 kb
Host smart-fd2b7a5a-28b4-4597-a6a6-24949a12ee7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1354545656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha384_vectors.1354545656
Directory /workspace/44.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha512_vectors.1417389179
Short name T162
Test name
Test status
Simulation time 31387180929 ps
CPU time 1747.96 seconds
Started Jun 26 06:20:12 PM PDT 24
Finished Jun 26 06:49:22 PM PDT 24
Peak memory 215544 kb
Host smart-2f9e49c5-958e-42a6-b7f6-2e6851dfa279
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1417389179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha512_vectors.1417389179
Directory /workspace/44.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.649886922
Short name T172
Test name
Test status
Simulation time 1727700761 ps
CPU time 30.01 seconds
Started Jun 26 06:20:12 PM PDT 24
Finished Jun 26 06:20:45 PM PDT 24
Peak memory 200092 kb
Host smart-11325d8b-5d0e-4bdd-8495-cba84db44236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649886922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.649886922
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.506439328
Short name T419
Test name
Test status
Simulation time 33280841 ps
CPU time 0.59 seconds
Started Jun 26 06:20:17 PM PDT 24
Finished Jun 26 06:20:19 PM PDT 24
Peak memory 196876 kb
Host smart-8f5916a8-47a1-4354-9fce-fbb355648405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506439328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.506439328
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.1088821531
Short name T321
Test name
Test status
Simulation time 231921341 ps
CPU time 9.18 seconds
Started Jun 26 06:20:18 PM PDT 24
Finished Jun 26 06:20:29 PM PDT 24
Peak memory 200048 kb
Host smart-d21923ac-9fdd-43ca-a2c4-8f7d854859b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088821531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.1088821531
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.1991923548
Short name T377
Test name
Test status
Simulation time 2836341507 ps
CPU time 10.6 seconds
Started Jun 26 06:20:16 PM PDT 24
Finished Jun 26 06:20:27 PM PDT 24
Peak memory 200136 kb
Host smart-b5657703-72b0-4e71-aca1-cc8666432cf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1991923548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.1991923548
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2869963913
Short name T28
Test name
Test status
Simulation time 20549415482 ps
CPU time 451.1 seconds
Started Jun 26 06:20:17 PM PDT 24
Finished Jun 26 06:27:50 PM PDT 24
Peak memory 612740 kb
Host smart-39f2a139-06fa-4dc4-b93e-73c70560f1ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2869963913 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2869963913
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.60919900
Short name T226
Test name
Test status
Simulation time 12694336915 ps
CPU time 109.14 seconds
Started Jun 26 06:20:17 PM PDT 24
Finished Jun 26 06:22:07 PM PDT 24
Peak memory 200108 kb
Host smart-8ff41381-028c-43c9-9946-962e1e332473
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60919900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.60919900
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.1267546387
Short name T617
Test name
Test status
Simulation time 11264646170 ps
CPU time 150.23 seconds
Started Jun 26 06:20:11 PM PDT 24
Finished Jun 26 06:22:44 PM PDT 24
Peak memory 200252 kb
Host smart-43e67aa9-7582-41de-9542-6a8bbcfa7739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267546387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.1267546387
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.1561674066
Short name T543
Test name
Test status
Simulation time 1653475942 ps
CPU time 10.34 seconds
Started Jun 26 06:20:13 PM PDT 24
Finished Jun 26 06:20:25 PM PDT 24
Peak memory 200224 kb
Host smart-58871391-0846-46a6-987e-938f56d24164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561674066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.1561674066
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_test_hmac_vectors.1654115336
Short name T365
Test name
Test status
Simulation time 56439205 ps
CPU time 1.12 seconds
Started Jun 26 06:20:17 PM PDT 24
Finished Jun 26 06:20:20 PM PDT 24
Peak memory 199988 kb
Host smart-c825b4d9-cd8e-493c-81aa-f3ead2d7fafe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654115336 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac_vectors.1654115336
Directory /workspace/45.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha256_vectors.647681082
Short name T196
Test name
Test status
Simulation time 27622105977 ps
CPU time 406.79 seconds
Started Jun 26 06:20:18 PM PDT 24
Finished Jun 26 06:27:06 PM PDT 24
Peak memory 200312 kb
Host smart-a5251ba0-099f-4635-a5d3-9222f0d44e77
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=647681082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha256_vectors.647681082
Directory /workspace/45.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha384_vectors.691021680
Short name T563
Test name
Test status
Simulation time 140017787815 ps
CPU time 1940.22 seconds
Started Jun 26 06:20:18 PM PDT 24
Finished Jun 26 06:52:40 PM PDT 24
Peak memory 215848 kb
Host smart-18f1727c-c93f-41fa-9973-e00ec4d6e682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=691021680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha384_vectors.691021680
Directory /workspace/45.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha512_vectors.1487113270
Short name T230
Test name
Test status
Simulation time 140098417601 ps
CPU time 1744.17 seconds
Started Jun 26 06:20:17 PM PDT 24
Finished Jun 26 06:49:23 PM PDT 24
Peak memory 216492 kb
Host smart-3812e75b-0a9a-435f-81e0-ae39d24f5e03
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1487113270 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha512_vectors.1487113270
Directory /workspace/45.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.548039267
Short name T416
Test name
Test status
Simulation time 71132888 ps
CPU time 0.7 seconds
Started Jun 26 06:20:20 PM PDT 24
Finished Jun 26 06:20:21 PM PDT 24
Peak memory 196716 kb
Host smart-5724909b-2d71-4de2-9d8e-bfe03f1272f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548039267 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.548039267
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.1559992199
Short name T8
Test name
Test status
Simulation time 43296969 ps
CPU time 0.59 seconds
Started Jun 26 06:20:21 PM PDT 24
Finished Jun 26 06:20:23 PM PDT 24
Peak memory 195744 kb
Host smart-67a99480-7cee-4043-85b6-c366fb999c44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559992199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.1559992199
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1239178848
Short name T534
Test name
Test status
Simulation time 99747203 ps
CPU time 5.18 seconds
Started Jun 26 06:20:19 PM PDT 24
Finished Jun 26 06:20:25 PM PDT 24
Peak memory 200028 kb
Host smart-7bc564c5-8f8b-4693-8dfe-445c3cb1bd7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1239178848 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1239178848
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1313262806
Short name T663
Test name
Test status
Simulation time 2860610945 ps
CPU time 354.06 seconds
Started Jun 26 06:20:18 PM PDT 24
Finished Jun 26 06:26:13 PM PDT 24
Peak memory 622264 kb
Host smart-ef1be61b-022a-429f-8730-e12c81be1c7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313262806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1313262806
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2892061858
Short name T388
Test name
Test status
Simulation time 1110100773 ps
CPU time 14.49 seconds
Started Jun 26 06:20:16 PM PDT 24
Finished Jun 26 06:20:32 PM PDT 24
Peak memory 200068 kb
Host smart-62587699-aa9f-4323-af98-5e5e4c1b9043
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892061858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2892061858
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.1308513898
Short name T338
Test name
Test status
Simulation time 573679936 ps
CPU time 32.54 seconds
Started Jun 26 06:20:17 PM PDT 24
Finished Jun 26 06:20:51 PM PDT 24
Peak memory 200052 kb
Host smart-27cf8602-3d37-4203-96bd-2ae02c92e844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308513898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.1308513898
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.290680806
Short name T203
Test name
Test status
Simulation time 25285099 ps
CPU time 0.96 seconds
Started Jun 26 06:20:16 PM PDT 24
Finished Jun 26 06:20:18 PM PDT 24
Peak memory 199164 kb
Host smart-85a26fe8-e1dc-419d-8d70-e3c9161cdef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290680806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.290680806
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_test_hmac_vectors.1722813619
Short name T621
Test name
Test status
Simulation time 28734534 ps
CPU time 1.1 seconds
Started Jun 26 06:20:18 PM PDT 24
Finished Jun 26 06:20:21 PM PDT 24
Peak memory 199920 kb
Host smart-617413b9-80f9-4666-becb-cfb5e1513a50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722813619 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac_vectors.1722813619
Directory /workspace/46.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha256_vectors.969134959
Short name T45
Test name
Test status
Simulation time 81752481061 ps
CPU time 506.07 seconds
Started Jun 26 06:20:21 PM PDT 24
Finished Jun 26 06:28:48 PM PDT 24
Peak memory 200072 kb
Host smart-0f697fad-c28b-4d68-aab7-d2af44ee8a4a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=969134959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha256_vectors.969134959
Directory /workspace/46.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha384_vectors.1736024666
Short name T473
Test name
Test status
Simulation time 173286346159 ps
CPU time 2292.73 seconds
Started Jun 26 06:20:18 PM PDT 24
Finished Jun 26 06:58:33 PM PDT 24
Peak memory 215776 kb
Host smart-3b24e49a-81bf-4cb6-834c-74c27647dd10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1736024666 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha384_vectors.1736024666
Directory /workspace/46.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha512_vectors.4124252797
Short name T623
Test name
Test status
Simulation time 422324970262 ps
CPU time 1805.38 seconds
Started Jun 26 06:20:19 PM PDT 24
Finished Jun 26 06:50:26 PM PDT 24
Peak memory 215960 kb
Host smart-2361d1c6-ca0f-4e00-93d5-e49bd07b079f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4124252797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha512_vectors.4124252797
Directory /workspace/46.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1846769326
Short name T547
Test name
Test status
Simulation time 3417219779 ps
CPU time 32.87 seconds
Started Jun 26 06:20:17 PM PDT 24
Finished Jun 26 06:20:51 PM PDT 24
Peak memory 200120 kb
Host smart-75eb6396-b71b-4e22-af83-9fd7e7f75e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846769326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1846769326
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1705041421
Short name T353
Test name
Test status
Simulation time 15383768 ps
CPU time 0.61 seconds
Started Jun 26 06:20:26 PM PDT 24
Finished Jun 26 06:20:28 PM PDT 24
Peak memory 196060 kb
Host smart-9852d952-04d1-43af-8c95-5475a50b324b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705041421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1705041421
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.1230288691
Short name T403
Test name
Test status
Simulation time 809626642 ps
CPU time 37.21 seconds
Started Jun 26 06:20:18 PM PDT 24
Finished Jun 26 06:20:57 PM PDT 24
Peak memory 200072 kb
Host smart-371d3218-0278-4d33-8b60-6b16b420dd17
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1230288691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.1230288691
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.1253568218
Short name T135
Test name
Test status
Simulation time 3167548991 ps
CPU time 50.05 seconds
Started Jun 26 06:20:20 PM PDT 24
Finished Jun 26 06:21:11 PM PDT 24
Peak memory 200100 kb
Host smart-644d36f0-fdf2-4d1c-bbc1-f870d67b7dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253568218 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.1253568218
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.132812227
Short name T475
Test name
Test status
Simulation time 1770538358 ps
CPU time 463.48 seconds
Started Jun 26 06:20:21 PM PDT 24
Finished Jun 26 06:28:05 PM PDT 24
Peak memory 623332 kb
Host smart-57d91e6e-15d0-45e6-881e-128998da437d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=132812227 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.132812227
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.3345115234
Short name T583
Test name
Test status
Simulation time 29559247097 ps
CPU time 86.22 seconds
Started Jun 26 06:20:20 PM PDT 24
Finished Jun 26 06:21:47 PM PDT 24
Peak memory 200008 kb
Host smart-d79795a2-8f72-4c8c-b4c3-32a5d7c814db
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345115234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.3345115234
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.2412651395
Short name T256
Test name
Test status
Simulation time 4305349795 ps
CPU time 19.98 seconds
Started Jun 26 06:20:21 PM PDT 24
Finished Jun 26 06:20:41 PM PDT 24
Peak memory 200040 kb
Host smart-d0c2351f-14c9-49b6-8d09-09c035cd87ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412651395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.2412651395
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2970983682
Short name T221
Test name
Test status
Simulation time 2735756002 ps
CPU time 15.51 seconds
Started Jun 26 06:20:21 PM PDT 24
Finished Jun 26 06:20:37 PM PDT 24
Peak memory 200164 kb
Host smart-50cc7564-6928-43fa-9693-d23322800332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970983682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2970983682
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_test_hmac_vectors.4121900636
Short name T344
Test name
Test status
Simulation time 51797874 ps
CPU time 1.05 seconds
Started Jun 26 06:20:26 PM PDT 24
Finished Jun 26 06:20:29 PM PDT 24
Peak memory 199848 kb
Host smart-948430d1-7b7d-4944-8709-6f520b093982
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121900636 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac_vectors.4121900636
Directory /workspace/47.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha256_vectors.4248010194
Short name T160
Test name
Test status
Simulation time 42786886435 ps
CPU time 486.98 seconds
Started Jun 26 06:20:26 PM PDT 24
Finished Jun 26 06:28:34 PM PDT 24
Peak memory 200072 kb
Host smart-55b5f23f-9605-4716-9c10-42dda833b410
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4248010194 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha256_vectors.4248010194
Directory /workspace/47.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha384_vectors.1424534125
Short name T467
Test name
Test status
Simulation time 46596195851 ps
CPU time 1754.53 seconds
Started Jun 26 06:20:24 PM PDT 24
Finished Jun 26 06:49:40 PM PDT 24
Peak memory 216048 kb
Host smart-77f9ba6b-59ee-4864-b2d0-dae2c402efe0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1424534125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha384_vectors.1424534125
Directory /workspace/47.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha512_vectors.641901090
Short name T301
Test name
Test status
Simulation time 168625105500 ps
CPU time 2132.55 seconds
Started Jun 26 06:20:26 PM PDT 24
Finished Jun 26 06:56:00 PM PDT 24
Peak memory 215744 kb
Host smart-d6b72646-9dcc-4743-941b-12c226700fb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=641901090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha512_vectors.641901090
Directory /workspace/47.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1183134710
Short name T394
Test name
Test status
Simulation time 1317164383 ps
CPU time 19.85 seconds
Started Jun 26 06:20:24 PM PDT 24
Finished Jun 26 06:20:45 PM PDT 24
Peak memory 200204 kb
Host smart-b3e3c720-257c-43b6-810e-5af1fc376949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183134710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1183134710
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.1423528734
Short name T514
Test name
Test status
Simulation time 14863236 ps
CPU time 0.56 seconds
Started Jun 26 06:20:32 PM PDT 24
Finished Jun 26 06:20:33 PM PDT 24
Peak memory 195760 kb
Host smart-422ae451-ff59-473e-a9f4-19f8fe3b4387
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423528734 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.1423528734
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.2751489017
Short name T435
Test name
Test status
Simulation time 1823738974 ps
CPU time 22.8 seconds
Started Jun 26 06:20:25 PM PDT 24
Finished Jun 26 06:20:50 PM PDT 24
Peak memory 200080 kb
Host smart-3e19f022-e650-4d70-acdf-65d837edd753
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2751489017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.2751489017
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.2669291272
Short name T308
Test name
Test status
Simulation time 100853054 ps
CPU time 5.6 seconds
Started Jun 26 06:20:26 PM PDT 24
Finished Jun 26 06:20:33 PM PDT 24
Peak memory 199964 kb
Host smart-11148f00-6e4d-4204-b0a5-f46cde1e0cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669291272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.2669291272
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.285250204
Short name T395
Test name
Test status
Simulation time 185061845 ps
CPU time 29.46 seconds
Started Jun 26 06:20:24 PM PDT 24
Finished Jun 26 06:20:55 PM PDT 24
Peak memory 307824 kb
Host smart-148159e1-28ef-489a-a90e-a6619c0bfa04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=285250204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.285250204
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.3739638719
Short name T484
Test name
Test status
Simulation time 17539695136 ps
CPU time 116.34 seconds
Started Jun 26 06:20:27 PM PDT 24
Finished Jun 26 06:22:24 PM PDT 24
Peak memory 200096 kb
Host smart-4059e935-7a4a-4126-886a-a44df0d9ead5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739638719 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.3739638719
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.3888234025
Short name T501
Test name
Test status
Simulation time 969440653 ps
CPU time 29.23 seconds
Started Jun 26 06:20:24 PM PDT 24
Finished Jun 26 06:20:54 PM PDT 24
Peak memory 200092 kb
Host smart-e6cd8ef3-8794-4b91-88d2-430e4d9c5323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888234025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.3888234025
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3180544703
Short name T239
Test name
Test status
Simulation time 341075182 ps
CPU time 9.61 seconds
Started Jun 26 06:20:26 PM PDT 24
Finished Jun 26 06:20:37 PM PDT 24
Peak memory 200060 kb
Host smart-74e9e360-776b-4076-baad-87f1c7e37e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180544703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3180544703
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_test_hmac_vectors.3325019290
Short name T374
Test name
Test status
Simulation time 235960340 ps
CPU time 1.45 seconds
Started Jun 26 06:20:30 PM PDT 24
Finished Jun 26 06:20:33 PM PDT 24
Peak memory 200016 kb
Host smart-6a538dcd-15ac-4987-99b5-5a359ee38355
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325019290 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac_vectors.3325019290
Directory /workspace/48.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha256_vectors.3167807792
Short name T573
Test name
Test status
Simulation time 34689364013 ps
CPU time 457.07 seconds
Started Jun 26 06:20:25 PM PDT 24
Finished Jun 26 06:28:04 PM PDT 24
Peak memory 200048 kb
Host smart-96af8af8-a231-458e-9bb0-bf4e7130b1ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3167807792 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha256_vectors.3167807792
Directory /workspace/48.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha384_vectors.196993069
Short name T638
Test name
Test status
Simulation time 65465205489 ps
CPU time 1758.76 seconds
Started Jun 26 06:20:26 PM PDT 24
Finished Jun 26 06:49:46 PM PDT 24
Peak memory 200076 kb
Host smart-6a4f465a-7b8f-4f45-9926-54e70ac97f6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=196993069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha384_vectors.196993069
Directory /workspace/48.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha512_vectors.2113072525
Short name T597
Test name
Test status
Simulation time 94443693795 ps
CPU time 1675.36 seconds
Started Jun 26 06:20:26 PM PDT 24
Finished Jun 26 06:48:23 PM PDT 24
Peak memory 215952 kb
Host smart-2a8ebc19-18fc-45de-944b-d3cba42df750
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2113072525 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha512_vectors.2113072525
Directory /workspace/48.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.1613675257
Short name T539
Test name
Test status
Simulation time 6037018073 ps
CPU time 80.96 seconds
Started Jun 26 06:20:25 PM PDT 24
Finished Jun 26 06:21:48 PM PDT 24
Peak memory 200104 kb
Host smart-39b44a52-f68d-45cb-b591-52d8156ef389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613675257 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.1613675257
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2998201801
Short name T287
Test name
Test status
Simulation time 39612341 ps
CPU time 0.59 seconds
Started Jun 26 06:20:35 PM PDT 24
Finished Jun 26 06:20:36 PM PDT 24
Peak memory 196220 kb
Host smart-ff038dfd-8570-42a3-b964-ae94e7728fec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998201801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2998201801
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.357772146
Short name T398
Test name
Test status
Simulation time 408368330 ps
CPU time 8.51 seconds
Started Jun 26 06:20:29 PM PDT 24
Finished Jun 26 06:20:39 PM PDT 24
Peak memory 200048 kb
Host smart-008bab22-3c65-4bc6-ae4d-457524e88d2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=357772146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.357772146
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.1534545516
Short name T14
Test name
Test status
Simulation time 957077392 ps
CPU time 47.81 seconds
Started Jun 26 06:20:32 PM PDT 24
Finished Jun 26 06:21:21 PM PDT 24
Peak memory 200076 kb
Host smart-25537d46-8a5c-45b3-9a3f-b63e5c4958a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534545516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.1534545516
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.2090178774
Short name T389
Test name
Test status
Simulation time 1618814302 ps
CPU time 412.06 seconds
Started Jun 26 06:20:33 PM PDT 24
Finished Jun 26 06:27:26 PM PDT 24
Peak memory 673396 kb
Host smart-3a73a9ad-483f-424d-9a7f-97e85ebd87d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090178774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.2090178774
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.1692532651
Short name T32
Test name
Test status
Simulation time 4757530155 ps
CPU time 72.31 seconds
Started Jun 26 06:20:30 PM PDT 24
Finished Jun 26 06:21:43 PM PDT 24
Peak memory 199996 kb
Host smart-bfba1aef-1e37-4b77-ba6c-5497086a5d87
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692532651 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.1692532651
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_smoke.1003756220
Short name T584
Test name
Test status
Simulation time 916251243 ps
CPU time 6.1 seconds
Started Jun 26 06:20:36 PM PDT 24
Finished Jun 26 06:20:42 PM PDT 24
Peak memory 200268 kb
Host smart-41a49f6b-685e-484b-b694-c79528349a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003756220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.1003756220
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac_vectors.735709639
Short name T490
Test name
Test status
Simulation time 45631804 ps
CPU time 1.31 seconds
Started Jun 26 06:20:33 PM PDT 24
Finished Jun 26 06:20:35 PM PDT 24
Peak memory 199968 kb
Host smart-9f2e41c1-76dd-4870-9e24-41c795f009e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735709639 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac_vectors.735709639
Directory /workspace/49.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha256_vectors.1099842219
Short name T168
Test name
Test status
Simulation time 56210671025 ps
CPU time 490.32 seconds
Started Jun 26 06:20:32 PM PDT 24
Finished Jun 26 06:28:43 PM PDT 24
Peak memory 200040 kb
Host smart-a02bb7bc-3ddb-4a96-a942-ca73da14c037
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1099842219 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha256_vectors.1099842219
Directory /workspace/49.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha384_vectors.2230230326
Short name T184
Test name
Test status
Simulation time 116795873591 ps
CPU time 2084.38 seconds
Started Jun 26 06:20:36 PM PDT 24
Finished Jun 26 06:55:22 PM PDT 24
Peak memory 215436 kb
Host smart-8b6923df-777b-4f69-b7e4-7d888377e683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2230230326 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha384_vectors.2230230326
Directory /workspace/49.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha512_vectors.3312718440
Short name T550
Test name
Test status
Simulation time 113765414934 ps
CPU time 2037.07 seconds
Started Jun 26 06:20:30 PM PDT 24
Finished Jun 26 06:54:28 PM PDT 24
Peak memory 216480 kb
Host smart-a985215b-be52-4d18-b207-3ff625f91a58
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3312718440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha512_vectors.3312718440
Directory /workspace/49.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3826450825
Short name T51
Test name
Test status
Simulation time 916477820 ps
CPU time 26.68 seconds
Started Jun 26 06:20:36 PM PDT 24
Finished Jun 26 06:21:04 PM PDT 24
Peak memory 200068 kb
Host smart-77d36cf6-c067-4e88-94c6-df64672e7cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826450825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3826450825
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.1415358528
Short name T468
Test name
Test status
Simulation time 13537296 ps
CPU time 0.58 seconds
Started Jun 26 06:18:30 PM PDT 24
Finished Jun 26 06:18:32 PM PDT 24
Peak memory 196848 kb
Host smart-1fba2aeb-a5ca-434d-a33e-20470de4130c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415358528 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.1415358528
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.613930229
Short name T24
Test name
Test status
Simulation time 1173474758 ps
CPU time 27.05 seconds
Started Jun 26 06:18:18 PM PDT 24
Finished Jun 26 06:18:46 PM PDT 24
Peak memory 200000 kb
Host smart-6df5ab59-0a38-4563-bab8-c7e1d0e27d81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=613930229 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.613930229
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.1004969329
Short name T352
Test name
Test status
Simulation time 1744365053 ps
CPU time 24.59 seconds
Started Jun 26 06:18:20 PM PDT 24
Finished Jun 26 06:18:46 PM PDT 24
Peak memory 200056 kb
Host smart-47b8bee4-027c-41d6-a382-092d888fea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004969329 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.1004969329
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.2493371461
Short name T436
Test name
Test status
Simulation time 950477167 ps
CPU time 99 seconds
Started Jun 26 06:18:19 PM PDT 24
Finished Jun 26 06:20:00 PM PDT 24
Peak memory 555500 kb
Host smart-f0ee2747-95c0-419b-9689-091fb1ef5166
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2493371461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.2493371461
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.369998353
Short name T648
Test name
Test status
Simulation time 13675107819 ps
CPU time 92.2 seconds
Started Jun 26 06:18:21 PM PDT 24
Finished Jun 26 06:19:54 PM PDT 24
Peak memory 200056 kb
Host smart-2db9827a-a522-4950-b1e4-6f90fe308483
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369998353 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.369998353
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3864394824
Short name T330
Test name
Test status
Simulation time 24602477561 ps
CPU time 137.86 seconds
Started Jun 26 06:18:20 PM PDT 24
Finished Jun 26 06:20:40 PM PDT 24
Peak memory 200088 kb
Host smart-c6ef7d38-9460-4078-ae83-d1b61636488b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864394824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3864394824
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.565033868
Short name T288
Test name
Test status
Simulation time 545896210 ps
CPU time 7.84 seconds
Started Jun 26 06:18:22 PM PDT 24
Finished Jun 26 06:18:31 PM PDT 24
Peak memory 200072 kb
Host smart-51539150-f116-47f3-8ee9-06caa95ccb36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565033868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.565033868
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1647714192
Short name T595
Test name
Test status
Simulation time 4632846463 ps
CPU time 119.33 seconds
Started Jun 26 06:18:26 PM PDT 24
Finished Jun 26 06:20:28 PM PDT 24
Peak memory 216500 kb
Host smart-c0a43a25-1328-4b41-9a2a-73acc4848816
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647714192 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1647714192
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac_vectors.1471173981
Short name T169
Test name
Test status
Simulation time 83786329 ps
CPU time 1.1 seconds
Started Jun 26 06:18:24 PM PDT 24
Finished Jun 26 06:18:27 PM PDT 24
Peak memory 199976 kb
Host smart-cfdba604-78a3-425c-8247-dc22c2badeeb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471173981 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac_vectors.1471173981
Directory /workspace/5.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha256_vectors.3040953025
Short name T379
Test name
Test status
Simulation time 167118538456 ps
CPU time 556.89 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:27:44 PM PDT 24
Peak memory 200072 kb
Host smart-77a26c35-1031-4034-8415-51899cb2cda2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3040953025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha256_vectors.3040953025
Directory /workspace/5.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha384_vectors.1420004805
Short name T599
Test name
Test status
Simulation time 102442722110 ps
CPU time 1892.6 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:50:01 PM PDT 24
Peak memory 215536 kb
Host smart-71f57e7c-990e-4ee4-8364-0c85b01e5b6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1420004805 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha384_vectors.1420004805
Directory /workspace/5.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha512_vectors.213390369
Short name T449
Test name
Test status
Simulation time 279012152973 ps
CPU time 1926.84 seconds
Started Jun 26 06:18:24 PM PDT 24
Finished Jun 26 06:50:32 PM PDT 24
Peak memory 216192 kb
Host smart-0fecd2c6-6f61-4def-8383-121da9801456
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=213390369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha512_vectors.213390369
Directory /workspace/5.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.2076061400
Short name T283
Test name
Test status
Simulation time 9499687600 ps
CPU time 46.83 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:19:13 PM PDT 24
Peak memory 200132 kb
Host smart-e51e76e1-b324-4882-9dd8-f9d1b2da48d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076061400 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.2076061400
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.3541908023
Short name T326
Test name
Test status
Simulation time 38646099 ps
CPU time 0.63 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:18:28 PM PDT 24
Peak memory 196840 kb
Host smart-6688c742-35bd-48b2-8e7e-df53c53bac1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541908023 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.3541908023
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.412271558
Short name T155
Test name
Test status
Simulation time 1205028480 ps
CPU time 43.5 seconds
Started Jun 26 06:18:23 PM PDT 24
Finished Jun 26 06:19:08 PM PDT 24
Peak memory 200064 kb
Host smart-738282a6-5674-4d15-b77c-d02d1b808a5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=412271558 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.412271558
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.3311291206
Short name T129
Test name
Test status
Simulation time 3989913254 ps
CPU time 55.5 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:19:23 PM PDT 24
Peak memory 200044 kb
Host smart-97e84df6-8eba-425e-a044-07cc5020f789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311291206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.3311291206
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.2644530501
Short name T531
Test name
Test status
Simulation time 2505756276 ps
CPU time 301.29 seconds
Started Jun 26 06:18:24 PM PDT 24
Finished Jun 26 06:23:26 PM PDT 24
Peak memory 641204 kb
Host smart-349eaaa6-5350-4321-9447-8a82ff02eac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2644530501 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.2644530501
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.3536189090
Short name T3
Test name
Test status
Simulation time 4031025270 ps
CPU time 6.31 seconds
Started Jun 26 06:18:30 PM PDT 24
Finished Jun 26 06:18:38 PM PDT 24
Peak memory 200068 kb
Host smart-ecae57ab-1b67-49e1-b4d2-c118d72e42e3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536189090 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.3536189090
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3125171369
Short name T497
Test name
Test status
Simulation time 24657764103 ps
CPU time 109.24 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:20:16 PM PDT 24
Peak memory 200328 kb
Host smart-93224c38-45ef-41fa-9c3c-1782f8aedd0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125171369 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3125171369
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.561399018
Short name T524
Test name
Test status
Simulation time 3035030851 ps
CPU time 12.58 seconds
Started Jun 26 06:18:30 PM PDT 24
Finished Jun 26 06:18:44 PM PDT 24
Peak memory 200140 kb
Host smart-4597679a-e911-4bf5-8d47-34c2efcd690f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561399018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.561399018
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_test_hmac_vectors.618408841
Short name T380
Test name
Test status
Simulation time 58643002 ps
CPU time 1.35 seconds
Started Jun 26 06:18:24 PM PDT 24
Finished Jun 26 06:18:27 PM PDT 24
Peak memory 199980 kb
Host smart-4c7c6c68-ff1b-4b03-bbe8-3b4856fd029a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618408841 -assert nopostpr
oc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac_vectors.618408841
Directory /workspace/6.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha256_vectors.2480549565
Short name T362
Test name
Test status
Simulation time 177289345812 ps
CPU time 543.51 seconds
Started Jun 26 06:18:26 PM PDT 24
Finished Jun 26 06:27:32 PM PDT 24
Peak memory 200112 kb
Host smart-fe6caa67-dee3-446b-b3fe-abe8acf02065
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2480549565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha256_vectors.2480549565
Directory /workspace/6.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha384_vectors.3782688686
Short name T548
Test name
Test status
Simulation time 324101587659 ps
CPU time 2079.38 seconds
Started Jun 26 06:18:24 PM PDT 24
Finished Jun 26 06:53:05 PM PDT 24
Peak memory 216200 kb
Host smart-209f0fec-cc03-4dbc-b0da-81e5f5aeecfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3782688686 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha384_vectors.3782688686
Directory /workspace/6.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha512_vectors.2612428779
Short name T560
Test name
Test status
Simulation time 368578035899 ps
CPU time 1664.01 seconds
Started Jun 26 06:18:24 PM PDT 24
Finished Jun 26 06:46:10 PM PDT 24
Peak memory 216296 kb
Host smart-f821c103-12b2-4cc7-804d-c7fa728b6958
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2612428779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha512_vectors.2612428779
Directory /workspace/6.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.752914418
Short name T18
Test name
Test status
Simulation time 1564087653 ps
CPU time 67.13 seconds
Started Jun 26 06:18:25 PM PDT 24
Finished Jun 26 06:19:35 PM PDT 24
Peak memory 200016 kb
Host smart-94013799-696e-423a-8c04-325fa2b57acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752914418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.752914418
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.4082663944
Short name T275
Test name
Test status
Simulation time 13507279 ps
CPU time 0.6 seconds
Started Jun 26 06:18:33 PM PDT 24
Finished Jun 26 06:18:35 PM PDT 24
Peak memory 196868 kb
Host smart-ac47d5f3-cfb0-4bea-b66f-e27a46397813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082663944 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.4082663944
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1450376214
Short name T298
Test name
Test status
Simulation time 249486549 ps
CPU time 4.81 seconds
Started Jun 26 06:18:27 PM PDT 24
Finished Jun 26 06:18:34 PM PDT 24
Peak memory 200032 kb
Host smart-dcb0c8f4-6883-41e9-951d-4c29260f7fb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1450376214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1450376214
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.1793848076
Short name T420
Test name
Test status
Simulation time 14442777728 ps
CPU time 60.78 seconds
Started Jun 26 06:18:31 PM PDT 24
Finished Jun 26 06:19:33 PM PDT 24
Peak memory 208316 kb
Host smart-98e08e2c-1d54-4f6f-b619-7972f14b86c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793848076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.1793848076
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.1611105262
Short name T261
Test name
Test status
Simulation time 1930676198 ps
CPU time 502.87 seconds
Started Jun 26 06:18:22 PM PDT 24
Finished Jun 26 06:26:47 PM PDT 24
Peak memory 677496 kb
Host smart-8310f63f-30cc-4775-93e8-c694cd161df0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611105262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.1611105262
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.3025695307
Short name T393
Test name
Test status
Simulation time 2640162340 ps
CPU time 47.41 seconds
Started Jun 26 06:18:34 PM PDT 24
Finished Jun 26 06:19:23 PM PDT 24
Peak memory 200100 kb
Host smart-2f7dc60f-1cc5-48be-a90e-8f1d595ef9e8
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025695307 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.3025695307
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.3618448931
Short name T439
Test name
Test status
Simulation time 27662390161 ps
CPU time 94.07 seconds
Started Jun 26 06:18:23 PM PDT 24
Finished Jun 26 06:19:58 PM PDT 24
Peak memory 200168 kb
Host smart-95972f0e-29fd-4d0d-97ef-a1589d5d99f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618448931 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.3618448931
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3631404292
Short name T427
Test name
Test status
Simulation time 162006170 ps
CPU time 2.66 seconds
Started Jun 26 06:18:23 PM PDT 24
Finished Jun 26 06:18:27 PM PDT 24
Peak memory 200048 kb
Host smart-7abc1af4-0657-44a4-bd24-643e0756764b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631404292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3631404292
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_test_hmac_vectors.2171949321
Short name T606
Test name
Test status
Simulation time 79165839 ps
CPU time 1.44 seconds
Started Jun 26 06:18:32 PM PDT 24
Finished Jun 26 06:18:35 PM PDT 24
Peak memory 200040 kb
Host smart-163b6bed-2678-4185-8ac8-32fb8d961353
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171949321 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac_vectors.2171949321
Directory /workspace/7.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha256_vectors.3991481461
Short name T211
Test name
Test status
Simulation time 16773202149 ps
CPU time 472.11 seconds
Started Jun 26 06:18:30 PM PDT 24
Finished Jun 26 06:26:24 PM PDT 24
Peak memory 200004 kb
Host smart-0450cbbb-93db-4c1d-90ab-7d57de777eb7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3991481461 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha256_vectors.3991481461
Directory /workspace/7.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha384_vectors.3048300529
Short name T508
Test name
Test status
Simulation time 196942856209 ps
CPU time 1777.06 seconds
Started Jun 26 06:18:32 PM PDT 24
Finished Jun 26 06:48:11 PM PDT 24
Peak memory 215788 kb
Host smart-d8c8e75c-a98a-42a4-ad1a-3156f092b740
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3048300529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha384_vectors.3048300529
Directory /workspace/7.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha512_vectors.668232563
Short name T415
Test name
Test status
Simulation time 400871223793 ps
CPU time 1786.6 seconds
Started Jun 26 06:18:30 PM PDT 24
Finished Jun 26 06:48:19 PM PDT 24
Peak memory 215920 kb
Host smart-6261552e-1f8c-422d-9a39-60675eb2095a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=668232563 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha512_vectors.668232563
Directory /workspace/7.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.1189008296
Short name T624
Test name
Test status
Simulation time 20900916868 ps
CPU time 75.97 seconds
Started Jun 26 06:18:31 PM PDT 24
Finished Jun 26 06:19:48 PM PDT 24
Peak memory 200096 kb
Host smart-da30f909-78d7-40f7-afa8-6c5c5ae55552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189008296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.1189008296
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2277723414
Short name T258
Test name
Test status
Simulation time 26912250 ps
CPU time 0.61 seconds
Started Jun 26 06:18:38 PM PDT 24
Finished Jun 26 06:18:41 PM PDT 24
Peak memory 196080 kb
Host smart-7ccbeec3-8ec0-4b3d-bdc3-0e93fc71653a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277723414 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2277723414
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.2358636819
Short name T79
Test name
Test status
Simulation time 692319108 ps
CPU time 9.55 seconds
Started Jun 26 06:18:28 PM PDT 24
Finished Jun 26 06:18:39 PM PDT 24
Peak memory 199968 kb
Host smart-ca8c9057-8e8f-49a3-8992-5ea46b33f84c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358636819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.2358636819
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.1401169087
Short name T461
Test name
Test status
Simulation time 248435325 ps
CPU time 13.48 seconds
Started Jun 26 06:18:30 PM PDT 24
Finished Jun 26 06:18:45 PM PDT 24
Peak memory 199916 kb
Host smart-d76299bf-a1ba-4899-84f4-ee291536f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401169087 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.1401169087
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.975197438
Short name T294
Test name
Test status
Simulation time 3087600315 ps
CPU time 71.26 seconds
Started Jun 26 06:18:32 PM PDT 24
Finished Jun 26 06:19:45 PM PDT 24
Peak memory 345540 kb
Host smart-0f8d791e-7530-434f-be04-801a3f677971
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=975197438 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.975197438
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.3454228061
Short name T445
Test name
Test status
Simulation time 1012195779 ps
CPU time 57.99 seconds
Started Jun 26 06:18:34 PM PDT 24
Finished Jun 26 06:19:33 PM PDT 24
Peak memory 199992 kb
Host smart-fb799cfc-1c00-4ef0-820c-f4ae824b08da
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454228061 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.3454228061
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1911475575
Short name T35
Test name
Test status
Simulation time 3938474350 ps
CPU time 78.41 seconds
Started Jun 26 06:18:30 PM PDT 24
Finished Jun 26 06:19:50 PM PDT 24
Peak memory 200376 kb
Host smart-968c02c1-a427-4853-825c-56a91cf4e9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911475575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1911475575
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.2485864831
Short name T187
Test name
Test status
Simulation time 746469080 ps
CPU time 8.77 seconds
Started Jun 26 06:18:34 PM PDT 24
Finished Jun 26 06:18:44 PM PDT 24
Peak memory 200092 kb
Host smart-dbce6ce2-d3b7-48a6-aa23-e8d3e3563fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485864831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.2485864831
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_test_hmac_vectors.3941312047
Short name T502
Test name
Test status
Simulation time 47369837 ps
CPU time 1.14 seconds
Started Jun 26 06:18:30 PM PDT 24
Finished Jun 26 06:18:33 PM PDT 24
Peak memory 199884 kb
Host smart-4570d73a-ef9d-4593-b52a-d542759c9a0d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941312047 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac_vectors.3941312047
Directory /workspace/8.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha256_vectors.3400318323
Short name T383
Test name
Test status
Simulation time 103973446796 ps
CPU time 455.87 seconds
Started Jun 26 06:18:30 PM PDT 24
Finished Jun 26 06:26:08 PM PDT 24
Peak memory 200044 kb
Host smart-6f928d82-483e-405f-b3cd-7f242a162b0f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3400318323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha256_vectors.3400318323
Directory /workspace/8.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha384_vectors.3827829328
Short name T207
Test name
Test status
Simulation time 472904114029 ps
CPU time 1542.38 seconds
Started Jun 26 06:18:31 PM PDT 24
Finished Jun 26 06:44:15 PM PDT 24
Peak memory 216172 kb
Host smart-372f544a-38a5-4955-a3f8-27cef038cfc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3827829328 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha384_vectors.3827829328
Directory /workspace/8.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha512_vectors.1915099058
Short name T243
Test name
Test status
Simulation time 666269537967 ps
CPU time 2051.26 seconds
Started Jun 26 06:18:35 PM PDT 24
Finished Jun 26 06:52:47 PM PDT 24
Peak memory 216460 kb
Host smart-f8aea979-8a74-4308-aa3c-9398c4b52a64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1915099058 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha512_vectors.1915099058
Directory /workspace/8.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.274881134
Short name T406
Test name
Test status
Simulation time 3277961607 ps
CPU time 43.5 seconds
Started Jun 26 06:18:31 PM PDT 24
Finished Jun 26 06:19:16 PM PDT 24
Peak memory 200132 kb
Host smart-cc98caf9-5af2-4d2a-ac0a-74b9227e33f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274881134 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.274881134
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.1744868653
Short name T253
Test name
Test status
Simulation time 11313705 ps
CPU time 0.59 seconds
Started Jun 26 06:18:36 PM PDT 24
Finished Jun 26 06:18:37 PM PDT 24
Peak memory 195736 kb
Host smart-ecf79eb6-7f27-49c7-93f6-b61a650e7248
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744868653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.1744868653
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.88611760
Short name T25
Test name
Test status
Simulation time 1212621651 ps
CPU time 44.28 seconds
Started Jun 26 06:18:39 PM PDT 24
Finished Jun 26 06:19:25 PM PDT 24
Peak memory 200056 kb
Host smart-acbc6e6a-0306-4426-a5a8-d6e474cfc60f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=88611760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.88611760
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.4264995133
Short name T660
Test name
Test status
Simulation time 14866102171 ps
CPU time 864.75 seconds
Started Jun 26 06:18:37 PM PDT 24
Finished Jun 26 06:33:03 PM PDT 24
Peak memory 726516 kb
Host smart-790010db-04e9-4b08-835d-02bedb918f5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4264995133 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.4264995133
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2519481266
Short name T553
Test name
Test status
Simulation time 9099230143 ps
CPU time 176.36 seconds
Started Jun 26 06:18:41 PM PDT 24
Finished Jun 26 06:21:39 PM PDT 24
Peak memory 200124 kb
Host smart-af2e135e-71fe-4772-abc4-e6a4be89c254
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519481266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2519481266
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.237533059
Short name T127
Test name
Test status
Simulation time 67728737069 ps
CPU time 141.99 seconds
Started Jun 26 06:18:38 PM PDT 24
Finished Jun 26 06:21:02 PM PDT 24
Peak memory 200156 kb
Host smart-e9beb297-f29e-46aa-8afd-2c29dd735804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237533059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.237533059
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.1627930565
Short name T481
Test name
Test status
Simulation time 216088645 ps
CPU time 9.31 seconds
Started Jun 26 06:18:37 PM PDT 24
Finished Jun 26 06:18:47 PM PDT 24
Peak memory 200060 kb
Host smart-3b3b67cb-97fa-4ee3-8495-c5bb4a2e501c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627930565 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.1627930565
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_test_hmac_vectors.3034616849
Short name T281
Test name
Test status
Simulation time 230730620 ps
CPU time 1.4 seconds
Started Jun 26 06:18:38 PM PDT 24
Finished Jun 26 06:18:42 PM PDT 24
Peak memory 200036 kb
Host smart-a6977f8a-0148-4f79-8a72-0c8775925a54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034616849 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac_vectors.3034616849
Directory /workspace/9.hmac_test_hmac_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha256_vectors.1835630424
Short name T421
Test name
Test status
Simulation time 108410757940 ps
CPU time 469.36 seconds
Started Jun 26 06:18:38 PM PDT 24
Finished Jun 26 06:26:29 PM PDT 24
Peak memory 200092 kb
Host smart-4c95e9a5-7a83-4b02-aa66-038fcbc3eda9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1835630424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha256_vectors.1835630424
Directory /workspace/9.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha384_vectors.795566733
Short name T186
Test name
Test status
Simulation time 220688276008 ps
CPU time 1989.92 seconds
Started Jun 26 06:18:37 PM PDT 24
Finished Jun 26 06:51:48 PM PDT 24
Peak memory 216504 kb
Host smart-5b650260-cbdd-45e9-bba5-09a7f708beef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=795566733 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha384_vectors.795566733
Directory /workspace/9.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.2698570115
Short name T462
Test name
Test status
Simulation time 14978113341 ps
CPU time 75.98 seconds
Started Jun 26 06:18:38 PM PDT 24
Finished Jun 26 06:19:56 PM PDT 24
Peak memory 200148 kb
Host smart-c492fa85-1456-4d5c-a93a-1b248ce7e399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698570115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.2698570115
Directory /workspace/9.hmac_wipe_secret/latest
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