Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

124206171

1

T1

736183

T2

25222

T3

55652

full_word

128657488

1

T1

774560

T2

21451

T3

51469

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	252863259	1			T1	151074		T2	46673		T3	107121
auto[TlIntgErrCmd]	121	1			T54	6		T55	8		T56	2
auto[TlIntgErrData]	143	1			T54	3		T55	8		T56	8
auto[TlIntgErrBoth]	136	1			T54	11		T55	4		T56	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

101864104

1

T1

613799

T2

18952

T3

51734

auto[1]

150999555

1

T1

896944

T2

27721

T3

55387

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	51354024	1			T1	307158		T2	9570		T3	25874
auto[TlIntgErrNone]	partial	auto[1]	72851775	1			T1	429025		T2	15652		T3	29778
auto[TlIntgErrNone]	full_word	auto[0]	50509908	1			T1	306641		T2	9382		T3	25860
auto[TlIntgErrNone]	full_word	auto[1]	78147552	1			T1	467919		T2	12069		T3	25609
auto[TlIntgErrCmd]	partial	auto[0]	43	1			T54	2		T55	3		T56	1
auto[TlIntgErrCmd]	partial	auto[1]	69	1			T54	2		T55	4		T56	1
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T54	1		T138	1		T143	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T54	1		T55	1		T139	2
auto[TlIntgErrData]	partial	auto[0]	64	1			T54	2		T55	2		T56	1
auto[TlIntgErrData]	partial	auto[1]	67	1			T54	1		T55	6		T56	6
auto[TlIntgErrData]	full_word	auto[0]	8	1			T61	1		T143	1		T144	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T56	1		T61	1		T143	1
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T54	4		T55	1		T56	4
auto[TlIntgErrBoth]	partial	auto[1]	79	1			T54	6		T55	3		T56	6
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T60	1		T145	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T54	1		T143	1		T141	1