Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.42	100.00	93.75	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1466723471	797284	0	0
intr_enable_rd_A	1466723471	2554	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466723471	797284	0	0
T17	913617	33433	0	0
T42	0	267479	0	0
T43	0	16	0	0
T53	0	883	0	0
T54	0	5	0	0
T55	0	4	0	0
T57	0	1192	0	0
T58	0	399	0	0
T62	0	841	0	0
T63	0	7	0	0
T64	133891	0	0	0
T65	80082	0	0	0
T66	288325	0	0	0
T67	759349	0	0	0
T68	40776	0	0	0
T69	746120	0	0	0
T70	294030	0	0	0
T71	180712	0	0	0
T72	306165	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1466723471	2554	0	0
T12	59654	0	0	0
T13	180269	0	0	0
T19	802985	24	0	0
T33	884054	0	0	0
T34	117813	0	0	0
T35	595074	0	0	0
T71	0	43	0	0
T73	0	28	0	0
T74	0	62	0	0
T75	0	37	0	0
T76	0	34	0	0
T77	0	37	0	0
T78	0	5	0	0
T79	0	6	0	0
T80	0	17	0	0
T81	787304	0	0	0
T82	152209	0	0	0
T83	332759	0	0	0
T84	5868	0	0	0