Module Definition
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Module Instance : tb.dut.u_tlul_adapter.u_rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
89.64 92.86 80.00 85.71 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.74 87.18 66.67 61.11 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.69 98.57 95.56 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.15 84.00 60.00 45.45



Module Instance : tb.dut.u_tlul_adapter.u_sramreqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.93 92.31 71.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
78.08 86.84 62.96 62.50 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.69 98.57 95.56 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 63.15 84.00 60.00 45.45



Module Instance : tb.dut.u_msg_fifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.42 100.00 93.75 100.00 100.00 96.77 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_tlul_adapter.u_reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
91.36 95.00 87.10 83.33 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.69 98.57 95.56 100.00 84.62 u_tlul_adapter


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 81.58 92.00 80.00 72.73



Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 fifo_h


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_msg_fifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
90.93 92.31
tb.dut.u_tlul_adapter.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL151280.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
89.64 92.86
tb.dut.u_tlul_adapter.u_rspfifo

Line No.TotalCoveredPercent
TOTAL151386.67
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS1112150.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 0 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
90.93 71.43
tb.dut.u_tlul_adapter.u_sramreqfifo

TotalCoveredPercent
Conditions16531.25
Logical16531.25
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_msg_fifo

TotalCoveredPercent
Conditions242083.33
Logical242083.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT9,T5,T12
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT9,T12,T18
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
89.64 80.00
tb.dut.u_tlul_adapter.u_rspfifo

TotalCoveredPercent
Conditions24833.33
Logical24833.33
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110Not Covered
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=36,Pass=1,Depth=32,OutputZeroIfEmpty=1,Secure=0,DepthW=6,gen_normal_fifo.PtrW=5 + Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_msg_fifo

SCOREBRANCH
89.64 85.71
tb.dut.u_tlul_adapter.u_rspfifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.u_tlul_adapter.u_reqfifo

SCOREBRANCH
90.93 100.00
tb.dut.u_tlul_adapter.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 1631565513 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2147483647 190329913 0 0
gen_passthru_fifo.paramCheckPass 4890 4890 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1631565513 0 0
T1 1272288 2428316 0 0
T2 2636816 231376 0 0
T3 6022320 457848 0 0
T6 21936 2129 0 0
T7 2310304 300962 0 0
T8 2236288 1792607 0 0
T9 146440 48750 0 0
T10 2300520 2049884 0 0
T11 15360 312 0 0
T15 94224 19560 0 0
T16 0 353568 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1590360 1590350 0 0
T2 3296020 3295200 0 0
T3 7527900 7526950 0 0
T6 27420 26640 0 0
T7 2887880 2887160 0 0
T8 2795360 2795300 0 0
T9 183050 182340 0 0
T10 2875650 2875560 0 0
T11 19200 18420 0 0
T15 117780 117100 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1590360 1590350 0 0
T2 3296020 3295200 0 0
T3 7527900 7526950 0 0
T6 27420 26640 0 0
T7 2887880 2887160 0 0
T8 2795360 2795300 0 0
T9 183050 182340 0 0
T10 2875650 2875560 0 0
T11 19200 18420 0 0
T15 117780 117100 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 1590360 1590350 0 0
T2 3296020 3295200 0 0
T3 7527900 7526950 0 0
T6 27420 26640 0 0
T7 2887880 2887160 0 0
T8 2795360 2795300 0 0
T9 183050 182340 0 0
T10 2875650 2875560 0 0
T11 19200 18420 0 0
T15 117780 117100 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 190329913 0 0
T1 318072 501176 0 0
T2 659204 44684 0 0
T3 1505580 29364 0 0
T6 5484 785 0 0
T7 577576 46602 0 0
T8 559072 205739 0 0
T9 36610 17310 0 0
T10 575130 952308 0 0
T11 3840 0 0 0
T15 23556 2540 0 0
T16 0 205306 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 4890 4890 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T6 6 6 0 0
T7 6 6 0 0
T8 6 6 0 0
T9 6 6 0 0
T10 6 6 0 0
T11 6 6 0 0
T15 6 6 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Line No.TotalCoveredPercent
TOTAL141392.86
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN108100.00
ALWAYS11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 0 1
111 1 1
112 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
TotalCoveredPercent
Conditions10880.00
Logical10880.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTestsExclude Annotation
0CoveredT1,T2,T3
1Excluded VC_COV_UNR

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10CoveredT1,T2,T3
11Excluded VC_COV_UNR

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTestsExclude Annotation
01Excluded VC_COV_UNR
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
Line No.TotalCoveredPercent
Branches 7 6 85.71
TERNARY 130 1 1 100.00
TERNARY 138 1 1 100.00
IF 69 3 3 100.00
IF 123 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded VC_COV_UNR


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Not Covered
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncompleteExclusionExclude Annotation
DataKnown_A Excluded [UNSUPPORTED] excluded by fpv
DepthKnown_A 1442533375 1442461276 0 0
RvalidKnown_A 1442533375 1442461276 0 0
WreadyKnown_A 1442533375 1442461276 0 0
gen_normal_fifo.depthShallNotExceedParamDepth Excluded [UNSUPPORTED] excluded by fpv


DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Line No.TotalCoveredPercent
TOTAL131292.31
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10800
ALWAYS11111100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN133100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 excluded
Exclude Annotation: [UNR] Pass is always '1'
111 1 1
112 excluded
Exclude Annotation: VC_COV_UNR
MISSING_ELSE
116 1 1
133 0 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
TotalCoveredPercent
Conditions7571.43
Logical7571.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11Excluded VC_COV_UNR

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111Excluded VC_COV_UNR

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
Line No.TotalCoveredPercent
Branches 5 5 100.00
TERNARY 138 1 1 100.00
IF 69 3 3 100.00
IF 111 1 1 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTestsExclude Annotation
1 Covered T1,T2,T3
0 Excluded VC_COV_UNR


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTestsExclude Annotation
1 Excluded VC_COV_UNR
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_sramreqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncompleteExclusionExclude Annotation
DataKnown_A Excluded [UNSUPPORTED] excluded by fpv
DepthKnown_A 1442533375 1442461276 0 0
RvalidKnown_A 1442533375 1442461276 0 0
WreadyKnown_A 1442533375 1442461276 0 0
gen_normal_fifo.depthShallNotExceedParamDepth Excluded [UNSUPPORTED] excluded by fpv


DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

Line Coverage for Instance : tb.dut.u_msg_fifo
Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
130 1 1
131 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_msg_fifo
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT9,T5,T12
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101CoveredT9,T12,T18
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (36'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_msg_fifo
Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 123 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_msg_fifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1442533375 91137597 0 0
DepthKnown_A 1442533375 1442461276 0 0
RvalidKnown_A 1442533375 1442461276 0 0
WreadyKnown_A 1442533375 1442461276 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1442533375 91137597 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 91137597 0 0
T1 159036 368701 0 0
T2 329602 26884 0 0
T3 752790 5682 0 0
T6 2742 733 0 0
T7 288788 10676 0 0
T8 279536 131327 0 0
T9 18305 12520 0 0
T10 287565 657368 0 0
T11 1920 0 0 0
T15 11778 1752 0 0
T16 0 131175 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 91137597 0 0
T1 159036 368701 0 0
T2 329602 26884 0 0
T3 752790 5682 0 0
T6 2742 733 0 0
T7 288788 10676 0 0
T8 279536 131327 0 0
T9 18305 12520 0 0
T10 287565 657368 0 0
T11 1920 0 0 0
T15 11778 1752 0 0
T16 0 131175 0 0

Line Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1


Cond Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
TotalCoveredPercent
Conditions1111100.00
Logical1111100.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTestsExclude Annotation
01CoveredT1,T2,T3
10Excluded VC_COV_UNR
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011CoveredT1,T2,T3
101Excluded VC_COV_UNR
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTestsExclude Annotation
011Excluded VC_COV_UNR
101CoveredT1,T2,T3
110Excluded VC_COV_UNR
111CoveredT1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 138 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 69 if ((!rst_ni)) -2-: 71 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 111 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_adapter.u_reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1442533375 99192316 0 0
DepthKnown_A 1442533375 1442461276 0 0
RvalidKnown_A 1442533375 1442461276 0 0
WreadyKnown_A 1442533375 1442461276 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 1442533375 99192316 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 99192316 0 0
T1 159036 132475 0 0
T2 329602 17800 0 0
T3 752790 23682 0 0
T6 2742 52 0 0
T7 288788 35926 0 0
T8 279536 74412 0 0
T9 18305 4790 0 0
T10 287565 294940 0 0
T11 1920 0 0 0
T15 11778 788 0 0
T16 0 74131 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 1442461276 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 1442533375 99192316 0 0
T1 159036 132475 0 0
T2 329602 17800 0 0
T3 752790 23682 0 0
T6 2742 52 0 0
T7 288788 35926 0 0
T8 279536 74412 0 0
T9 18305 4790 0 0
T10 287565 294940 0 0
T11 1920 0 0 0
T15 11778 788 0 0
T16 0 74131 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1466723471 255979454 0 0
DepthKnown_A 1466723471 1466606711 0 0
RvalidKnown_A 1466723471 1466606711 0 0
WreadyKnown_A 1466723471 1466606711 0 0
gen_passthru_fifo.paramCheckPass 815 815 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 255979454 0 0
T1 159036 151074 0 0
T2 329602 46673 0 0
T3 752790 107121 0 0
T6 2742 336 0 0
T7 288788 31122 0 0
T8 279536 396717 0 0
T9 18305 10413 0 0
T10 287565 141671 0 0
T11 1920 78 0 0
T15 11778 4255 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 815 815 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1466723471 465025278 0 0
DepthKnown_A 1466723471 1466606711 0 0
RvalidKnown_A 1466723471 1466606711 0 0
WreadyKnown_A 1466723471 1466606711 0 0
gen_passthru_fifo.paramCheckPass 815 815 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 465025278 0 0
T1 159036 679998 0 0
T2 329602 46673 0 0
T3 752790 107121 0 0
T6 2742 336 0 0
T7 288788 96058 0 0
T8 279536 396717 0 0
T9 18305 5307 0 0
T10 287565 141671 0 0
T11 1920 78 0 0
T15 11778 4255 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 815 815 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1466723471 57352909 0 0
DepthKnown_A 1466723471 1466606711 0 0
RvalidKnown_A 1466723471 1466606711 0 0
WreadyKnown_A 1466723471 1466606711 0 0
gen_passthru_fifo.paramCheckPass 815 815 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 57352909 0 0
T1 159036 294440 0 0
T2 329602 17800 0 0
T3 752790 23682 0 0
T6 2742 52 0 0
T7 288788 11696 0 0
T8 279536 74412 0 0
T9 18305 9896 0 0
T10 287565 294940 0 0
T11 1920 0 0 0
T15 11778 788 0 0
T16 0 74131 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 815 815 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1466723471 100594633 0 0
DepthKnown_A 1466723471 1466606711 0 0
RvalidKnown_A 1466723471 1466606711 0 0
WreadyKnown_A 1466723471 1466606711 0 0
gen_passthru_fifo.paramCheckPass 815 815 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 100594633 0 0
T1 159036 132475 0 0
T2 329602 17800 0 0
T3 752790 23682 0 0
T6 2742 52 0 0
T7 288788 35926 0 0
T8 279536 74412 0 0
T9 18305 4790 0 0
T10 287565 294940 0 0
T11 1920 0 0 0
T15 11778 788 0 0
T16 0 74131 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 815 815 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1466723471 197852681 0 0
DepthKnown_A 1466723471 1466606711 0 0
RvalidKnown_A 1466723471 1466606711 0 0
WreadyKnown_A 1466723471 1466606711 0 0
gen_passthru_fifo.paramCheckPass 815 815 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 197852681 0 0
T1 159036 121630 0 0
T2 329602 28873 0 0
T3 752790 83439 0 0
T6 2742 284 0 0
T7 288788 19426 0 0
T8 279536 322305 0 0
T9 18305 517 0 0
T10 287565 112177 0 0
T11 1920 78 0 0
T15 11778 3467 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 815 815 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 1466723471 364430645 0 0
DepthKnown_A 1466723471 1466606711 0 0
RvalidKnown_A 1466723471 1466606711 0 0
WreadyKnown_A 1466723471 1466606711 0 0
gen_passthru_fifo.paramCheckPass 815 815 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 364430645 0 0
T1 159036 547523 0 0
T2 329602 28873 0 0
T3 752790 83439 0 0
T6 2742 284 0 0
T7 288788 60132 0 0
T8 279536 322305 0 0
T9 18305 517 0 0
T10 287565 112177 0 0
T11 1920 78 0 0
T15 11778 3467 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1466723471 1466606711 0 0
T1 159036 159035 0 0
T2 329602 329520 0 0
T3 752790 752695 0 0
T6 2742 2664 0 0
T7 288788 288716 0 0
T8 279536 279530 0 0
T9 18305 18234 0 0
T10 287565 287556 0 0
T11 1920 1842 0 0
T15 11778 11710 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 815 815 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0
T11 1 1 0 0
T15 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%