Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	51049945	1			T1	579		T2	33330		T3	21975
all_values[1]	51049945	1			T1	579		T2	33330		T3	21975
all_values[2]	51049945	1			T1	579		T2	33330		T3	21975

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

100731

1

T1

2

T3

395

T4

6952

auto[1]

153049104

1

T1

1735

T2

99990

T3

65530

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

126738804

1

T1

1503

T2

73296

T3

50675

auto[1]

26411031

1

T1

234

T2

26694

T3

15250

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	39197	1			T4	3474		T42	15		T23	339
all_values[0]	auto[0]	auto[1]	321	1			T4	2		T46	2		T54	1
all_values[0]	auto[1]	auto[0]	50900830	1			T1	561		T2	33324		T3	21957
all_values[0]	auto[1]	auto[1]	109597	1			T1	18		T2	6		T3	18
all_values[1]	auto[0]	auto[0]	27266	1			T1	2		T3	395		T5	28
all_values[1]	auto[0]	auto[1]	171	1			T46	3		T24	4		T131	3
all_values[1]	auto[1]	auto[0]	51018736	1			T1	577		T2	33330		T3	21580
all_values[1]	auto[1]	auto[1]	3772	1			T9	152		T10	42		T11	84
all_values[2]	auto[0]	auto[0]	14346	1			T4	3476		T5	1		T31	1
all_values[2]	auto[0]	auto[1]	19430	1			T5	27		T31	37		T37	19
all_values[2]	auto[1]	auto[0]	24738429	1			T1	363		T2	6642		T3	6743
all_values[2]	auto[1]	auto[1]	26277740	1			T1	216		T2	26688		T3	15232