Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::msg_len_cg

Group : hmac_env_pkg::hmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
82.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	2	16	88.89
Crosses	32	7	25	78.12

Variables for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hmac_en	2	0	2	100.00	100	1	1	2
msg_len_lower_cp	15	1	14	93.33	100	1	1	0
msg_len_upper_cp	1	1	0	0.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::msg_len_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
msg_len_lower_cross	30	5	25	83.33	100	1	1	0
msg_len_upper_cross	2	2	0	0.00	100	1	1	0

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171102

1

T1

26

T2

26

T7

4

auto[1]

133928

1

T1

20

T2

32

T3

50

---

Summary for Variable msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	1	14	93.33

User Defined Bins for msg_len_lower_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_511	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_2050_plus	47035	1			T2	28		T3	6		T4	24
len_1026_2046	31659	1			T2	1		T4	3		T8	4
len_514_1022	9005	1			T4	1		T8	2		T5	213
len_2_510	55758	1			T1	18		T7	7		T15	106
len_2049	11	1			T140	3		T141	2		T134	2
len_2048	57	1			T5	4		T142	2		T24	1
len_2047	20	1			T89	20		-	-		-	-
len_1025	25	1			T57	1		T141	8		T143	2
len_1024	99	1			T5	4		T33	1		T10	1
len_1023	10	1			T110	1		T144	2		T145	1
len_513	2	1			T146	1		T147	1		-	-
len_512	124	1			T5	5		T38	1		T142	3
len_1	1184	1			T3	17		T4	11		T8	2
len_0	7526	1			T1	5		T3	2		T8	1

---

Summary for Variable msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	1	0	0.00

User Defined Bins for msg_len_upper_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
len_upper	0	1	1

---

Summary for Cross msg_len_lower_cross

Samples crossed: hmac_en msg_len_lower_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	5	25	83.33	5

Automatically Generated Cross Bins for msg_len_lower_cross

Uncovered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[len_1025]	0	1	1
[auto[0]]	[len_513]	0	1	1
[auto[0]]	[len_511]	0	1	1
[auto[1]]	[len_2047]	0	1	1
[auto[1]]	[len_511]	0	1	1

Covered bins

hmac_en	msg_len_lower_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	len_2050_plus	27933	1			T2	12		T8	57		T5	498
auto[0]	len_1026_2046	16954	1			T2	1		T8	4		T5	333
auto[0]	len_514_1022	5900	1			T8	2		T5	96		T12	3
auto[0]	len_2_510	30180	1			T1	12		T7	2		T8	145
auto[0]	len_2049	2	1			T134	1		T148	1		-	-
auto[0]	len_2048	32	1			T5	4		T142	2		T106	1
auto[0]	len_2047	20	1			T89	20		-	-		-	-
auto[0]	len_1024	58	1			T5	3		T33	1		T142	2
auto[0]	len_1023	8	1			T144	1		T145	1		T149	2
auto[0]	len_512	73	1			T5	4		T142	3		T46	2
auto[0]	len_1	220	1			T8	2		T13	1		T150	1
auto[0]	len_0	4171	1			T1	1		T8	1		T5	1
auto[1]	len_2050_plus	19102	1			T2	16		T3	6		T4	24
auto[1]	len_1026_2046	14705	1			T4	3		T5	67		T44	2
auto[1]	len_514_1022	3105	1			T4	1		T5	117		T33	5
auto[1]	len_2_510	25578	1			T1	6		T7	5		T15	106
auto[1]	len_2049	9	1			T140	3		T141	2		T134	1
auto[1]	len_2048	25	1			T24	1		T131	1		T108	1
auto[1]	len_1025	25	1			T57	1		T141	8		T143	2
auto[1]	len_1024	41	1			T5	1		T10	1		T131	1
auto[1]	len_1023	2	1			T110	1		T144	1		-	-
auto[1]	len_513	2	1			T146	1		T147	1		-	-
auto[1]	len_512	51	1			T5	1		T38	1		T24	1
auto[1]	len_1	964	1			T3	17		T4	11		T46	20
auto[1]	len_0	3355	1			T1	4		T3	2		T5	176

---

Summary for Cross msg_len_upper_cross

Samples crossed: hmac_en msg_len_upper_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	2	2	0	0.00	2

Automatically Generated Cross Bins for msg_len_upper_cross

Uncovered bins

hmac_en	msg_len_upper_cp	COUNT	AT LEAST	NUMBER	STATUS
*	*	--	--	2