Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::status_cg

Group : hmac_env_pkg::hmac_env_cov::status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	96	0	96	100.00

Variables for Group hmac_env_pkg::hmac_env_cov::status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	2
sta_fifo_depth	8	0	8	100.00	100	1	1	0
sta_fifo_empty	2	0	2	100.00	100	1	1	2
sta_fifo_full	2	0	2	100.00	100	1	1	2

Crosses for Group hmac_env_pkg::hmac_env_cov::status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
fifo_empty_cross	16	0	16	100.00	100	1	1	0
fifo_full_cross	16	0	16	100.00	100	1	1	0
fifo_depth_cross	64	0	64	100.00	100	1	1	0

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24938805

1

T1

347

T2

3659

T3

9609

auto[1]

2196325

1

T1

127

T2

4947

T3

11819

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2250810

1

T1

289

T2

5208

T3

15485

auto[1]

24884320

1

T1

185

T2

3398

T3

5943

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23010432

1

T1

159

T2

5107

T7

70

auto[1]

4124698

1

T1

315

T2

3499

T3

21428

---

Summary for Variable sta_fifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for sta_fifo_depth

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	23735152	1			T1	393		T2	8286		T3	18264
fifo_depth[1]	703669	1			T1	5		T2	170		T3	327
fifo_depth[2]	524759	1			T1	4		T2	74		T3	312
fifo_depth[3]	412197	1			T1	6		T2	47		T3	337
fifo_depth[4]	322041	1			T1	11		T2	18		T3	295
fifo_depth[5]	249937	1			T1	4		T2	8		T3	316
fifo_depth[6]	217160	1			T1	7		T2	2		T3	301
fifo_depth[7]	193172	1			T1	6		T2	1		T3	279

---

Summary for Variable sta_fifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3399978

1

T1

81

T2

320

T3

3164

auto[1]

23735152

1

T1

393

T2

8286

T3

18264

---

Summary for Variable sta_fifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sta_fifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27123256

1

T1

474

T2

8606

T3

21428

auto[1]

11874

1

T157

6

T26

2

T131

1510

---

Summary for Cross fifo_empty_cross

Samples crossed: sta_fifo_empty hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_empty_cross

Bins

sta_fifo_empty

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

64142

1

T1

20

T2

172

T5

2

auto[0]

auto[0]

auto[0]

auto[1]

57512

1

T2

84

T5

55

T40

377

auto[0]

auto[0]

auto[1]

auto[0]

2597696

1

T7

3

T8

7822

T5

1

auto[0]

auto[0]

auto[1]

auto[1]

65261

1

T2

16

T5

41

T40

545

auto[0]

auto[1]

auto[0]

auto[0]

122848

1

T1

14

T3

766

T7

7

auto[0]

auto[1]

auto[0]

auto[1]

120000

1

T1

25

T2

9

T3

2169

auto[0]

auto[1]

auto[1]

auto[0]

275741

1

T1

22

T15

680

T4

4040

auto[0]

auto[1]

auto[1]

auto[1]

96778

1

T2

39

T3

229

T7

5

auto[1]

auto[0]

auto[0]

auto[0]

247170

1

T1

69

T2

2803

T5

1473

auto[1]

auto[0]

auto[0]

auto[1]

237812

1

T1

30

T2

1291

T7

2

auto[1]

auto[0]

auto[1]

auto[0]

19498909

1

T1

23

T2

3

T7

63

auto[1]

auto[0]

auto[1]

auto[1]

241930

1

T1

17

T2

738

T7

2

auto[1]

auto[1]

auto[0]

auto[0]

701514

1

T1

85

T2

428

T3

6765

auto[1]

auto[1]

auto[0]

auto[1]

699812

1

T1

46

T2

421

T3

5785

auto[1]

auto[1]

auto[1]

auto[0]

1430785

1

T1

114

T2

253

T3

2078

auto[1]

auto[1]

auto[1]

auto[1]

677220

1

T1

9

T2

2349

T3

3636

---

Summary for Cross fifo_full_cross

Samples crossed: sta_fifo_full hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for fifo_full_cross

Bins

sta_fifo_full

hmac_en

endian_swap

digest_swap

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

308867

1

T1

89

T2

2975

T5

1475

auto[0]

auto[0]

auto[0]

auto[1]

294606

1

T1

30

T2

1375

T7

2

auto[0]

auto[0]

auto[1]

auto[0]

22095752

1

T1

23

T2

3

T7

66

auto[0]

auto[0]

auto[1]

auto[1]

305728

1

T1

17

T2

754

T7

2

auto[0]

auto[1]

auto[0]

auto[0]

823193

1

T1

99

T2

428

T3

7531

auto[0]

auto[1]

auto[0]

auto[1]

817650

1

T1

71

T2

430

T3

7954

auto[0]

auto[1]

auto[1]

auto[0]

1705395

1

T1

136

T2

253

T3

2078

auto[0]

auto[1]

auto[1]

auto[1]

772065

1

T1

9

T2

2388

T3

3865

auto[1]

auto[0]

auto[0]

auto[0]

2445

1

T134

352

T158

6

T110

1196

auto[1]

auto[0]

auto[0]

auto[1]

718

1

T26

1

T131

63

T28

1

auto[1]

auto[0]

auto[1]

auto[0]

853

1

T26

1

T131

106

T29

1

auto[1]

auto[0]

auto[1]

auto[1]

1463

1

T28

1

T159

18

T134

79

auto[1]

auto[1]

auto[0]

auto[0]

1169

1

T131

1

T29

1

T134

1

auto[1]

auto[1]

auto[0]

auto[1]

2162

1

T131

8

T106

15

T107

1

auto[1]

auto[1]

auto[1]

auto[0]

1131

1

T157

4

T131

2

T159

3

auto[1]

auto[1]

auto[1]

auto[1]

1933

1

T157

2

T131

1330

T28

1

---

Summary for Cross fifo_depth_cross

Samples crossed: sta_fifo_depth hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for fifo_depth_cross

Bins

sta_fifo_depth	hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
fifo_depth[0]	auto[0]	auto[0]	auto[0]	247170	1			T1	69		T2	2803		T5	1473
fifo_depth[0]	auto[0]	auto[0]	auto[1]	237812	1			T1	30		T2	1291		T7	2
fifo_depth[0]	auto[0]	auto[1]	auto[0]	19498909	1			T1	23		T2	3		T7	63
fifo_depth[0]	auto[0]	auto[1]	auto[1]	241930	1			T1	17		T2	738		T7	2
fifo_depth[0]	auto[1]	auto[0]	auto[0]	701514	1			T1	85		T2	428		T3	6765
fifo_depth[0]	auto[1]	auto[0]	auto[1]	699812	1			T1	46		T2	421		T3	5785
fifo_depth[0]	auto[1]	auto[1]	auto[0]	1430785	1			T1	114		T2	253		T3	2078
fifo_depth[0]	auto[1]	auto[1]	auto[1]	677220	1			T1	9		T2	2349		T3	3636
fifo_depth[1]	auto[0]	auto[0]	auto[0]	5978	1			T1	2		T2	67		T5	1
fifo_depth[1]	auto[0]	auto[0]	auto[1]	5882	1			T2	57		T5	3		T40	32
fifo_depth[1]	auto[0]	auto[1]	auto[0]	608593	1			T8	3629		T12	2508		T13	4952
fifo_depth[1]	auto[0]	auto[1]	auto[1]	6157	1			T2	16		T5	13		T40	41
fifo_depth[1]	auto[1]	auto[0]	auto[0]	13125	1			T3	86		T7	1		T4	140
fifo_depth[1]	auto[1]	auto[0]	auto[1]	12233	1			T1	2		T2	9		T3	224
fifo_depth[1]	auto[1]	auto[1]	auto[0]	41560	1			T1	1		T15	179		T4	356
fifo_depth[1]	auto[1]	auto[1]	auto[1]	10141	1			T2	21		T3	17		T7	2
fifo_depth[2]	auto[0]	auto[0]	auto[0]	5276	1			T1	3		T2	41		T5	1
fifo_depth[2]	auto[0]	auto[0]	auto[1]	5310	1			T2	20		T5	33		T40	26
fifo_depth[2]	auto[0]	auto[1]	auto[0]	443055	1			T8	2213		T5	1		T12	2393
fifo_depth[2]	auto[0]	auto[1]	auto[1]	5411	1			T5	12		T40	50		T22	20
fifo_depth[2]	auto[1]	auto[0]	auto[0]	11959	1			T3	79		T7	3		T4	150
fifo_depth[2]	auto[1]	auto[0]	auto[1]	11304	1			T1	1		T3	214		T4	252
fifo_depth[2]	auto[1]	auto[1]	auto[0]	33278	1			T15	149		T4	396		T20	193
fifo_depth[2]	auto[1]	auto[1]	auto[1]	9166	1			T2	13		T3	19		T4	298
fifo_depth[3]	auto[0]	auto[0]	auto[0]	4039	1			T1	2		T2	38		T42	4
fifo_depth[3]	auto[0]	auto[0]	auto[1]	3923	1			T2	6		T40	37		T22	19
fifo_depth[3]	auto[0]	auto[1]	auto[0]	344484	1			T7	1		T8	1217		T12	1955
fifo_depth[3]	auto[0]	auto[1]	auto[1]	4438	1			T5	7		T40	49		T22	13
fifo_depth[3]	auto[1]	auto[0]	auto[0]	10551	1			T1	1		T3	79		T7	1
fifo_depth[3]	auto[1]	auto[0]	auto[1]	10031	1			T1	3		T3	243		T4	289
fifo_depth[3]	auto[1]	auto[1]	auto[0]	26924	1			T15	141		T4	367		T20	154
fifo_depth[3]	auto[1]	auto[1]	auto[1]	7807	1			T2	3		T3	15		T7	1
fifo_depth[4]	auto[0]	auto[0]	auto[0]	3932	1			T1	4		T2	16		T42	2
fifo_depth[4]	auto[0]	auto[0]	auto[1]	3812	1			T2	1		T5	19		T40	44
fifo_depth[4]	auto[0]	auto[1]	auto[0]	259634	1			T7	1		T8	529		T12	1455
fifo_depth[4]	auto[0]	auto[1]	auto[1]	4393	1			T5	8		T40	45		T22	4
fifo_depth[4]	auto[1]	auto[0]	auto[0]	10085	1			T1	1		T3	83		T7	1
fifo_depth[4]	auto[1]	auto[0]	auto[1]	9695	1			T1	2		T3	199		T4	258
fifo_depth[4]	auto[1]	auto[1]	auto[0]	23227	1			T1	4		T15	102		T4	358
fifo_depth[4]	auto[1]	auto[1]	auto[1]	7263	1			T2	1		T3	13		T4	299
fifo_depth[5]	auto[0]	auto[0]	auto[0]	3068	1			T1	1		T2	7		T43	1
fifo_depth[5]	auto[0]	auto[0]	auto[1]	3186	1			T40	51		T23	1		T142	2
fifo_depth[5]	auto[0]	auto[1]	auto[0]	195026	1			T7	1		T8	166		T12	1257
fifo_depth[5]	auto[0]	auto[1]	auto[1]	3601	1			T40	52		T22	1		T38	4
fifo_depth[5]	auto[1]	auto[0]	auto[0]	9346	1			T3	93		T7	1		T4	135
fifo_depth[5]	auto[1]	auto[0]	auto[1]	8951	1			T1	1		T3	200		T4	277
fifo_depth[5]	auto[1]	auto[1]	auto[0]	20075	1			T1	2		T15	64		T4	406
fifo_depth[5]	auto[1]	auto[1]	auto[1]	6684	1			T2	1		T3	23		T4	269
fifo_depth[6]	auto[0]	auto[0]	auto[0]	3179	1			T1	4		T2	2		T22	1
fifo_depth[6]	auto[0]	auto[0]	auto[1]	3060	1			T40	37		T142	2		T46	4
fifo_depth[6]	auto[0]	auto[1]	auto[0]	164760	1			T8	55		T12	1087		T13	2132
fifo_depth[6]	auto[0]	auto[1]	auto[1]	3488	1			T40	45		T22	3		T38	11
fifo_depth[6]	auto[1]	auto[0]	auto[0]	9227	1			T1	1		T3	91		T4	110
fifo_depth[6]	auto[1]	auto[0]	auto[1]	8912	1			T1	1		T3	190		T4	309
fifo_depth[6]	auto[1]	auto[1]	auto[0]	17876	1			T1	1		T15	31		T4	360
fifo_depth[6]	auto[1]	auto[1]	auto[1]	6658	1			T3	20		T4	279		T40	18
fifo_depth[7]	auto[0]	auto[0]	auto[0]	2776	1			T1	2		T2	1		T38	5
fifo_depth[7]	auto[0]	auto[0]	auto[1]	2882	1			T40	39		T142	2		T46	3
fifo_depth[7]	auto[0]	auto[1]	auto[0]	145087	1			T8	8		T12	893		T13	1857
fifo_depth[7]	auto[0]	auto[1]	auto[1]	3116	1			T5	1		T40	48		T38	3
fifo_depth[7]	auto[1]	auto[0]	auto[0]	8641	1			T1	1		T3	68		T4	109
fifo_depth[7]	auto[1]	auto[0]	auto[1]	8437	1			T1	2		T3	187		T4	247
fifo_depth[7]	auto[1]	auto[1]	auto[0]	15914	1			T1	1		T15	12		T4	329
fifo_depth[7]	auto[1]	auto[1]	auto[1]	6319	1			T3	24		T7	1		T4	242