Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	51049945	1			T1	579		T2	33330		T3	21975
all_pins[1]	51049945	1			T1	579		T2	33330		T3	21975
all_pins[2]	51049945	1			T1	579		T2	33330		T3	21975

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	126757967	1			T1	1501		T2	73296		T3	50675
values[0x1]	26391868	1			T1	236		T2	26694		T3	15250
transitions[0x0=>0x1]	26391638	1			T1	236		T2	26694		T3	15250
transitions[0x1=>0x0]	26391643	1			T1	236		T2	26694		T3	15250

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	50939685	1			T1	559		T2	33324		T3	21957
all_pins[0]	values[0x1]	110260	1			T1	20		T2	6		T3	18
all_pins[0]	transitions[0x0=>0x1]	110219	1			T1	20		T2	6		T3	18
all_pins[0]	transitions[0x1=>0x0]	26277704	1			T1	216		T2	26688		T3	15232
all_pins[1]	values[0x0]	51046077	1			T1	579		T2	33330		T3	21975
all_pins[1]	values[0x1]	3868	1			T9	156		T10	43		T11	86
all_pins[1]	transitions[0x0=>0x1]	3719	1			T9	151		T10	42		T11	84
all_pins[1]	transitions[0x1=>0x0]	110111	1			T1	20		T2	6		T3	18
all_pins[2]	values[0x0]	24772205	1			T1	363		T2	6642		T3	6743
all_pins[2]	values[0x1]	26277740	1			T1	216		T2	26688		T3	15232
all_pins[2]	transitions[0x0=>0x1]	26277700	1			T1	216		T2	26688		T3	15232
all_pins[2]	transitions[0x1=>0x0]	3828	1			T9	156		T10	43		T11	86