Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 0 18 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 0 18 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 758 1 T46 7 T54 4 T24 17
all_values[1] 758 1 T46 7 T54 4 T24 17
all_values[2] 758 1 T46 7 T54 4 T24 17


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1262 1 T46 15 T54 2 T24 30
auto[1] 1012 1 T46 6 T54 10 T24 21


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 799 1 T46 8 T54 4 T24 20
auto[1] 1475 1 T46 13 T54 8 T24 31


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1290 1 T46 13 T54 7 T24 29
auto[1] 984 1 T46 8 T54 5 T24 22


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 0 18 100.00
Automatically Generated Cross Bins 18 0 18 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 154 1 T46 3 T24 4 T131 2
all_values[0] auto[0] auto[0] auto[1] 88 1 T46 1 T24 1 T106 2
all_values[0] auto[0] auto[1] auto[0] 116 1 T46 1 T54 1 T24 2
all_values[0] auto[0] auto[1] auto[1] 60 1 T24 2 T106 1 T134 1
all_values[0] auto[1] auto[0] auto[1] 181 1 T46 1 T54 1 T24 7
all_values[0] auto[1] auto[1] auto[1] 159 1 T46 1 T54 2 T24 1
all_values[1] auto[0] auto[0] auto[0] 138 1 T46 1 T54 1 T24 4
all_values[1] auto[0] auto[0] auto[1] 99 1 T46 1 T24 3 T106 2
all_values[1] auto[0] auto[1] auto[0] 108 1 T54 1 T24 1 T106 3
all_values[1] auto[0] auto[1] auto[1] 93 1 T46 2 T54 1 T24 2
all_values[1] auto[1] auto[0] auto[1] 176 1 T46 3 T24 3 T131 3
all_values[1] auto[1] auto[1] auto[1] 144 1 T54 1 T24 4 T131 2
all_values[2] auto[0] auto[0] auto[0] 165 1 T46 3 T24 2 T131 1
all_values[2] auto[0] auto[0] auto[1] 86 1 T46 1 T24 1 T106 1
all_values[2] auto[0] auto[1] auto[0] 118 1 T54 1 T24 7 T131 1
all_values[2] auto[0] auto[1] auto[1] 65 1 T54 2 T131 1 T106 2
all_values[2] auto[1] auto[0] auto[1] 175 1 T46 1 T24 5 T131 2
all_values[2] auto[1] auto[1] auto[1] 149 1 T46 2 T54 1 T24 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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