Unified Coverage Report :: Group :: hmac_env_pkg::hmac_env_cov::cfg_cg

Group : hmac_env_pkg::hmac_env_cov::cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.47	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_hmac_env_0.1/hmac_env_cov.sv

---

Summary for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	2	18	90.00
Crosses	82	22	60	73.17

Variables for Group hmac_env_pkg::hmac_env_cov::cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
digest_size	5	1	4	80.00	100	1	1	0
digest_swap	2	0	2	100.00	100	1	1	2
endian_swap	2	0	2	100.00	100	1	1	2
hmac_en	2	0	2	100.00	100	1	1	0
key_length	7	1	6	85.71	100	1	1	0
sha_en	2	0	2	100.00	100	1	1	0

Crosses for Group hmac_env_pkg::hmac_env_cov::cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cfg_cross	8	0	8	100.00	100	1	1	0
hmac_dis_x_sha_en	4	0	4	100.00	100	1	1	0
key_x_digest_mismatch	35	11	24	68.57	100	1	1	0
key_length_x_digest_size	35	11	24	68.57	100	1	1	0

Summary for Variable digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	1	4	80.00

User Defined Bins for digest_size

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
sha2_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
sha2_none	127	1			T2	1		T42	1		T44	2
sha2_512	41004	1			T1	7		T2	14		T3	5
sha2_384	42979	1			T1	3		T2	4		T3	5
sha2_256	25217	1			T1	5		T2	13		T3	3

---

Summary for Variable digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for digest_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104902

1

T1

10

T2

14

T3

6

auto[1]

4425

1

T1

5

T2

18

T3

7

---

Summary for Variable endian_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for endian_swap

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4577

1

T1

10

T2

23

T3

10

auto[1]

104750

1

T1

5

T2

9

T3

3

---

Summary for Variable hmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for hmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

40525

1

T1

6

T2

9

T3

13

disabled

68802

1

T1

9

T2

23

T7

3

---

Summary for Variable key_length

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	1	6	85.71

User Defined Bins for key_length

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
key_invalid	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	65677	1			T2	2		T7	1		T8	386
key_1024	19824	1			T1	5		T2	7		T15	225
key_512	13355	1			T1	3		T2	1		T3	2
key_384	7485	1			T1	3		T2	10		T3	5
key_256	1493	1			T1	3		T2	10		T3	3
key_128	1493	1			T1	1		T2	2		T3	3

---

Summary for Variable sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

108969

1

T1

15

T2

25

T3

13

disabled

358

1

T2

7

T42

3

T44

3

---

Summary for Cross cfg_cross

Samples crossed: hmac_en endian_swap digest_swap

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cfg_cross

Bins

hmac_en	endian_swap	digest_swap	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
enabled	auto[0]	auto[0]	1093	1			T1	1		T2	1		T3	5
enabled	auto[0]	auto[1]	1044	1			T1	2		T2	2		T3	5
enabled	auto[1]	auto[0]	37415	1			T1	3		T2	1		T3	1
enabled	auto[1]	auto[1]	973	1			T2	5		T3	2		T7	1
disabled	auto[0]	auto[0]	1203	1			T1	5		T2	10		T5	3
disabled	auto[0]	auto[1]	1237	1			T1	2		T2	10		T5	3
disabled	auto[1]	auto[0]	65191	1			T1	1		T2	2		T7	2
disabled	auto[1]	auto[1]	1171	1			T1	1		T2	1		T7	1

---

Summary for Cross hmac_dis_x_sha_en

Samples crossed: hmac_en sha_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	4	0	4	100.00
Automatically Generated Cross Bins	3	0	3	100.00
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for hmac_dis_x_sha_en

Bins

hmac_en

sha_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

enabled

enabled

40342

1

T1

6

T2

6

T3

13

enabled

disabled

183

1

T2

3

T42

3

T44

2

disabled

disabled

175

1

T2

4

T44

1

T43

1

User Defined Cross Bins for hmac_dis_x_sha_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

68627

1

T1

9

T2

19

T7

3

---

Summary for Cross key_x_digest_mismatch

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	35	11	24	68.57	11
Automatically Generated Cross Bins	34	11	23	67.65	11
User Defined Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for key_x_digest_mismatch

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	46	1			T43	1		T131	1		T106	2
key_none	sha2_512	24295	1			T2	1		T7	1		T8	386
key_none	sha2_384	27187	1			T5	3		T44	1		T40	1
key_none	sha2_256	14149	1			T2	1		T5	1		T12	194
key_1024	sha2_none	17	1			T42	1		T106	2		T137	1
key_1024	sha2_512	14632	1			T1	2		T2	5		T15	225
key_1024	sha2_384	4907	1			T1	2		T2	1		T42	5
key_512	sha2_none	24	1			T43	1		T131	1		T106	1
key_512	sha2_512	534	1			T1	2		T2	1		T3	1
key_512	sha2_384	9368	1			T1	1		T3	1		T7	1
key_512	sha2_256	3429	1			T20	45		T21	45		T5	1
key_384	sha2_none	13	1			T44	1		T46	1		T106	1
key_384	sha2_512	494	1			T1	1		T3	2		T6	1
key_384	sha2_384	513	1			T3	2		T4	1		T5	1
key_384	sha2_256	6465	1			T1	2		T2	10		T3	1
key_256	sha2_none	9	1			T44	1		T110	1		T138	1
key_256	sha2_512	518	1			T1	1		T2	7		T3	1
key_256	sha2_384	514	1			T2	3		T3	1		T7	1
key_256	sha2_256	452	1			T1	2		T3	1		T4	4
key_128	sha2_none	18	1			T2	1		T139	1		T106	1
key_128	sha2_512	531	1			T1	1		T3	1		T7	1
key_128	sha2_384	490	1			T3	1		T42	1		T40	1
key_128	sha2_256	454	1			T2	1		T3	1		T4	2

User Defined Cross Bins for key_x_digest_mismatch

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

b0

268

1

T1

1

T2

1

T22

1

---

Summary for Cross key_length_x_digest_size

Samples crossed: key_length digest_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	11	24	68.57	11

Automatically Generated Cross Bins for key_length_x_digest_size

Element holes

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_invalid]	*	--	--	5

Uncovered bins

key_length	digest_size	COUNT	AT LEAST	NUMBER	STATUS
[key_none , key_1024 , key_512 , key_384 , key_256 , key_128]	[sha2_invalid]	--	--	6

Covered bins

key_length	digest_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
key_none	sha2_none	46	1			T43	1		T131	1		T106	2
key_none	sha2_512	24295	1			T2	1		T7	1		T8	386
key_none	sha2_384	27187	1			T5	3		T44	1		T40	1
key_none	sha2_256	14149	1			T2	1		T5	1		T12	194
key_1024	sha2_none	17	1			T42	1		T106	2		T137	1
key_1024	sha2_512	14632	1			T1	2		T2	5		T15	225
key_1024	sha2_384	4907	1			T1	2		T2	1		T42	5
key_1024	sha2_256	268	1			T1	1		T2	1		T22	1
key_512	sha2_none	24	1			T43	1		T131	1		T106	1
key_512	sha2_512	534	1			T1	2		T2	1		T3	1
key_512	sha2_384	9368	1			T1	1		T3	1		T7	1
key_512	sha2_256	3429	1			T20	45		T21	45		T5	1
key_384	sha2_none	13	1			T44	1		T46	1		T106	1
key_384	sha2_512	494	1			T1	1		T3	2		T6	1
key_384	sha2_384	513	1			T3	2		T4	1		T5	1
key_384	sha2_256	6465	1			T1	2		T2	10		T3	1
key_256	sha2_none	9	1			T44	1		T110	1		T138	1
key_256	sha2_512	518	1			T1	1		T2	7		T3	1
key_256	sha2_384	514	1			T2	3		T3	1		T7	1
key_256	sha2_256	452	1			T1	2		T3	1		T4	4
key_128	sha2_none	18	1			T2	1		T139	1		T106	1
key_128	sha2_512	531	1			T1	1		T3	1		T7	1
key_128	sha2_384	490	1			T3	1		T42	1		T40	1
key_128	sha2_256	454	1			T2	1		T3	1		T4	2