Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.67 95.94 94.34 100.00 79.49 92.33 99.49 94.10


Total test records in report: 913
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T794 /workspace/coverage/cover_reg_top/48.hmac_intr_test.1492340970 Jun 28 05:54:36 PM PDT 24 Jun 28 05:54:44 PM PDT 24 34566279 ps
T795 /workspace/coverage/cover_reg_top/23.hmac_intr_test.2954509693 Jun 28 05:54:31 PM PDT 24 Jun 28 05:54:38 PM PDT 24 48615574 ps
T47 /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2744941028 Jun 28 05:54:30 PM PDT 24 Jun 28 05:54:39 PM PDT 24 76992469 ps
T48 /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1662451974 Jun 28 05:54:10 PM PDT 24 Jun 28 05:54:15 PM PDT 24 53147199 ps
T796 /workspace/coverage/cover_reg_top/43.hmac_intr_test.1099927239 Jun 28 05:54:37 PM PDT 24 Jun 28 05:54:45 PM PDT 24 41439764 ps
T797 /workspace/coverage/cover_reg_top/24.hmac_intr_test.714009085 Jun 28 05:54:26 PM PDT 24 Jun 28 05:54:33 PM PDT 24 46056145 ps
T60 /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4105725621 Jun 28 05:54:10 PM PDT 24 Jun 28 05:54:19 PM PDT 24 957728709 ps
T798 /workspace/coverage/cover_reg_top/35.hmac_intr_test.3100299964 Jun 28 05:54:42 PM PDT 24 Jun 28 05:54:49 PM PDT 24 61084808 ps
T74 /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3074530057 Jun 28 05:54:26 PM PDT 24 Jun 28 05:54:34 PM PDT 24 148865962 ps
T799 /workspace/coverage/cover_reg_top/45.hmac_intr_test.2383694399 Jun 28 05:54:37 PM PDT 24 Jun 28 05:54:45 PM PDT 24 100668059 ps
T120 /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.279799603 Jun 28 05:53:57 PM PDT 24 Jun 28 05:54:15 PM PDT 24 1425562933 ps
T75 /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3626682946 Jun 28 05:54:22 PM PDT 24 Jun 28 05:54:28 PM PDT 24 34899877 ps
T68 /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.95731294 Jun 28 05:53:54 PM PDT 24 Jun 28 05:53:57 PM PDT 24 217851099 ps
T800 /workspace/coverage/cover_reg_top/41.hmac_intr_test.3999941230 Jun 28 05:54:40 PM PDT 24 Jun 28 05:54:47 PM PDT 24 16923278 ps
T111 /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2860918163 Jun 28 05:54:00 PM PDT 24 Jun 28 05:54:09 PM PDT 24 663473511 ps
T801 /workspace/coverage/cover_reg_top/13.hmac_intr_test.606792476 Jun 28 05:54:25 PM PDT 24 Jun 28 05:54:31 PM PDT 24 75091103 ps
T112 /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2348907992 Jun 28 05:54:21 PM PDT 24 Jun 28 05:54:26 PM PDT 24 18026363 ps
T802 /workspace/coverage/cover_reg_top/26.hmac_intr_test.3551062095 Jun 28 05:54:27 PM PDT 24 Jun 28 05:54:33 PM PDT 24 12457697 ps
T126 /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.224374050 Jun 28 05:54:00 PM PDT 24 Jun 28 05:54:06 PM PDT 24 239753330 ps
T803 /workspace/coverage/cover_reg_top/46.hmac_intr_test.4256208991 Jun 28 05:54:38 PM PDT 24 Jun 28 05:54:46 PM PDT 24 18509271 ps
T61 /workspace/coverage/cover_reg_top/4.hmac_tl_errors.309568529 Jun 28 05:53:52 PM PDT 24 Jun 28 05:53:56 PM PDT 24 161284822 ps
T804 /workspace/coverage/cover_reg_top/18.hmac_intr_test.383372252 Jun 28 05:54:36 PM PDT 24 Jun 28 05:54:44 PM PDT 24 27999548 ps
T65 /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3727650463 Jun 28 05:53:56 PM PDT 24 Jun 28 05:54:01 PM PDT 24 49819441 ps
T62 /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3767482256 Jun 28 05:53:44 PM PDT 24 Jun 28 05:53:51 PM PDT 24 578782143 ps
T67 /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1403813188 Jun 28 05:54:19 PM PDT 24 Jun 28 05:54:26 PM PDT 24 255608161 ps
T121 /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1916734146 Jun 28 05:53:52 PM PDT 24 Jun 28 05:53:59 PM PDT 24 428320143 ps
T805 /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3518353440 Jun 28 05:54:29 PM PDT 24 Jun 28 05:54:36 PM PDT 24 95425615 ps
T806 /workspace/coverage/cover_reg_top/25.hmac_intr_test.3908397404 Jun 28 05:54:29 PM PDT 24 Jun 28 05:54:36 PM PDT 24 74101669 ps
T127 /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3129197464 Jun 28 05:54:35 PM PDT 24 Jun 28 05:54:43 PM PDT 24 55130507 ps
T807 /workspace/coverage/cover_reg_top/10.hmac_intr_test.3395913009 Jun 28 05:54:20 PM PDT 24 Jun 28 05:54:25 PM PDT 24 17374638 ps
T63 /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3065529294 Jun 28 05:54:01 PM PDT 24 Jun 28 05:54:07 PM PDT 24 158673466 ps
T113 /workspace/coverage/cover_reg_top/1.hmac_csr_rw.525340979 Jun 28 05:53:53 PM PDT 24 Jun 28 05:53:55 PM PDT 24 117728514 ps
T808 /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4027458321 Jun 28 05:54:29 PM PDT 24 Jun 28 05:54:37 PM PDT 24 34043808 ps
T128 /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2876219604 Jun 28 05:53:52 PM PDT 24 Jun 28 05:53:55 PM PDT 24 105891790 ps
T64 /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.227048767 Jun 28 05:53:55 PM PDT 24 Jun 28 05:53:58 PM PDT 24 174929752 ps
T114 /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1761312841 Jun 28 05:53:55 PM PDT 24 Jun 28 05:53:57 PM PDT 24 30753382 ps
T129 /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3482607675 Jun 28 05:54:30 PM PDT 24 Jun 28 05:54:37 PM PDT 24 157190580 ps
T115 /workspace/coverage/cover_reg_top/7.hmac_csr_rw.948222000 Jun 28 05:54:10 PM PDT 24 Jun 28 05:54:15 PM PDT 24 38225428 ps
T116 /workspace/coverage/cover_reg_top/13.hmac_csr_rw.193798760 Jun 28 05:54:25 PM PDT 24 Jun 28 05:54:31 PM PDT 24 261186046 ps
T117 /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4265034656 Jun 28 05:54:29 PM PDT 24 Jun 28 05:54:36 PM PDT 24 113731933 ps
T809 /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.545413516 Jun 28 05:53:52 PM PDT 24 Jun 28 05:53:59 PM PDT 24 223834308 ps
T810 /workspace/coverage/cover_reg_top/6.hmac_intr_test.525830710 Jun 28 05:54:02 PM PDT 24 Jun 28 05:54:05 PM PDT 24 48471885 ps
T811 /workspace/coverage/cover_reg_top/14.hmac_intr_test.1525188135 Jun 28 05:54:21 PM PDT 24 Jun 28 05:54:25 PM PDT 24 15172134 ps
T812 /workspace/coverage/cover_reg_top/9.hmac_tl_errors.722852491 Jun 28 05:54:13 PM PDT 24 Jun 28 05:54:22 PM PDT 24 78648872 ps
T813 /workspace/coverage/cover_reg_top/32.hmac_intr_test.3055457736 Jun 28 05:54:37 PM PDT 24 Jun 28 05:54:45 PM PDT 24 17635219 ps
T814 /workspace/coverage/cover_reg_top/1.hmac_intr_test.73247975 Jun 28 05:53:53 PM PDT 24 Jun 28 05:53:56 PM PDT 24 11054436 ps
T151 /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.360698147 Jun 28 05:54:28 PM PDT 24 Jun 28 05:54:37 PM PDT 24 211576763 ps
T70 /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3562757982 Jun 28 05:53:55 PM PDT 24 Jun 28 05:53:59 PM PDT 24 103223780 ps
T815 /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2760640111 Jun 28 05:54:01 PM PDT 24 Jun 28 05:54:05 PM PDT 24 47702774 ps
T816 /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.818796224 Jun 28 05:54:28 PM PDT 24 Jun 28 05:54:36 PM PDT 24 79320653 ps
T73 /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2885736777 Jun 28 05:54:03 PM PDT 24 Jun 28 05:54:12 PM PDT 24 888228915 ps
T817 /workspace/coverage/cover_reg_top/21.hmac_intr_test.3065212469 Jun 28 05:54:31 PM PDT 24 Jun 28 05:54:38 PM PDT 24 17538745 ps
T118 /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2860013018 Jun 28 05:54:22 PM PDT 24 Jun 28 05:54:27 PM PDT 24 35136584 ps
T818 /workspace/coverage/cover_reg_top/5.hmac_intr_test.2606993166 Jun 28 05:54:03 PM PDT 24 Jun 28 05:54:08 PM PDT 24 30253605 ps
T819 /workspace/coverage/cover_reg_top/12.hmac_intr_test.2326447847 Jun 28 05:54:20 PM PDT 24 Jun 28 05:54:24 PM PDT 24 13203500 ps
T820 /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4242735768 Jun 28 05:54:11 PM PDT 24 Jun 28 05:54:18 PM PDT 24 89980660 ps
T119 /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3294332757 Jun 28 05:54:21 PM PDT 24 Jun 28 05:54:26 PM PDT 24 42042702 ps
T122 /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1902826742 Jun 28 05:53:53 PM PDT 24 Jun 28 05:53:55 PM PDT 24 435649874 ps
T130 /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.792456538 Jun 28 05:53:52 PM PDT 24 Jun 28 05:53:55 PM PDT 24 310001943 ps
T821 /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1784715544 Jun 28 05:54:09 PM PDT 24 Jun 28 05:54:14 PM PDT 24 240685663 ps
T822 /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.448349361 Jun 28 05:54:00 PM PDT 24 Jun 28 05:54:05 PM PDT 24 133048802 ps
T69 /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3399519958 Jun 28 05:54:10 PM PDT 24 Jun 28 05:54:19 PM PDT 24 195180345 ps
T823 /workspace/coverage/cover_reg_top/20.hmac_intr_test.2125172281 Jun 28 05:54:26 PM PDT 24 Jun 28 05:54:33 PM PDT 24 116105528 ps
T153 /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1990003952 Jun 28 05:54:12 PM PDT 24 Jun 28 05:54:19 PM PDT 24 681307425 ps
T123 /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3112334234 Jun 28 05:54:02 PM PDT 24 Jun 28 05:54:17 PM PDT 24 745828136 ps
T824 /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2447909250 Jun 28 05:54:29 PM PDT 24 Jun 28 05:54:38 PM PDT 24 42966359 ps
T825 /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3851179633 Jun 28 05:53:51 PM PDT 24 Jun 28 05:53:56 PM PDT 24 227811252 ps
T826 /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.399231309 Jun 28 05:53:54 PM PDT 24 Jun 28 05:53:58 PM PDT 24 594616446 ps
T827 /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.507417574 Jun 28 05:54:10 PM PDT 24 Jun 28 05:54:17 PM PDT 24 81449012 ps
T828 /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.55124425 Jun 28 05:53:54 PM PDT 24 Jun 28 05:53:58 PM PDT 24 103862737 ps
T829 /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2420515235 Jun 28 05:54:29 PM PDT 24 Jun 28 05:54:39 PM PDT 24 367607293 ps
T830 /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2174651883 Jun 28 05:54:11 PM PDT 24 Jun 28 05:54:18 PM PDT 24 308840287 ps
T124 /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1384100122 Jun 28 05:53:53 PM PDT 24 Jun 28 05:54:01 PM PDT 24 6505792735 ps
T831 /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3497800037 Jun 28 05:54:32 PM PDT 24 Jun 28 05:54:42 PM PDT 24 45095985 ps
T832 /workspace/coverage/cover_reg_top/47.hmac_intr_test.4175990425 Jun 28 05:54:38 PM PDT 24 Jun 28 05:54:46 PM PDT 24 37250089 ps
T833 /workspace/coverage/cover_reg_top/19.hmac_intr_test.268749327 Jun 28 05:54:26 PM PDT 24 Jun 28 05:54:33 PM PDT 24 51882881 ps
T834 /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.840540413 Jun 28 05:53:52 PM PDT 24 Jun 28 05:53:57 PM PDT 24 102471527 ps
T835 /workspace/coverage/cover_reg_top/29.hmac_intr_test.2610691891 Jun 28 05:54:30 PM PDT 24 Jun 28 05:54:37 PM PDT 24 47275242 ps
T836 /workspace/coverage/cover_reg_top/49.hmac_intr_test.3886184099 Jun 28 05:54:38 PM PDT 24 Jun 28 05:54:46 PM PDT 24 66087810 ps
T837 /workspace/coverage/cover_reg_top/11.hmac_csr_rw.590328246 Jun 28 05:54:21 PM PDT 24 Jun 28 05:54:25 PM PDT 24 16815833 ps
T838 /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1601730980 Jun 28 05:54:02 PM PDT 24 Jun 28 05:54:06 PM PDT 24 43820009 ps
T839 /workspace/coverage/cover_reg_top/8.hmac_intr_test.3220895840 Jun 28 05:54:10 PM PDT 24 Jun 28 05:54:15 PM PDT 24 17645327 ps
T840 /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2053729547 Jun 28 05:53:53 PM PDT 24 Jun 28 05:53:57 PM PDT 24 87314412 ps
T841 /workspace/coverage/cover_reg_top/4.hmac_csr_rw.157736382 Jun 28 05:54:01 PM PDT 24 Jun 28 05:54:05 PM PDT 24 53949818 ps
T842 /workspace/coverage/cover_reg_top/39.hmac_intr_test.166540864 Jun 28 05:54:38 PM PDT 24 Jun 28 05:54:45 PM PDT 24 46472822 ps
T843 /workspace/coverage/cover_reg_top/11.hmac_intr_test.3120319852 Jun 28 05:54:19 PM PDT 24 Jun 28 05:54:22 PM PDT 24 12267196 ps
T844 /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2991366031 Jun 28 05:54:25 PM PDT 24 Jun 28 05:54:32 PM PDT 24 128656800 ps
T845 /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3620758287 Jun 28 05:53:52 PM PDT 24 Jun 28 05:53:56 PM PDT 24 121389112 ps
T156 /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2270664040 Jun 28 05:54:26 PM PDT 24 Jun 28 05:54:36 PM PDT 24 442134623 ps
T846 /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2755570982 Jun 28 05:54:01 PM PDT 24 Jun 28 05:54:06 PM PDT 24 590784132 ps
T154 /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2213455428 Jun 28 05:54:18 PM PDT 24 Jun 28 05:54:25 PM PDT 24 453103473 ps
T847 /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2703216314 Jun 28 05:54:01 PM PDT 24 Jun 28 05:54:05 PM PDT 24 14203673 ps
T848 /workspace/coverage/cover_reg_top/4.hmac_intr_test.1686100736 Jun 28 05:54:01 PM PDT 24 Jun 28 05:54:05 PM PDT 24 15450929 ps
T849 /workspace/coverage/cover_reg_top/33.hmac_intr_test.3750931787 Jun 28 05:54:41 PM PDT 24 Jun 28 05:54:47 PM PDT 24 55074668 ps
T850 /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2455402122 Jun 28 05:54:10 PM PDT 24 Jun 28 05:54:18 PM PDT 24 52251140 ps
T851 /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3541586031 Jun 28 05:54:37 PM PDT 24 Jun 28 05:54:45 PM PDT 24 42714889 ps
T125 /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1595266277 Jun 28 05:53:45 PM PDT 24 Jun 28 05:53:49 PM PDT 24 72599235 ps
T852 /workspace/coverage/cover_reg_top/15.hmac_intr_test.1632282046 Jun 28 05:54:29 PM PDT 24 Jun 28 05:54:36 PM PDT 24 35378132 ps
T853 /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2992586834 Jun 28 05:54:19 PM PDT 24 Jun 28 05:54:25 PM PDT 24 102403275 ps
T854 /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4203864101 Jun 28 05:53:52 PM PDT 24 Jun 28 05:53:57 PM PDT 24 117828988 ps
T855 /workspace/coverage/cover_reg_top/15.hmac_tl_errors.256394743 Jun 28 05:54:27 PM PDT 24 Jun 28 05:54:35 PM PDT 24 147317492 ps
T856 /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1933644862 Jun 28 05:54:02 PM PDT 24 Jun 28 05:54:07 PM PDT 24 59255658 ps
T857 /workspace/coverage/cover_reg_top/38.hmac_intr_test.729054817 Jun 28 05:54:38 PM PDT 24 Jun 28 05:54:45 PM PDT 24 24229892 ps
T858 /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.733709302 Jun 28 05:54:22 PM PDT 24 Jun 28 05:54:28 PM PDT 24 407206847 ps
T155 /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3541307222 Jun 28 05:54:19 PM PDT 24 Jun 28 05:54:25 PM PDT 24 183210691 ps
T859 /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4056646194 Jun 28 05:54:22 PM PDT 24 Jun 28 05:54:28 PM PDT 24 62466687 ps
T860 /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3994188347 Jun 28 05:54:37 PM PDT 24 Jun 28 05:54:44 PM PDT 24 78989864 ps
T861 /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1163032984 Jun 28 05:54:21 PM PDT 24 Jun 28 05:54:27 PM PDT 24 38025674 ps
T862 /workspace/coverage/cover_reg_top/31.hmac_intr_test.3015578709 Jun 28 05:54:38 PM PDT 24 Jun 28 05:54:45 PM PDT 24 14495060 ps
T863 /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3425295573 Jun 28 05:53:52 PM PDT 24 Jun 28 05:53:55 PM PDT 24 28280726 ps
T864 /workspace/coverage/cover_reg_top/37.hmac_intr_test.2256189065 Jun 28 05:54:38 PM PDT 24 Jun 28 05:54:46 PM PDT 24 51329688 ps
T865 /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1622871185 Jun 28 05:54:10 PM PDT 24 Jun 28 05:54:16 PM PDT 24 37952946 ps
T866 /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3283326882 Jun 28 05:53:52 PM PDT 24 Jun 28 05:54:00 PM PDT 24 548704970 ps
T867 /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2573188776 Jun 28 05:54:27 PM PDT 24 Jun 28 05:54:34 PM PDT 24 91369799 ps
T868 /workspace/coverage/cover_reg_top/0.hmac_intr_test.1533542960 Jun 28 05:53:44 PM PDT 24 Jun 28 05:53:48 PM PDT 24 43655857 ps
T869 /workspace/coverage/cover_reg_top/7.hmac_tl_errors.936411970 Jun 28 05:54:12 PM PDT 24 Jun 28 05:54:19 PM PDT 24 62150096 ps
T72 /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1418658143 Jun 28 05:54:09 PM PDT 24 Jun 28 05:54:16 PM PDT 24 164858680 ps
T71 /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2419009268 Jun 28 05:54:28 PM PDT 24 Jun 28 05:54:37 PM PDT 24 651571563 ps
T870 /workspace/coverage/cover_reg_top/34.hmac_intr_test.3457283026 Jun 28 05:54:39 PM PDT 24 Jun 28 05:54:47 PM PDT 24 20876637 ps
T871 /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3338186865 Jun 28 05:54:29 PM PDT 24 Jun 28 05:54:36 PM PDT 24 20539509 ps
T872 /workspace/coverage/cover_reg_top/36.hmac_intr_test.4253903479 Jun 28 05:54:37 PM PDT 24 Jun 28 05:54:45 PM PDT 24 18592231 ps
T873 /workspace/coverage/cover_reg_top/16.hmac_intr_test.3805821969 Jun 28 05:54:30 PM PDT 24 Jun 28 05:54:37 PM PDT 24 80832998 ps
T152 /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3838919619 Jun 28 05:54:20 PM PDT 24 Jun 28 05:54:25 PM PDT 24 415282739 ps
T874 /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1265451844 Jun 28 05:53:51 PM PDT 24 Jun 28 05:53:55 PM PDT 24 97646801 ps
T875 /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3915571510 Jun 28 05:54:28 PM PDT 24 Jun 28 05:54:36 PM PDT 24 66474712 ps
T876 /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3761393099 Jun 28 05:54:02 PM PDT 24 Jun 28 05:54:07 PM PDT 24 111893469 ps
T877 /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3539785500 Jun 28 05:54:20 PM PDT 24 Jun 28 05:54:26 PM PDT 24 361384150 ps
T878 /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3588247016 Jun 28 05:53:54 PM PDT 24 Jun 28 05:53:57 PM PDT 24 19681718 ps
T879 /workspace/coverage/cover_reg_top/40.hmac_intr_test.2372927722 Jun 28 05:54:38 PM PDT 24 Jun 28 05:54:45 PM PDT 24 29097683 ps
T880 /workspace/coverage/cover_reg_top/22.hmac_intr_test.3484374381 Jun 28 05:54:26 PM PDT 24 Jun 28 05:54:33 PM PDT 24 13793577 ps
T881 /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.198218459 Jun 28 05:54:19 PM PDT 24 Jun 28 05:54:24 PM PDT 24 91604737 ps
T882 /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2765466953 Jun 28 05:53:51 PM PDT 24 Jun 28 05:53:58 PM PDT 24 671541594 ps
T883 /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4090296127 Jun 28 05:53:53 PM PDT 24 Jun 28 05:53:57 PM PDT 24 112658683 ps
T884 /workspace/coverage/cover_reg_top/44.hmac_intr_test.3614922887 Jun 28 05:54:38 PM PDT 24 Jun 28 05:54:45 PM PDT 24 12318991 ps
T885 /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2089385684 Jun 28 05:54:37 PM PDT 24 Jun 28 05:54:46 PM PDT 24 622217782 ps
T886 /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4134932125 Jun 28 05:54:22 PM PDT 24 Jun 28 05:54:30 PM PDT 24 125183523 ps
T887 /workspace/coverage/cover_reg_top/30.hmac_intr_test.4234066291 Jun 28 05:54:28 PM PDT 24 Jun 28 05:54:36 PM PDT 24 11521942 ps
T888 /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1127455836 Jun 28 05:54:28 PM PDT 24 Jun 28 05:54:36 PM PDT 24 31845867 ps
T889 /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3996605258 Jun 28 05:54:30 PM PDT 24 Jun 28 05:54:38 PM PDT 24 50457753 ps
T890 /workspace/coverage/cover_reg_top/13.hmac_tl_errors.364315511 Jun 28 05:54:19 PM PDT 24 Jun 28 05:54:24 PM PDT 24 103951508 ps
T891 /workspace/coverage/cover_reg_top/27.hmac_intr_test.3216306823 Jun 28 05:54:29 PM PDT 24 Jun 28 05:54:36 PM PDT 24 15320582 ps
T892 /workspace/coverage/cover_reg_top/28.hmac_intr_test.659322454 Jun 28 05:54:37 PM PDT 24 Jun 28 05:54:45 PM PDT 24 34423087 ps
T893 /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2852089534 Jun 28 05:54:21 PM PDT 24 Jun 28 05:54:28 PM PDT 24 148639441 ps
T894 /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1869203365 Jun 28 05:54:01 PM PDT 24 Jun 28 05:54:08 PM PDT 24 488674112 ps
T895 /workspace/coverage/cover_reg_top/3.hmac_intr_test.4107512387 Jun 28 05:53:54 PM PDT 24 Jun 28 05:53:57 PM PDT 24 14997474 ps
T896 /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3502688114 Jun 28 05:54:10 PM PDT 24 Jun 28 05:54:17 PM PDT 24 121259499 ps
T897 /workspace/coverage/cover_reg_top/2.hmac_intr_test.2982620313 Jun 28 05:53:56 PM PDT 24 Jun 28 05:53:59 PM PDT 24 23226416 ps
T898 /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.610510722 Jun 28 05:53:56 PM PDT 24 Jun 28 05:54:00 PM PDT 24 48666440 ps
T899 /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1131708427 Jun 28 05:54:03 PM PDT 24 Jun 28 05:54:08 PM PDT 24 87953646 ps
T900 /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1120057515 Jun 28 05:54:27 PM PDT 24 Jun 28 05:54:35 PM PDT 24 1588079438 ps
T901 /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3851249850 Jun 28 05:54:26 PM PDT 24 Jun 28 05:54:34 PM PDT 24 130261452 ps
T902 /workspace/coverage/cover_reg_top/9.hmac_intr_test.2069695412 Jun 28 05:54:10 PM PDT 24 Jun 28 05:54:15 PM PDT 24 14666288 ps
T903 /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3125600654 Jun 28 05:54:20 PM PDT 24 Jun 28 05:54:25 PM PDT 24 144771449 ps
T904 /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.850193148 Jun 28 05:53:52 PM PDT 24 Jun 28 05:53:54 PM PDT 24 17911067 ps
T905 /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3242077165 Jun 28 05:54:00 PM PDT 24 Jun 28 05:54:08 PM PDT 24 834888405 ps
T906 /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2846371034 Jun 28 05:54:11 PM PDT 24 Jun 28 05:54:17 PM PDT 24 74585842 ps
T907 /workspace/coverage/cover_reg_top/7.hmac_intr_test.1602849535 Jun 28 05:54:11 PM PDT 24 Jun 28 05:54:16 PM PDT 24 136031155 ps
T908 /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2774827912 Jun 28 05:53:54 PM PDT 24 Jun 28 05:53:58 PM PDT 24 109135372 ps
T909 /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.750380777 Jun 28 05:54:29 PM PDT 24 Jun 28 05:54:40 PM PDT 24 358497965 ps
T910 /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.311650135 Jun 28 05:54:11 PM PDT 24 Jun 28 05:54:20 PM PDT 24 584282333 ps
T911 /workspace/coverage/cover_reg_top/42.hmac_intr_test.2986764861 Jun 28 05:54:37 PM PDT 24 Jun 28 05:54:45 PM PDT 24 43946209 ps
T912 /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1594022291 Jun 28 05:54:27 PM PDT 24 Jun 28 05:54:37 PM PDT 24 89869808 ps
T913 /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3630646604 Jun 28 05:53:43 PM PDT 24 Jun 28 05:53:48 PM PDT 24 62452440 ps

Test location /workspace/coverage/default/39.hmac_datapath_stress.378552272
Short name T4
Test name
Test status
Simulation time 8579791247 ps
CPU time 1275.02 seconds
Started Jun 28 05:04:32 PM PDT 24
Finished Jun 28 05:25:48 PM PDT 24
Peak memory 692480 kb
Host smart-3cd72f5b-6497-4aef-b52b-91185aa741a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378552272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_datapath_stress.378552272
Directory /workspace/39.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_stress_all_with_rand_reset.2012034131
Short name T14
Test name
Test status
Simulation time 35087708168 ps
CPU time 1226.77 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:20:59 PM PDT 24
Peak memory 734236 kb
Host smart-774cfe7b-4ab3-4704-978b-08bf9bbfd863
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2012034131 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all_with_rand_reset.2012034131
Directory /workspace/6.hmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.hmac_stress_all.3533013570
Short name T131
Test name
Test status
Simulation time 79509466679 ps
CPU time 2321.48 seconds
Started Jun 28 05:04:22 PM PDT 24
Finished Jun 28 05:43:04 PM PDT 24
Peak memory 215676 kb
Host smart-a85b44e6-4b2b-4e1e-94f8-69406a1a94b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533013570 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.hmac_stress_all.3533013570
Directory /workspace/37.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_burst_wr.1457252745
Short name T5
Test name
Test status
Simulation time 16681971922 ps
CPU time 66.91 seconds
Started Jun 28 05:04:31 PM PDT 24
Finished Jun 28 05:05:39 PM PDT 24
Peak memory 208468 kb
Host smart-4eefe1d1-2dd1-49c2-a1f3-c4289a95dcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457252745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_burst_wr.1457252745
Directory /workspace/40.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_test_sha512_vectors.2221975950
Short name T8
Test name
Test status
Simulation time 153861784233 ps
CPU time 1758.44 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 05:30:06 PM PDT 24
Peak memory 216216 kb
Host smart-e4e4167d-8bb5-4b3d-92c8-b79e5f083f00
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2221975950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha512_vectors.2221975950
Directory /workspace/9.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_intg_err.2885736777
Short name T73
Test name
Test status
Simulation time 888228915 ps
CPU time 4.16 seconds
Started Jun 28 05:54:03 PM PDT 24
Finished Jun 28 05:54:12 PM PDT 24
Peak memory 199884 kb
Host smart-5e71754c-65ba-4fda-b223-c29447f085f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885736777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_intg_err.2885736777
Directory /workspace/6.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/41.hmac_back_pressure.3449981935
Short name T9
Test name
Test status
Simulation time 1789345356 ps
CPU time 20.72 seconds
Started Jun 28 05:04:40 PM PDT 24
Finished Jun 28 05:05:01 PM PDT 24
Peak memory 200296 kb
Host smart-e2cafeda-c9f0-442c-a31e-0c704842f1f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449981935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_back_pressure.3449981935
Directory /workspace/41.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_sec_cm.2723498468
Short name T45
Test name
Test status
Simulation time 68351346 ps
CPU time 0.85 seconds
Started Jun 28 05:00:10 PM PDT 24
Finished Jun 28 05:00:11 PM PDT 24
Peak memory 218520 kb
Host smart-7be1a30a-a131-4906-a63f-ad4db52837ef
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723498468 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_sec_cm.2723498468
Directory /workspace/3.hmac_sec_cm/latest

Test location /workspace/coverage/default/17.hmac_stress_all.3496422538
Short name T46
Test name
Test status
Simulation time 30866031063 ps
CPU time 962.54 seconds
Started Jun 28 05:01:36 PM PDT 24
Finished Jun 28 05:17:39 PM PDT 24
Peak memory 664716 kb
Host smart-f982d009-d2bc-4bb0-b0c6-ea4f47b9b2f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496422538 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.hmac_stress_all.3496422538
Directory /workspace/17.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_aliasing.644997049
Short name T94
Test name
Test status
Simulation time 1590385690 ps
CPU time 6.35 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:54:00 PM PDT 24
Peak memory 199788 kb
Host smart-e19733c4-11b2-4607-a5ed-8b42ab452c08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644997049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_aliasing.644997049
Directory /workspace/1.hmac_csr_aliasing/latest

Test location /workspace/coverage/default/32.hmac_stress_all.3119761190
Short name T110
Test name
Test status
Simulation time 18309236603 ps
CPU time 932.34 seconds
Started Jun 28 05:03:35 PM PDT 24
Finished Jun 28 05:19:08 PM PDT 24
Peak memory 200264 kb
Host smart-8ddb25fe-8790-4cfd-91e4-9eb175d69b4d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119761190 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.hmac_stress_all.3119761190
Directory /workspace/32.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_error.3718365538
Short name T42
Test name
Test status
Simulation time 8262382078 ps
CPU time 40.18 seconds
Started Jun 28 05:01:50 PM PDT 24
Finished Jun 28 05:02:31 PM PDT 24
Peak memory 200340 kb
Host smart-f34e4f15-ad25-4a19-a5d5-405d2169f74b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718365538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_error.3718365538
Directory /workspace/19.hmac_error/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_intg_err.3065529294
Short name T63
Test name
Test status
Simulation time 158673466 ps
CPU time 3.01 seconds
Started Jun 28 05:54:01 PM PDT 24
Finished Jun 28 05:54:07 PM PDT 24
Peak memory 199848 kb
Host smart-394bb2b3-d518-44b4-9a3d-90b5e1e0c596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065529294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_intg_err.3065529294
Directory /workspace/5.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/1.hmac_stress_all.2303108204
Short name T134
Test name
Test status
Simulation time 168170114934 ps
CPU time 3582.37 seconds
Started Jun 28 04:59:59 PM PDT 24
Finished Jun 28 05:59:43 PM PDT 24
Peak memory 803848 kb
Host smart-b4beb7b5-95af-43ff-a050-d68ce4064f68
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303108204 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.hmac_stress_all.2303108204
Directory /workspace/1.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_alert_test.3475098959
Short name T18
Test name
Test status
Simulation time 34250910 ps
CPU time 0.58 seconds
Started Jun 28 05:01:00 PM PDT 24
Finished Jun 28 05:01:01 PM PDT 24
Peak memory 195804 kb
Host smart-4915e2cd-9eb3-400d-b0a2-479b242311a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475098959 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_alert_test.3475098959
Directory /workspace/11.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_datapath_stress.1360277377
Short name T57
Test name
Test status
Simulation time 6163490446 ps
CPU time 777.44 seconds
Started Jun 28 04:59:56 PM PDT 24
Finished Jun 28 05:12:54 PM PDT 24
Peak memory 716016 kb
Host smart-0b89776c-bffb-4946-8730-fc61d7b6fa89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1360277377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_datapath_stress.1360277377
Directory /workspace/0.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_stress_all.3329758545
Short name T595
Test name
Test status
Simulation time 80244333833 ps
CPU time 1190.92 seconds
Started Jun 28 05:01:58 PM PDT 24
Finished Jun 28 05:21:50 PM PDT 24
Peak memory 259236 kb
Host smart-eba2bcbe-02e9-4356-afda-8f2c76358358
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329758545 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.hmac_stress_all.3329758545
Directory /workspace/20.hmac_stress_all/latest

Test location /workspace/coverage/default/24.hmac_stress_all.18279814
Short name T147
Test name
Test status
Simulation time 102807604208 ps
CPU time 6678.85 seconds
Started Jun 28 05:02:33 PM PDT 24
Finished Jun 28 06:53:54 PM PDT 24
Peak memory 701992 kb
Host smart-a4c432a4-2a9a-4310-b0bb-ba118254f27d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18279814 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.hmac_stress_all.18279814
Directory /workspace/24.hmac_stress_all/latest

Test location /workspace/coverage/default/42.hmac_stress_all.2405461359
Short name T89
Test name
Test status
Simulation time 422603652681 ps
CPU time 3012 seconds
Started Jun 28 05:05:02 PM PDT 24
Finished Jun 28 05:55:16 PM PDT 24
Peak memory 808328 kb
Host smart-6b69c289-8952-488c-b2a9-22cde14e1e7c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405461359 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.hmac_stress_all.2405461359
Directory /workspace/42.hmac_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_rw.1902826742
Short name T122
Test name
Test status
Simulation time 435649874 ps
CPU time 0.96 seconds
Started Jun 28 05:53:53 PM PDT 24
Finished Jun 28 05:53:55 PM PDT 24
Peak memory 199588 kb
Host smart-9a08ec47-932c-4779-b96a-d3f4381df546
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902826742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_rw.1902826742
Directory /workspace/0.hmac_csr_rw/latest

Test location /workspace/coverage/default/10.hmac_back_pressure.4221453294
Short name T100
Test name
Test status
Simulation time 920615058 ps
CPU time 44.15 seconds
Started Jun 28 05:00:52 PM PDT 24
Finished Jun 28 05:01:37 PM PDT 24
Peak memory 200168 kb
Host smart-8d83a0ec-e1e8-4f0b-a2ac-4b8471828415
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221453294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_back_pressure.4221453294
Directory /workspace/10.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_wipe_secret.386763304
Short name T145
Test name
Test status
Simulation time 3621948108 ps
CPU time 78.27 seconds
Started Jun 28 05:00:10 PM PDT 24
Finished Jun 28 05:01:29 PM PDT 24
Peak memory 200196 kb
Host smart-e43e0e5d-9aa1-4056-be22-2e0b6b1b6845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386763304 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_wipe_secret.386763304
Directory /workspace/3.hmac_wipe_secret/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_intg_err.2419009268
Short name T71
Test name
Test status
Simulation time 651571563 ps
CPU time 1.95 seconds
Started Jun 28 05:54:28 PM PDT 24
Finished Jun 28 05:54:37 PM PDT 24
Peak memory 199848 kb
Host smart-afc19552-5f89-4aee-a041-5cee8e9ed21f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419009268 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_intg_err.2419009268
Directory /workspace/16.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_intg_err.1418658143
Short name T72
Test name
Test status
Simulation time 164858680 ps
CPU time 2.91 seconds
Started Jun 28 05:54:09 PM PDT 24
Finished Jun 28 05:54:16 PM PDT 24
Peak memory 199848 kb
Host smart-5db0c9f0-98ce-4c56-9d7c-17c82abe6db0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418658143 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_intg_err.1418658143
Directory /workspace/7.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_aliasing.1384100122
Short name T124
Test name
Test status
Simulation time 6505792735 ps
CPU time 6.25 seconds
Started Jun 28 05:53:53 PM PDT 24
Finished Jun 28 05:54:01 PM PDT 24
Peak memory 199844 kb
Host smart-4c756006-e6d4-407a-9f9a-9c37b43d5c53
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384100122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_aliasing.1384100122
Directory /workspace/0.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_bit_bash.279799603
Short name T120
Test name
Test status
Simulation time 1425562933 ps
CPU time 15.78 seconds
Started Jun 28 05:53:57 PM PDT 24
Finished Jun 28 05:54:15 PM PDT 24
Peak memory 199768 kb
Host smart-99bb4a25-c325-4b30-8cd2-258d28990ce1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279799603 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_bit_bash.279799603
Directory /workspace/0.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_hw_reset.1595266277
Short name T125
Test name
Test status
Simulation time 72599235 ps
CPU time 0.96 seconds
Started Jun 28 05:53:45 PM PDT 24
Finished Jun 28 05:53:49 PM PDT 24
Peak memory 199588 kb
Host smart-75aa81a2-8411-4bea-a59a-e3d36c3c6363
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595266277 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_csr_hw_reset.1595266277
Directory /workspace/0.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3727650463
Short name T65
Test name
Test status
Simulation time 49819441 ps
CPU time 2.91 seconds
Started Jun 28 05:53:56 PM PDT 24
Finished Jun 28 05:54:01 PM PDT 24
Peak memory 215456 kb
Host smart-8e81b6ab-32a7-4134-aa1c-8d0c37f44a13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727650463 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.hmac_csr_mem_rw_with_rand_reset.3727650463
Directory /workspace/0.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_intr_test.1533542960
Short name T868
Test name
Test status
Simulation time 43655857 ps
CPU time 0.64 seconds
Started Jun 28 05:53:44 PM PDT 24
Finished Jun 28 05:53:48 PM PDT 24
Peak memory 194632 kb
Host smart-c2152af1-7fe0-404f-ac58-cc93696295be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533542960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_intr_test.1533542960
Directory /workspace/0.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_same_csr_outstanding.792456538
Short name T130
Test name
Test status
Simulation time 310001943 ps
CPU time 1.75 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:53:55 PM PDT 24
Peak memory 199856 kb
Host smart-36db36ac-b9a7-44e0-83f6-139ae5bf0782
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792456538 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_same_csr_
outstanding.792456538
Directory /workspace/0.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_errors.3767482256
Short name T62
Test name
Test status
Simulation time 578782143 ps
CPU time 3.19 seconds
Started Jun 28 05:53:44 PM PDT 24
Finished Jun 28 05:53:51 PM PDT 24
Peak memory 199776 kb
Host smart-00378d42-1803-406f-b656-c21ea28eb7ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767482256 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_errors.3767482256
Directory /workspace/0.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.hmac_tl_intg_err.3630646604
Short name T913
Test name
Test status
Simulation time 62452440 ps
CPU time 1.84 seconds
Started Jun 28 05:53:43 PM PDT 24
Finished Jun 28 05:53:48 PM PDT 24
Peak memory 199900 kb
Host smart-a30c4ab4-3739-4297-86c1-a59c357af39f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630646604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.hmac_tl_intg_err.3630646604
Directory /workspace/0.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_bit_bash.1916734146
Short name T121
Test name
Test status
Simulation time 428320143 ps
CPU time 5.2 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:53:59 PM PDT 24
Peak memory 198708 kb
Host smart-1278f36a-1340-43b3-ab78-8cb10ea23f45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916734146 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_bit_bash.1916734146
Directory /workspace/1.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_hw_reset.3588247016
Short name T878
Test name
Test status
Simulation time 19681718 ps
CPU time 0.87 seconds
Started Jun 28 05:53:54 PM PDT 24
Finished Jun 28 05:53:57 PM PDT 24
Peak memory 199004 kb
Host smart-5a77d526-c368-41df-be14-030b1e5278b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588247016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_hw_reset.3588247016
Directory /workspace/1.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_mem_rw_with_rand_reset.2053729547
Short name T840
Test name
Test status
Simulation time 87314412 ps
CPU time 2.39 seconds
Started Jun 28 05:53:53 PM PDT 24
Finished Jun 28 05:53:57 PM PDT 24
Peak memory 199928 kb
Host smart-4d6dc197-a7f2-425b-8af9-c17deab39296
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053729547 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.hmac_csr_mem_rw_with_rand_reset.2053729547
Directory /workspace/1.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_csr_rw.525340979
Short name T113
Test name
Test status
Simulation time 117728514 ps
CPU time 0.94 seconds
Started Jun 28 05:53:53 PM PDT 24
Finished Jun 28 05:53:55 PM PDT 24
Peak memory 199336 kb
Host smart-2a22c11b-d1b5-4ab4-a514-55382459efd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525340979 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_csr_rw.525340979
Directory /workspace/1.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_intr_test.73247975
Short name T814
Test name
Test status
Simulation time 11054436 ps
CPU time 0.61 seconds
Started Jun 28 05:53:53 PM PDT 24
Finished Jun 28 05:53:56 PM PDT 24
Peak memory 194680 kb
Host smart-3a68e35c-cd1e-47e5-b7c0-cab5fe1af7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73247975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_intr_test.73247975
Directory /workspace/1.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_same_csr_outstanding.399231309
Short name T826
Test name
Test status
Simulation time 594616446 ps
CPU time 1.82 seconds
Started Jun 28 05:53:54 PM PDT 24
Finished Jun 28 05:53:58 PM PDT 24
Peak memory 199900 kb
Host smart-d02b9013-bdae-403c-9659-b48acd4541a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399231309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_same_csr_
outstanding.399231309
Directory /workspace/1.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_errors.3620758287
Short name T845
Test name
Test status
Simulation time 121389112 ps
CPU time 1.83 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:53:56 PM PDT 24
Peak memory 199832 kb
Host smart-7c9ed088-b599-4567-a6ae-48e4ed294531
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620758287 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_errors.3620758287
Directory /workspace/1.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.hmac_tl_intg_err.840540413
Short name T834
Test name
Test status
Simulation time 102471527 ps
CPU time 2.84 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:53:57 PM PDT 24
Peak memory 199900 kb
Host smart-cf17efac-657c-462d-ba13-80d80ca8899b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840540413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.hmac_tl_intg_err.840540413
Directory /workspace/1.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_mem_rw_with_rand_reset.1163032984
Short name T861
Test name
Test status
Simulation time 38025674 ps
CPU time 2.2 seconds
Started Jun 28 05:54:21 PM PDT 24
Finished Jun 28 05:54:27 PM PDT 24
Peak memory 199964 kb
Host smart-5c581734-57f7-436c-a3ba-93d05dc4d636
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163032984 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.hmac_csr_mem_rw_with_rand_reset.1163032984
Directory /workspace/10.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_csr_rw.3294332757
Short name T119
Test name
Test status
Simulation time 42042702 ps
CPU time 0.71 seconds
Started Jun 28 05:54:21 PM PDT 24
Finished Jun 28 05:54:26 PM PDT 24
Peak memory 197272 kb
Host smart-c69583a0-f0cd-4c31-ba0f-6b7954ff7a19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294332757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_csr_rw.3294332757
Directory /workspace/10.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_intr_test.3395913009
Short name T807
Test name
Test status
Simulation time 17374638 ps
CPU time 0.66 seconds
Started Jun 28 05:54:20 PM PDT 24
Finished Jun 28 05:54:25 PM PDT 24
Peak memory 194760 kb
Host smart-8b65b26f-c4b8-44d8-848f-cc9d5656a768
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395913009 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_intr_test.3395913009
Directory /workspace/10.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_same_csr_outstanding.198218459
Short name T881
Test name
Test status
Simulation time 91604737 ps
CPU time 2.17 seconds
Started Jun 28 05:54:19 PM PDT 24
Finished Jun 28 05:54:24 PM PDT 24
Peak memory 199900 kb
Host smart-3df1d386-e82e-454f-ba63-0665e78dd897
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198218459 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_same_csr
_outstanding.198218459
Directory /workspace/10.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_errors.3399519958
Short name T69
Test name
Test status
Simulation time 195180345 ps
CPU time 3.71 seconds
Started Jun 28 05:54:10 PM PDT 24
Finished Jun 28 05:54:19 PM PDT 24
Peak memory 199780 kb
Host smart-90f93baa-a795-431d-a334-e51304b3f635
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399519958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_errors.3399519958
Directory /workspace/10.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.hmac_tl_intg_err.311650135
Short name T910
Test name
Test status
Simulation time 584282333 ps
CPU time 4.09 seconds
Started Jun 28 05:54:11 PM PDT 24
Finished Jun 28 05:54:20 PM PDT 24
Peak memory 199836 kb
Host smart-9bd78c5d-e2e5-442d-bdf5-ce253ca1f1bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311650135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.hmac_tl_intg_err.311650135
Directory /workspace/10.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_mem_rw_with_rand_reset.3125600654
Short name T903
Test name
Test status
Simulation time 144771449 ps
CPU time 1.26 seconds
Started Jun 28 05:54:20 PM PDT 24
Finished Jun 28 05:54:25 PM PDT 24
Peak memory 199924 kb
Host smart-4939c51c-cd96-4afa-bcaa-83bd04cf6391
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125600654 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.hmac_csr_mem_rw_with_rand_reset.3125600654
Directory /workspace/11.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_csr_rw.590328246
Short name T837
Test name
Test status
Simulation time 16815833 ps
CPU time 0.85 seconds
Started Jun 28 05:54:21 PM PDT 24
Finished Jun 28 05:54:25 PM PDT 24
Peak memory 198992 kb
Host smart-a6af045b-a29c-49ec-938a-538d10e0e47c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590328246 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_csr_rw.590328246
Directory /workspace/11.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_intr_test.3120319852
Short name T843
Test name
Test status
Simulation time 12267196 ps
CPU time 0.62 seconds
Started Jun 28 05:54:19 PM PDT 24
Finished Jun 28 05:54:22 PM PDT 24
Peak memory 194680 kb
Host smart-e218415f-93a6-4b62-a333-c7736570d231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120319852 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_intr_test.3120319852
Directory /workspace/11.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_same_csr_outstanding.2991366031
Short name T844
Test name
Test status
Simulation time 128656800 ps
CPU time 1.57 seconds
Started Jun 28 05:54:25 PM PDT 24
Finished Jun 28 05:54:32 PM PDT 24
Peak memory 199796 kb
Host smart-4f091f0e-b856-4042-8324-533db1e0211d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991366031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_same_cs
r_outstanding.2991366031
Directory /workspace/11.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_errors.4134932125
Short name T886
Test name
Test status
Simulation time 125183523 ps
CPU time 4 seconds
Started Jun 28 05:54:22 PM PDT 24
Finished Jun 28 05:54:30 PM PDT 24
Peak memory 199724 kb
Host smart-0050edc9-46b1-47e8-94ae-1d8f91161fe3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134932125 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_errors.4134932125
Directory /workspace/11.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.hmac_tl_intg_err.733709302
Short name T858
Test name
Test status
Simulation time 407206847 ps
CPU time 1.93 seconds
Started Jun 28 05:54:22 PM PDT 24
Finished Jun 28 05:54:28 PM PDT 24
Peak memory 199760 kb
Host smart-81e57c55-9857-40ff-95d6-1fe838fd2770
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733709302 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.hmac_tl_intg_err.733709302
Directory /workspace/11.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_mem_rw_with_rand_reset.3626682946
Short name T75
Test name
Test status
Simulation time 34899877 ps
CPU time 1.2 seconds
Started Jun 28 05:54:22 PM PDT 24
Finished Jun 28 05:54:28 PM PDT 24
Peak memory 199652 kb
Host smart-5229ccd8-26ce-407f-8f5e-076cc3f53dce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626682946 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.hmac_csr_mem_rw_with_rand_reset.3626682946
Directory /workspace/12.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_csr_rw.2860013018
Short name T118
Test name
Test status
Simulation time 35136584 ps
CPU time 0.99 seconds
Started Jun 28 05:54:22 PM PDT 24
Finished Jun 28 05:54:27 PM PDT 24
Peak memory 199252 kb
Host smart-d3659b61-8598-46f5-8099-29f5fd01faf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860013018 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_csr_rw.2860013018
Directory /workspace/12.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_intr_test.2326447847
Short name T819
Test name
Test status
Simulation time 13203500 ps
CPU time 0.59 seconds
Started Jun 28 05:54:20 PM PDT 24
Finished Jun 28 05:54:24 PM PDT 24
Peak memory 194548 kb
Host smart-97191112-9d85-4e16-b598-923cfd66941b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326447847 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_intr_test.2326447847
Directory /workspace/12.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_same_csr_outstanding.3539785500
Short name T877
Test name
Test status
Simulation time 361384150 ps
CPU time 2.37 seconds
Started Jun 28 05:54:20 PM PDT 24
Finished Jun 28 05:54:26 PM PDT 24
Peak memory 199840 kb
Host smart-85c04348-d9d9-48a1-b441-7def56ab98ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539785500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_same_cs
r_outstanding.3539785500
Directory /workspace/12.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_errors.2992586834
Short name T853
Test name
Test status
Simulation time 102403275 ps
CPU time 2.94 seconds
Started Jun 28 05:54:19 PM PDT 24
Finished Jun 28 05:54:25 PM PDT 24
Peak memory 199780 kb
Host smart-8b4207d2-b01e-4c68-b042-b50c5085a135
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992586834 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_errors.2992586834
Directory /workspace/12.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.hmac_tl_intg_err.3838919619
Short name T152
Test name
Test status
Simulation time 415282739 ps
CPU time 1.95 seconds
Started Jun 28 05:54:20 PM PDT 24
Finished Jun 28 05:54:25 PM PDT 24
Peak memory 199852 kb
Host smart-116de7bc-bebc-4211-b4e3-c65c8967d994
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838919619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.hmac_tl_intg_err.3838919619
Directory /workspace/12.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_mem_rw_with_rand_reset.4056646194
Short name T859
Test name
Test status
Simulation time 62466687 ps
CPU time 1.11 seconds
Started Jun 28 05:54:22 PM PDT 24
Finished Jun 28 05:54:28 PM PDT 24
Peak memory 199588 kb
Host smart-3c06063d-8573-4abd-9ad6-51ed76cd6db3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056646194 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.hmac_csr_mem_rw_with_rand_reset.4056646194
Directory /workspace/13.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_csr_rw.193798760
Short name T116
Test name
Test status
Simulation time 261186046 ps
CPU time 0.85 seconds
Started Jun 28 05:54:25 PM PDT 24
Finished Jun 28 05:54:31 PM PDT 24
Peak memory 199016 kb
Host smart-0b538906-59c9-4dc1-821c-20adebfae3de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193798760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_csr_rw.193798760
Directory /workspace/13.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_intr_test.606792476
Short name T801
Test name
Test status
Simulation time 75091103 ps
CPU time 0.61 seconds
Started Jun 28 05:54:25 PM PDT 24
Finished Jun 28 05:54:31 PM PDT 24
Peak memory 194768 kb
Host smart-903dd5de-7c6e-415f-b654-d11849d59974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606792476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_intr_test.606792476
Directory /workspace/13.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_same_csr_outstanding.2852089534
Short name T893
Test name
Test status
Simulation time 148639441 ps
CPU time 2.59 seconds
Started Jun 28 05:54:21 PM PDT 24
Finished Jun 28 05:54:28 PM PDT 24
Peak memory 199848 kb
Host smart-13c45c4f-1c3c-425a-ab65-ff0d3a932739
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852089534 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_same_cs
r_outstanding.2852089534
Directory /workspace/13.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_errors.364315511
Short name T890
Test name
Test status
Simulation time 103951508 ps
CPU time 2.12 seconds
Started Jun 28 05:54:19 PM PDT 24
Finished Jun 28 05:54:24 PM PDT 24
Peak memory 199748 kb
Host smart-896e3403-e70d-4895-adff-3ae6f7f3f642
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364315511 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_errors.364315511
Directory /workspace/13.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.hmac_tl_intg_err.3541307222
Short name T155
Test name
Test status
Simulation time 183210691 ps
CPU time 3.31 seconds
Started Jun 28 05:54:19 PM PDT 24
Finished Jun 28 05:54:25 PM PDT 24
Peak memory 199824 kb
Host smart-5ed2e5f6-b499-4421-a92f-cda370bb09d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541307222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.hmac_tl_intg_err.3541307222
Directory /workspace/13.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_mem_rw_with_rand_reset.2744941028
Short name T47
Test name
Test status
Simulation time 76992469 ps
CPU time 1.83 seconds
Started Jun 28 05:54:30 PM PDT 24
Finished Jun 28 05:54:39 PM PDT 24
Peak memory 199544 kb
Host smart-c9115d52-1d12-4286-ae04-d69f5cd56e90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744941028 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.hmac_csr_mem_rw_with_rand_reset.2744941028
Directory /workspace/14.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_csr_rw.2348907992
Short name T112
Test name
Test status
Simulation time 18026363 ps
CPU time 0.82 seconds
Started Jun 28 05:54:21 PM PDT 24
Finished Jun 28 05:54:26 PM PDT 24
Peak memory 199336 kb
Host smart-a7e54dd4-f40c-4455-9f10-10299e68d5d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348907992 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_csr_rw.2348907992
Directory /workspace/14.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_intr_test.1525188135
Short name T811
Test name
Test status
Simulation time 15172134 ps
CPU time 0.63 seconds
Started Jun 28 05:54:21 PM PDT 24
Finished Jun 28 05:54:25 PM PDT 24
Peak memory 194636 kb
Host smart-ae7d59b2-443a-4c67-9525-5712f04eb5da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525188135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_intr_test.1525188135
Directory /workspace/14.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_same_csr_outstanding.3482607675
Short name T129
Test name
Test status
Simulation time 157190580 ps
CPU time 1.1 seconds
Started Jun 28 05:54:30 PM PDT 24
Finished Jun 28 05:54:37 PM PDT 24
Peak memory 199828 kb
Host smart-17296831-21ca-47a2-9ea1-00d95cfc945a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482607675 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_same_cs
r_outstanding.3482607675
Directory /workspace/14.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_errors.1403813188
Short name T67
Test name
Test status
Simulation time 255608161 ps
CPU time 3.84 seconds
Started Jun 28 05:54:19 PM PDT 24
Finished Jun 28 05:54:26 PM PDT 24
Peak memory 199844 kb
Host smart-3cdd1ccd-a048-4868-9e32-42cc83cdd14f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403813188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_errors.1403813188
Directory /workspace/14.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.hmac_tl_intg_err.2213455428
Short name T154
Test name
Test status
Simulation time 453103473 ps
CPU time 4.14 seconds
Started Jun 28 05:54:18 PM PDT 24
Finished Jun 28 05:54:25 PM PDT 24
Peak memory 200064 kb
Host smart-a0d53bbc-f6e8-4556-a1d1-975b09512962
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213455428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.hmac_tl_intg_err.2213455428
Directory /workspace/14.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_mem_rw_with_rand_reset.818796224
Short name T816
Test name
Test status
Simulation time 79320653 ps
CPU time 2.06 seconds
Started Jun 28 05:54:28 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 199896 kb
Host smart-30f29894-921c-4921-9b09-85d852aea997
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818796224 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.hmac_csr_mem_rw_with_rand_reset.818796224
Directory /workspace/15.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_csr_rw.3996605258
Short name T889
Test name
Test status
Simulation time 50457753 ps
CPU time 0.82 seconds
Started Jun 28 05:54:30 PM PDT 24
Finished Jun 28 05:54:38 PM PDT 24
Peak memory 198828 kb
Host smart-7df13c60-e123-4b02-9f5b-41cb3ad7eee3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996605258 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_csr_rw.3996605258
Directory /workspace/15.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_intr_test.1632282046
Short name T852
Test name
Test status
Simulation time 35378132 ps
CPU time 0.56 seconds
Started Jun 28 05:54:29 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 194632 kb
Host smart-b6ed4469-0682-4500-a81f-4f56dfd0e6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632282046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_intr_test.1632282046
Directory /workspace/15.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_same_csr_outstanding.3994188347
Short name T860
Test name
Test status
Simulation time 78989864 ps
CPU time 1.04 seconds
Started Jun 28 05:54:37 PM PDT 24
Finished Jun 28 05:54:44 PM PDT 24
Peak memory 199744 kb
Host smart-b3d9554d-7d2e-48ac-ad84-f1e34ee3a217
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994188347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_same_cs
r_outstanding.3994188347
Directory /workspace/15.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_errors.256394743
Short name T855
Test name
Test status
Simulation time 147317492 ps
CPU time 1.85 seconds
Started Jun 28 05:54:27 PM PDT 24
Finished Jun 28 05:54:35 PM PDT 24
Peak memory 199928 kb
Host smart-b2f429ce-7b0f-4e53-ace3-34f996f23bf4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256394743 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_errors.256394743
Directory /workspace/15.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.hmac_tl_intg_err.2270664040
Short name T156
Test name
Test status
Simulation time 442134623 ps
CPU time 4.34 seconds
Started Jun 28 05:54:26 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 199852 kb
Host smart-cc88ff7a-1f8c-42cf-ae22-38bd921acac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270664040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.hmac_tl_intg_err.2270664040
Directory /workspace/15.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_mem_rw_with_rand_reset.3851249850
Short name T901
Test name
Test status
Simulation time 130261452 ps
CPU time 1.25 seconds
Started Jun 28 05:54:26 PM PDT 24
Finished Jun 28 05:54:34 PM PDT 24
Peak memory 199716 kb
Host smart-7e5c52c4-759e-4730-942e-5b94fb31b910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851249850 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.hmac_csr_mem_rw_with_rand_reset.3851249850
Directory /workspace/16.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_csr_rw.3518353440
Short name T805
Test name
Test status
Simulation time 95425615 ps
CPU time 0.69 seconds
Started Jun 28 05:54:29 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 197592 kb
Host smart-4e820435-93a2-4063-9ee4-e9fda8535b02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518353440 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_csr_rw.3518353440
Directory /workspace/16.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_intr_test.3805821969
Short name T873
Test name
Test status
Simulation time 80832998 ps
CPU time 0.62 seconds
Started Jun 28 05:54:30 PM PDT 24
Finished Jun 28 05:54:37 PM PDT 24
Peak memory 194548 kb
Host smart-ec76b4f6-7ada-475e-b47e-8fe4f02c1fa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805821969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_intr_test.3805821969
Directory /workspace/16.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_same_csr_outstanding.2447909250
Short name T824
Test name
Test status
Simulation time 42966359 ps
CPU time 2.12 seconds
Started Jun 28 05:54:29 PM PDT 24
Finished Jun 28 05:54:38 PM PDT 24
Peak memory 199400 kb
Host smart-6719901b-4f0f-4053-b3be-4f6310b28a34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447909250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_same_cs
r_outstanding.2447909250
Directory /workspace/16.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.hmac_tl_errors.1594022291
Short name T912
Test name
Test status
Simulation time 89869808 ps
CPU time 4.46 seconds
Started Jun 28 05:54:27 PM PDT 24
Finished Jun 28 05:54:37 PM PDT 24
Peak memory 199700 kb
Host smart-a91db0cd-af4e-4736-8ef1-e0cad3c56d4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594022291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.hmac_tl_errors.1594022291
Directory /workspace/16.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_mem_rw_with_rand_reset.3497800037
Short name T831
Test name
Test status
Simulation time 45095985 ps
CPU time 2.9 seconds
Started Jun 28 05:54:32 PM PDT 24
Finished Jun 28 05:54:42 PM PDT 24
Peak memory 208104 kb
Host smart-7e90260f-2220-4e48-8e18-cae49d9c7184
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497800037 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.hmac_csr_mem_rw_with_rand_reset.3497800037
Directory /workspace/17.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_csr_rw.3338186865
Short name T871
Test name
Test status
Simulation time 20539509 ps
CPU time 0.71 seconds
Started Jun 28 05:54:29 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 197520 kb
Host smart-5e6c4615-d0f7-4b34-891b-147d3adbaa39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338186865 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_csr_rw.3338186865
Directory /workspace/17.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_intr_test.3614523543
Short name T793
Test name
Test status
Simulation time 64289608 ps
CPU time 0.66 seconds
Started Jun 28 05:54:28 PM PDT 24
Finished Jun 28 05:54:35 PM PDT 24
Peak memory 194680 kb
Host smart-6af5504c-8dbf-48e0-b8e5-afac71e30f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614523543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_intr_test.3614523543
Directory /workspace/17.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_same_csr_outstanding.3541586031
Short name T851
Test name
Test status
Simulation time 42714889 ps
CPU time 1.12 seconds
Started Jun 28 05:54:37 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 199504 kb
Host smart-b41351fb-f3cf-461c-96e9-120034c5670a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541586031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_same_cs
r_outstanding.3541586031
Directory /workspace/17.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_errors.1120057515
Short name T900
Test name
Test status
Simulation time 1588079438 ps
CPU time 2.06 seconds
Started Jun 28 05:54:27 PM PDT 24
Finished Jun 28 05:54:35 PM PDT 24
Peak memory 199776 kb
Host smart-38dd5d03-7e62-4c4e-ad3b-375661105e7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120057515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_errors.1120057515
Directory /workspace/17.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.hmac_tl_intg_err.360698147
Short name T151
Test name
Test status
Simulation time 211576763 ps
CPU time 3 seconds
Started Jun 28 05:54:28 PM PDT 24
Finished Jun 28 05:54:37 PM PDT 24
Peak memory 199912 kb
Host smart-5ab84209-e5a8-4ced-8d1e-51caf71e04a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360698147 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.hmac_tl_intg_err.360698147
Directory /workspace/17.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_mem_rw_with_rand_reset.4027458321
Short name T808
Test name
Test status
Simulation time 34043808 ps
CPU time 2.24 seconds
Started Jun 28 05:54:29 PM PDT 24
Finished Jun 28 05:54:37 PM PDT 24
Peak memory 199876 kb
Host smart-63beab1b-8e4a-48ed-bf9d-a5358fa8114f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027458321 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.hmac_csr_mem_rw_with_rand_reset.4027458321
Directory /workspace/18.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_csr_rw.4265034656
Short name T117
Test name
Test status
Simulation time 113731933 ps
CPU time 0.96 seconds
Started Jun 28 05:54:29 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 199580 kb
Host smart-54f8fa70-5078-4494-8dba-d02bfd0255c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265034656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_csr_rw.4265034656
Directory /workspace/18.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_intr_test.383372252
Short name T804
Test name
Test status
Simulation time 27999548 ps
CPU time 0.66 seconds
Started Jun 28 05:54:36 PM PDT 24
Finished Jun 28 05:54:44 PM PDT 24
Peak memory 194616 kb
Host smart-655ea3dd-1a4b-4847-9e9f-3af274861d03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383372252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_intr_test.383372252
Directory /workspace/18.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_same_csr_outstanding.3915571510
Short name T875
Test name
Test status
Simulation time 66474712 ps
CPU time 1.6 seconds
Started Jun 28 05:54:28 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 199596 kb
Host smart-e056f145-e54b-42e0-bea2-026aecaa179c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915571510 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_same_cs
r_outstanding.3915571510
Directory /workspace/18.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_errors.2420515235
Short name T829
Test name
Test status
Simulation time 367607293 ps
CPU time 4.18 seconds
Started Jun 28 05:54:29 PM PDT 24
Finished Jun 28 05:54:39 PM PDT 24
Peak memory 199784 kb
Host smart-60916f63-f723-4753-9374-a6b05351f295
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420515235 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_errors.2420515235
Directory /workspace/18.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.hmac_tl_intg_err.750380777
Short name T909
Test name
Test status
Simulation time 358497965 ps
CPU time 4.52 seconds
Started Jun 28 05:54:29 PM PDT 24
Finished Jun 28 05:54:40 PM PDT 24
Peak memory 199916 kb
Host smart-1eaa017a-19a2-4b28-b531-64c3e985bc73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750380777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.hmac_tl_intg_err.750380777
Directory /workspace/18.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_mem_rw_with_rand_reset.3074530057
Short name T74
Test name
Test status
Simulation time 148865962 ps
CPU time 1.19 seconds
Started Jun 28 05:54:26 PM PDT 24
Finished Jun 28 05:54:34 PM PDT 24
Peak memory 199684 kb
Host smart-4ba42dd7-5819-4b64-ada0-aad30f3816db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074530057 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.hmac_csr_mem_rw_with_rand_reset.3074530057
Directory /workspace/19.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_csr_rw.2573188776
Short name T867
Test name
Test status
Simulation time 91369799 ps
CPU time 0.86 seconds
Started Jun 28 05:54:27 PM PDT 24
Finished Jun 28 05:54:34 PM PDT 24
Peak memory 199596 kb
Host smart-e88900bb-cc5e-4901-abd6-8dd00228c05c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573188776 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_csr_rw.2573188776
Directory /workspace/19.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_intr_test.268749327
Short name T833
Test name
Test status
Simulation time 51882881 ps
CPU time 0.67 seconds
Started Jun 28 05:54:26 PM PDT 24
Finished Jun 28 05:54:33 PM PDT 24
Peak memory 194696 kb
Host smart-f2325c40-6a53-4f40-9f17-671b3089f56c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268749327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_intr_test.268749327
Directory /workspace/19.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_same_csr_outstanding.3129197464
Short name T127
Test name
Test status
Simulation time 55130507 ps
CPU time 1.12 seconds
Started Jun 28 05:54:35 PM PDT 24
Finished Jun 28 05:54:43 PM PDT 24
Peak memory 199436 kb
Host smart-c4ec45ee-63e1-47a6-bd19-5b04bed6a9e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129197464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_same_cs
r_outstanding.3129197464
Directory /workspace/19.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_errors.1127455836
Short name T888
Test name
Test status
Simulation time 31845867 ps
CPU time 1.82 seconds
Started Jun 28 05:54:28 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 199780 kb
Host smart-d495b57c-f8a8-41f4-8c0e-022bd38908da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127455836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_errors.1127455836
Directory /workspace/19.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.hmac_tl_intg_err.2089385684
Short name T885
Test name
Test status
Simulation time 622217782 ps
CPU time 1.98 seconds
Started Jun 28 05:54:37 PM PDT 24
Finished Jun 28 05:54:46 PM PDT 24
Peak memory 199780 kb
Host smart-de19cfca-9d24-4ea6-adeb-356f52c5c8fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089385684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.hmac_tl_intg_err.2089385684
Directory /workspace/19.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_aliasing.4203864101
Short name T854
Test name
Test status
Simulation time 117828988 ps
CPU time 3.01 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:53:57 PM PDT 24
Peak memory 199784 kb
Host smart-80d3d877-f1e3-44a0-a182-239114330228
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203864101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_aliasing.4203864101
Directory /workspace/2.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_bit_bash.545413516
Short name T809
Test name
Test status
Simulation time 223834308 ps
CPU time 5.37 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:53:59 PM PDT 24
Peak memory 199676 kb
Host smart-42286197-4d18-4f19-8110-78284701c992
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545413516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_bit_bash.545413516
Directory /workspace/2.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_hw_reset.610510722
Short name T898
Test name
Test status
Simulation time 48666440 ps
CPU time 0.73 seconds
Started Jun 28 05:53:56 PM PDT 24
Finished Jun 28 05:54:00 PM PDT 24
Peak memory 197528 kb
Host smart-df747682-c1aa-4fa5-8b08-baf655ccc8ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610510722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_hw_reset.610510722
Directory /workspace/2.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_mem_rw_with_rand_reset.3562757982
Short name T70
Test name
Test status
Simulation time 103223780 ps
CPU time 2.33 seconds
Started Jun 28 05:53:55 PM PDT 24
Finished Jun 28 05:53:59 PM PDT 24
Peak memory 199904 kb
Host smart-65b47a15-40db-40cd-88c9-190111008c55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562757982 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.hmac_csr_mem_rw_with_rand_reset.3562757982
Directory /workspace/2.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_csr_rw.1761312841
Short name T114
Test name
Test status
Simulation time 30753382 ps
CPU time 0.84 seconds
Started Jun 28 05:53:55 PM PDT 24
Finished Jun 28 05:53:57 PM PDT 24
Peak memory 199388 kb
Host smart-0cdb72c1-efb8-4556-8b1f-d49f9caa1701
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761312841 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_csr_rw.1761312841
Directory /workspace/2.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_intr_test.2982620313
Short name T897
Test name
Test status
Simulation time 23226416 ps
CPU time 0.6 seconds
Started Jun 28 05:53:56 PM PDT 24
Finished Jun 28 05:53:59 PM PDT 24
Peak memory 194780 kb
Host smart-de268b9d-7ec1-4993-828d-0c97c3fd7757
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982620313 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_intr_test.2982620313
Directory /workspace/2.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_same_csr_outstanding.2876219604
Short name T128
Test name
Test status
Simulation time 105891790 ps
CPU time 1.82 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:53:55 PM PDT 24
Peak memory 199772 kb
Host smart-9bec102c-0ba8-4414-9ee0-43403c7cb27b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876219604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_same_csr
_outstanding.2876219604
Directory /workspace/2.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_errors.2774827912
Short name T908
Test name
Test status
Simulation time 109135372 ps
CPU time 2.12 seconds
Started Jun 28 05:53:54 PM PDT 24
Finished Jun 28 05:53:58 PM PDT 24
Peak memory 199644 kb
Host smart-9f89bce7-d7b9-4971-a404-9b28b0893156
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774827912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_errors.2774827912
Directory /workspace/2.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.hmac_tl_intg_err.55124425
Short name T828
Test name
Test status
Simulation time 103862737 ps
CPU time 2.1 seconds
Started Jun 28 05:53:54 PM PDT 24
Finished Jun 28 05:53:58 PM PDT 24
Peak memory 199604 kb
Host smart-7406285e-3917-4ebe-bdc7-c580dbf38a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55124425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.hmac_tl_intg_err.55124425
Directory /workspace/2.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.hmac_intr_test.2125172281
Short name T823
Test name
Test status
Simulation time 116105528 ps
CPU time 0.59 seconds
Started Jun 28 05:54:26 PM PDT 24
Finished Jun 28 05:54:33 PM PDT 24
Peak memory 194636 kb
Host smart-1d0c714f-545a-4e7e-bab2-91a18de06a5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125172281 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.hmac_intr_test.2125172281
Directory /workspace/20.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.hmac_intr_test.3065212469
Short name T817
Test name
Test status
Simulation time 17538745 ps
CPU time 0.62 seconds
Started Jun 28 05:54:31 PM PDT 24
Finished Jun 28 05:54:38 PM PDT 24
Peak memory 194652 kb
Host smart-662d76ee-2d3e-47f0-b593-f395531ed374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065212469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.hmac_intr_test.3065212469
Directory /workspace/21.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.hmac_intr_test.3484374381
Short name T880
Test name
Test status
Simulation time 13793577 ps
CPU time 0.61 seconds
Started Jun 28 05:54:26 PM PDT 24
Finished Jun 28 05:54:33 PM PDT 24
Peak memory 194636 kb
Host smart-e2ab0d0c-37c4-456e-bfac-7dd342ffdfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484374381 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.hmac_intr_test.3484374381
Directory /workspace/22.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.hmac_intr_test.2954509693
Short name T795
Test name
Test status
Simulation time 48615574 ps
CPU time 0.59 seconds
Started Jun 28 05:54:31 PM PDT 24
Finished Jun 28 05:54:38 PM PDT 24
Peak memory 194644 kb
Host smart-a71e961d-6081-4319-9270-2843ffdfd6b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954509693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.hmac_intr_test.2954509693
Directory /workspace/23.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.hmac_intr_test.714009085
Short name T797
Test name
Test status
Simulation time 46056145 ps
CPU time 0.63 seconds
Started Jun 28 05:54:26 PM PDT 24
Finished Jun 28 05:54:33 PM PDT 24
Peak memory 194640 kb
Host smart-18ecafc2-7934-440a-948e-4ba1f6ab5d19
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714009085 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.hmac_intr_test.714009085
Directory /workspace/24.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.hmac_intr_test.3908397404
Short name T806
Test name
Test status
Simulation time 74101669 ps
CPU time 0.65 seconds
Started Jun 28 05:54:29 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 194908 kb
Host smart-011710a9-1a72-4eb4-bf40-a31df37bcff8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908397404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.hmac_intr_test.3908397404
Directory /workspace/25.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.hmac_intr_test.3551062095
Short name T802
Test name
Test status
Simulation time 12457697 ps
CPU time 0.66 seconds
Started Jun 28 05:54:27 PM PDT 24
Finished Jun 28 05:54:33 PM PDT 24
Peak memory 194628 kb
Host smart-af4d2c95-72b3-4de7-95dd-9531fe906bf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551062095 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.hmac_intr_test.3551062095
Directory /workspace/26.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.hmac_intr_test.3216306823
Short name T891
Test name
Test status
Simulation time 15320582 ps
CPU time 0.63 seconds
Started Jun 28 05:54:29 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 194752 kb
Host smart-21a0f15b-8219-44aa-b43d-7199b95b36ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216306823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.hmac_intr_test.3216306823
Directory /workspace/27.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.hmac_intr_test.659322454
Short name T892
Test name
Test status
Simulation time 34423087 ps
CPU time 0.63 seconds
Started Jun 28 05:54:37 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194580 kb
Host smart-59e572b0-65dd-4262-9a48-a91c9e5f7a63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659322454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.hmac_intr_test.659322454
Directory /workspace/28.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.hmac_intr_test.2610691891
Short name T835
Test name
Test status
Simulation time 47275242 ps
CPU time 0.63 seconds
Started Jun 28 05:54:30 PM PDT 24
Finished Jun 28 05:54:37 PM PDT 24
Peak memory 194672 kb
Host smart-b5dc74c8-85cb-4b26-893c-6dd4a1858eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610691891 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.hmac_intr_test.2610691891
Directory /workspace/29.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_aliasing.3851179633
Short name T825
Test name
Test status
Simulation time 227811252 ps
CPU time 3.16 seconds
Started Jun 28 05:53:51 PM PDT 24
Finished Jun 28 05:53:56 PM PDT 24
Peak memory 199720 kb
Host smart-7752976b-b0af-4e69-947f-f8934ac1467d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851179633 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_aliasing.3851179633
Directory /workspace/3.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_bit_bash.3283326882
Short name T866
Test name
Test status
Simulation time 548704970 ps
CPU time 6.36 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:54:00 PM PDT 24
Peak memory 199720 kb
Host smart-619b9a66-e511-4f5f-ade7-d7267e6a460f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283326882 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_bit_bash.3283326882
Directory /workspace/3.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_hw_reset.850193148
Short name T904
Test name
Test status
Simulation time 17911067 ps
CPU time 0.89 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:53:54 PM PDT 24
Peak memory 199224 kb
Host smart-3813d80e-60da-444a-8ee2-8a32881311d1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850193148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_hw_reset.850193148
Directory /workspace/3.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_mem_rw_with_rand_reset.95731294
Short name T68
Test name
Test status
Simulation time 217851099 ps
CPU time 1.76 seconds
Started Jun 28 05:53:54 PM PDT 24
Finished Jun 28 05:53:57 PM PDT 24
Peak memory 199908 kb
Host smart-5ad6384d-3baa-4a7f-b5ad-5271322c316e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95731294 -assert nopostproc +UVM_TESTNAME=h
mac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.hmac_csr_mem_rw_with_rand_reset.95731294
Directory /workspace/3.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_csr_rw.3425295573
Short name T863
Test name
Test status
Simulation time 28280726 ps
CPU time 0.86 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:53:55 PM PDT 24
Peak memory 198996 kb
Host smart-ae0e3f84-3072-424a-8979-4a62dd8b351f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425295573 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_csr_rw.3425295573
Directory /workspace/3.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_intr_test.4107512387
Short name T895
Test name
Test status
Simulation time 14997474 ps
CPU time 0.64 seconds
Started Jun 28 05:53:54 PM PDT 24
Finished Jun 28 05:53:57 PM PDT 24
Peak memory 194640 kb
Host smart-49d89f51-b230-4367-864e-962c904ddeba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107512387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_intr_test.4107512387
Directory /workspace/3.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_same_csr_outstanding.4090296127
Short name T883
Test name
Test status
Simulation time 112658683 ps
CPU time 2.28 seconds
Started Jun 28 05:53:53 PM PDT 24
Finished Jun 28 05:53:57 PM PDT 24
Peak memory 199852 kb
Host smart-cc36955b-7760-4673-9e98-4c0d89ba811a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090296127 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_same_csr
_outstanding.4090296127
Directory /workspace/3.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_errors.1265451844
Short name T874
Test name
Test status
Simulation time 97646801 ps
CPU time 2.19 seconds
Started Jun 28 05:53:51 PM PDT 24
Finished Jun 28 05:53:55 PM PDT 24
Peak memory 199788 kb
Host smart-747eb54d-a2b6-49b3-b478-6173a4ab31ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265451844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_errors.1265451844
Directory /workspace/3.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.hmac_tl_intg_err.227048767
Short name T64
Test name
Test status
Simulation time 174929752 ps
CPU time 1.8 seconds
Started Jun 28 05:53:55 PM PDT 24
Finished Jun 28 05:53:58 PM PDT 24
Peak memory 199852 kb
Host smart-80782f2c-8ee5-4e02-9c13-97b10f81ef13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227048767 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.hmac_tl_intg_err.227048767
Directory /workspace/3.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.hmac_intr_test.4234066291
Short name T887
Test name
Test status
Simulation time 11521942 ps
CPU time 0.66 seconds
Started Jun 28 05:54:28 PM PDT 24
Finished Jun 28 05:54:36 PM PDT 24
Peak memory 194568 kb
Host smart-b460f6a1-a883-4e7b-ab79-0c154afff21b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234066291 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.hmac_intr_test.4234066291
Directory /workspace/30.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.hmac_intr_test.3015578709
Short name T862
Test name
Test status
Simulation time 14495060 ps
CPU time 0.57 seconds
Started Jun 28 05:54:38 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194644 kb
Host smart-4a2bbe94-7824-4272-89f6-f29765cae674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015578709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.hmac_intr_test.3015578709
Directory /workspace/31.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.hmac_intr_test.3055457736
Short name T813
Test name
Test status
Simulation time 17635219 ps
CPU time 0.64 seconds
Started Jun 28 05:54:37 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194656 kb
Host smart-c73ba7cc-2bb8-447d-8cfe-3eba4b99444d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055457736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.hmac_intr_test.3055457736
Directory /workspace/32.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.hmac_intr_test.3750931787
Short name T849
Test name
Test status
Simulation time 55074668 ps
CPU time 0.62 seconds
Started Jun 28 05:54:41 PM PDT 24
Finished Jun 28 05:54:47 PM PDT 24
Peak memory 194972 kb
Host smart-a6af2e10-0e54-44b2-b661-6b8961b92e1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750931787 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.hmac_intr_test.3750931787
Directory /workspace/33.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.hmac_intr_test.3457283026
Short name T870
Test name
Test status
Simulation time 20876637 ps
CPU time 0.65 seconds
Started Jun 28 05:54:39 PM PDT 24
Finished Jun 28 05:54:47 PM PDT 24
Peak memory 194616 kb
Host smart-a597bd31-40ea-4f80-938b-1c4e00cc9843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457283026 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.hmac_intr_test.3457283026
Directory /workspace/34.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.hmac_intr_test.3100299964
Short name T798
Test name
Test status
Simulation time 61084808 ps
CPU time 0.63 seconds
Started Jun 28 05:54:42 PM PDT 24
Finished Jun 28 05:54:49 PM PDT 24
Peak memory 194632 kb
Host smart-86534a1a-ece5-4788-8e63-4a56b47ec834
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100299964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.hmac_intr_test.3100299964
Directory /workspace/35.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.hmac_intr_test.4253903479
Short name T872
Test name
Test status
Simulation time 18592231 ps
CPU time 0.65 seconds
Started Jun 28 05:54:37 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194564 kb
Host smart-16f706f5-abe9-420d-af01-e98e4e347282
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253903479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.hmac_intr_test.4253903479
Directory /workspace/36.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.hmac_intr_test.2256189065
Short name T864
Test name
Test status
Simulation time 51329688 ps
CPU time 0.61 seconds
Started Jun 28 05:54:38 PM PDT 24
Finished Jun 28 05:54:46 PM PDT 24
Peak memory 194664 kb
Host smart-1c39f602-55d6-4479-9014-6d94453f3264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256189065 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.hmac_intr_test.2256189065
Directory /workspace/37.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.hmac_intr_test.729054817
Short name T857
Test name
Test status
Simulation time 24229892 ps
CPU time 0.63 seconds
Started Jun 28 05:54:38 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194608 kb
Host smart-40fdf34d-1f85-4f1f-92fe-785ac1263054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729054817 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.hmac_intr_test.729054817
Directory /workspace/38.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.hmac_intr_test.166540864
Short name T842
Test name
Test status
Simulation time 46472822 ps
CPU time 0.64 seconds
Started Jun 28 05:54:38 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194644 kb
Host smart-a6512c00-edf8-4598-8d8d-320631ad60d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166540864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.hmac_intr_test.166540864
Directory /workspace/39.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_aliasing.2860918163
Short name T111
Test name
Test status
Simulation time 663473511 ps
CPU time 5.89 seconds
Started Jun 28 05:54:00 PM PDT 24
Finished Jun 28 05:54:09 PM PDT 24
Peak memory 199848 kb
Host smart-a2ffa3b4-c51a-4e37-9139-12c1936b9baa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860918163 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_aliasing.2860918163
Directory /workspace/4.hmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_bit_bash.3112334234
Short name T123
Test name
Test status
Simulation time 745828136 ps
CPU time 11.58 seconds
Started Jun 28 05:54:02 PM PDT 24
Finished Jun 28 05:54:17 PM PDT 24
Peak memory 199772 kb
Host smart-fd2d0591-ef51-41f3-903e-3bad92d7ed87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112334234 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_bit_bash.3112334234
Directory /workspace/4.hmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_hw_reset.2703216314
Short name T847
Test name
Test status
Simulation time 14203673 ps
CPU time 0.74 seconds
Started Jun 28 05:54:01 PM PDT 24
Finished Jun 28 05:54:05 PM PDT 24
Peak memory 197432 kb
Host smart-304141a6-da72-4cfb-bc7b-be33e19e320f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703216314 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_hw_reset.2703216314
Directory /workspace/4.hmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_mem_rw_with_rand_reset.1933644862
Short name T856
Test name
Test status
Simulation time 59255658 ps
CPU time 1.49 seconds
Started Jun 28 05:54:02 PM PDT 24
Finished Jun 28 05:54:07 PM PDT 24
Peak memory 199892 kb
Host smart-2aa8ef61-9d72-49e7-ad7c-fcff255c3863
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933644862 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.hmac_csr_mem_rw_with_rand_reset.1933644862
Directory /workspace/4.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_csr_rw.157736382
Short name T841
Test name
Test status
Simulation time 53949818 ps
CPU time 0.95 seconds
Started Jun 28 05:54:01 PM PDT 24
Finished Jun 28 05:54:05 PM PDT 24
Peak memory 199524 kb
Host smart-34dd1e9f-7675-41f9-a54c-66e1c2f0d80f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157736382 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_csr_rw.157736382
Directory /workspace/4.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_intr_test.1686100736
Short name T848
Test name
Test status
Simulation time 15450929 ps
CPU time 0.59 seconds
Started Jun 28 05:54:01 PM PDT 24
Finished Jun 28 05:54:05 PM PDT 24
Peak memory 194668 kb
Host smart-66dcae68-9a3f-4698-bcbb-9db027e7c9ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686100736 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_intr_test.1686100736
Directory /workspace/4.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_same_csr_outstanding.1131708427
Short name T899
Test name
Test status
Simulation time 87953646 ps
CPU time 1.1 seconds
Started Jun 28 05:54:03 PM PDT 24
Finished Jun 28 05:54:08 PM PDT 24
Peak memory 198376 kb
Host smart-ffded81d-8dcf-4f9a-92a8-de1160c649e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131708427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_same_csr
_outstanding.1131708427
Directory /workspace/4.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_errors.309568529
Short name T61
Test name
Test status
Simulation time 161284822 ps
CPU time 2.98 seconds
Started Jun 28 05:53:52 PM PDT 24
Finished Jun 28 05:53:56 PM PDT 24
Peak memory 199772 kb
Host smart-dcc2e6ed-0194-40b8-accb-5c5ecd6013f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309568529 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_errors.309568529
Directory /workspace/4.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.hmac_tl_intg_err.2765466953
Short name T882
Test name
Test status
Simulation time 671541594 ps
CPU time 5.01 seconds
Started Jun 28 05:53:51 PM PDT 24
Finished Jun 28 05:53:58 PM PDT 24
Peak memory 199884 kb
Host smart-67243d1b-e645-4f7b-8694-0b6bf73270e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765466953 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.hmac_tl_intg_err.2765466953
Directory /workspace/4.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.hmac_intr_test.2372927722
Short name T879
Test name
Test status
Simulation time 29097683 ps
CPU time 0.65 seconds
Started Jun 28 05:54:38 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194640 kb
Host smart-ed8fbae8-dfa0-4a93-88ff-d834e181b4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372927722 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.hmac_intr_test.2372927722
Directory /workspace/40.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.hmac_intr_test.3999941230
Short name T800
Test name
Test status
Simulation time 16923278 ps
CPU time 0.66 seconds
Started Jun 28 05:54:40 PM PDT 24
Finished Jun 28 05:54:47 PM PDT 24
Peak memory 194928 kb
Host smart-c2df81cf-8e4a-4731-a2f7-9272eb087dfc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999941230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.hmac_intr_test.3999941230
Directory /workspace/41.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.hmac_intr_test.2986764861
Short name T911
Test name
Test status
Simulation time 43946209 ps
CPU time 0.58 seconds
Started Jun 28 05:54:37 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194632 kb
Host smart-e0153c22-6f23-45ab-9323-ff748e857ace
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986764861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.hmac_intr_test.2986764861
Directory /workspace/42.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.hmac_intr_test.1099927239
Short name T796
Test name
Test status
Simulation time 41439764 ps
CPU time 0.58 seconds
Started Jun 28 05:54:37 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194576 kb
Host smart-2f9af977-deb4-45fa-8628-c92e3ced264e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099927239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.hmac_intr_test.1099927239
Directory /workspace/43.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.hmac_intr_test.3614922887
Short name T884
Test name
Test status
Simulation time 12318991 ps
CPU time 0.58 seconds
Started Jun 28 05:54:38 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194636 kb
Host smart-b6c369bb-802b-4047-9539-9d8b747049ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614922887 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.hmac_intr_test.3614922887
Directory /workspace/44.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.hmac_intr_test.2383694399
Short name T799
Test name
Test status
Simulation time 100668059 ps
CPU time 0.63 seconds
Started Jun 28 05:54:37 PM PDT 24
Finished Jun 28 05:54:45 PM PDT 24
Peak memory 194644 kb
Host smart-47ec12be-2e97-4757-b117-0d75eafa4ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383694399 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.hmac_intr_test.2383694399
Directory /workspace/45.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.hmac_intr_test.4256208991
Short name T803
Test name
Test status
Simulation time 18509271 ps
CPU time 0.65 seconds
Started Jun 28 05:54:38 PM PDT 24
Finished Jun 28 05:54:46 PM PDT 24
Peak memory 194704 kb
Host smart-20063cc9-5746-4405-b530-e95e8b2ce256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256208991 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.hmac_intr_test.4256208991
Directory /workspace/46.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.hmac_intr_test.4175990425
Short name T832
Test name
Test status
Simulation time 37250089 ps
CPU time 0.6 seconds
Started Jun 28 05:54:38 PM PDT 24
Finished Jun 28 05:54:46 PM PDT 24
Peak memory 194568 kb
Host smart-2b19ba81-e784-42bf-9897-550c483bddab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175990425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.hmac_intr_test.4175990425
Directory /workspace/47.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.hmac_intr_test.1492340970
Short name T794
Test name
Test status
Simulation time 34566279 ps
CPU time 0.58 seconds
Started Jun 28 05:54:36 PM PDT 24
Finished Jun 28 05:54:44 PM PDT 24
Peak memory 194692 kb
Host smart-30bcddd5-c5a6-4ccd-bd06-127cd82a7fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492340970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.hmac_intr_test.1492340970
Directory /workspace/48.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.hmac_intr_test.3886184099
Short name T836
Test name
Test status
Simulation time 66087810 ps
CPU time 0.58 seconds
Started Jun 28 05:54:38 PM PDT 24
Finished Jun 28 05:54:46 PM PDT 24
Peak memory 194636 kb
Host smart-9d86edaa-84d7-408b-977d-3e61555cea96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886184099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.hmac_intr_test.3886184099
Directory /workspace/49.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_mem_rw_with_rand_reset.448349361
Short name T822
Test name
Test status
Simulation time 133048802 ps
CPU time 2.31 seconds
Started Jun 28 05:54:00 PM PDT 24
Finished Jun 28 05:54:05 PM PDT 24
Peak memory 216184 kb
Host smart-f477866b-83f9-4614-a7b0-2e6bc5515a02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448349361 -assert nopostproc +UVM_TESTNAME=
hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.hmac_csr_mem_rw_with_rand_reset.448349361
Directory /workspace/5.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_csr_rw.2760640111
Short name T815
Test name
Test status
Simulation time 47702774 ps
CPU time 0.83 seconds
Started Jun 28 05:54:01 PM PDT 24
Finished Jun 28 05:54:05 PM PDT 24
Peak memory 199312 kb
Host smart-0ca665af-5755-48c5-9970-02aa4ff333c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760640111 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_csr_rw.2760640111
Directory /workspace/5.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_intr_test.2606993166
Short name T818
Test name
Test status
Simulation time 30253605 ps
CPU time 0.61 seconds
Started Jun 28 05:54:03 PM PDT 24
Finished Jun 28 05:54:08 PM PDT 24
Peak memory 194660 kb
Host smart-7559be49-eb91-43ad-b34b-9f1e07a1c7f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606993166 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_intr_test.2606993166
Directory /workspace/5.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_same_csr_outstanding.2755570982
Short name T846
Test name
Test status
Simulation time 590784132 ps
CPU time 2.06 seconds
Started Jun 28 05:54:01 PM PDT 24
Finished Jun 28 05:54:06 PM PDT 24
Peak memory 199804 kb
Host smart-c9cf888b-a75c-44b2-8898-41949668fe9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755570982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_same_csr
_outstanding.2755570982
Directory /workspace/5.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.hmac_tl_errors.1869203365
Short name T894
Test name
Test status
Simulation time 488674112 ps
CPU time 4.28 seconds
Started Jun 28 05:54:01 PM PDT 24
Finished Jun 28 05:54:08 PM PDT 24
Peak memory 199828 kb
Host smart-1980beaa-7ee3-4d7b-b606-1e078a736899
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869203365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.hmac_tl_errors.1869203365
Directory /workspace/5.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_mem_rw_with_rand_reset.1601730980
Short name T838
Test name
Test status
Simulation time 43820009 ps
CPU time 1.33 seconds
Started Jun 28 05:54:02 PM PDT 24
Finished Jun 28 05:54:06 PM PDT 24
Peak memory 199712 kb
Host smart-ee46986a-47f4-4d44-94fb-3871f0832182
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601730980 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.hmac_csr_mem_rw_with_rand_reset.1601730980
Directory /workspace/6.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_csr_rw.3761393099
Short name T876
Test name
Test status
Simulation time 111893469 ps
CPU time 0.88 seconds
Started Jun 28 05:54:02 PM PDT 24
Finished Jun 28 05:54:07 PM PDT 24
Peak memory 199588 kb
Host smart-6e97b38e-5309-4fc4-b22a-e8065481e4ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761393099 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_csr_rw.3761393099
Directory /workspace/6.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_intr_test.525830710
Short name T810
Test name
Test status
Simulation time 48471885 ps
CPU time 0.62 seconds
Started Jun 28 05:54:02 PM PDT 24
Finished Jun 28 05:54:05 PM PDT 24
Peak memory 194652 kb
Host smart-8eb5b97e-120e-4517-8799-c48b0c73be90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525830710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_intr_test.525830710
Directory /workspace/6.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_same_csr_outstanding.224374050
Short name T126
Test name
Test status
Simulation time 239753330 ps
CPU time 2.45 seconds
Started Jun 28 05:54:00 PM PDT 24
Finished Jun 28 05:54:06 PM PDT 24
Peak memory 200096 kb
Host smart-31a9480b-b703-46e3-85c7-fe2b21f73ed6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224374050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_same_csr_
outstanding.224374050
Directory /workspace/6.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.hmac_tl_errors.3242077165
Short name T905
Test name
Test status
Simulation time 834888405 ps
CPU time 4.62 seconds
Started Jun 28 05:54:00 PM PDT 24
Finished Jun 28 05:54:08 PM PDT 24
Peak memory 199788 kb
Host smart-1079a475-28c0-428d-8cbb-8b6fcefd194a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242077165 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.hmac_tl_errors.3242077165
Directory /workspace/6.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_mem_rw_with_rand_reset.1662451974
Short name T48
Test name
Test status
Simulation time 53147199 ps
CPU time 1.47 seconds
Started Jun 28 05:54:10 PM PDT 24
Finished Jun 28 05:54:15 PM PDT 24
Peak memory 199952 kb
Host smart-f6d632ba-aba0-499f-ab91-87afa7105fd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662451974 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.hmac_csr_mem_rw_with_rand_reset.1662451974
Directory /workspace/7.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_csr_rw.948222000
Short name T115
Test name
Test status
Simulation time 38225428 ps
CPU time 0.73 seconds
Started Jun 28 05:54:10 PM PDT 24
Finished Jun 28 05:54:15 PM PDT 24
Peak memory 197328 kb
Host smart-c89f6fd2-fbf1-4e16-9dce-d677f9f6756c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948222000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_csr_rw.948222000
Directory /workspace/7.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_intr_test.1602849535
Short name T907
Test name
Test status
Simulation time 136031155 ps
CPU time 0.61 seconds
Started Jun 28 05:54:11 PM PDT 24
Finished Jun 28 05:54:16 PM PDT 24
Peak memory 194556 kb
Host smart-c4ff467b-a8b6-4c03-9a2b-2a19ee27bd9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602849535 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_intr_test.1602849535
Directory /workspace/7.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_same_csr_outstanding.507417574
Short name T827
Test name
Test status
Simulation time 81449012 ps
CPU time 1.84 seconds
Started Jun 28 05:54:10 PM PDT 24
Finished Jun 28 05:54:17 PM PDT 24
Peak memory 199836 kb
Host smart-52c65807-57fe-4eef-9eda-e532b9663f17
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507417574 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_same_csr_
outstanding.507417574
Directory /workspace/7.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.hmac_tl_errors.936411970
Short name T869
Test name
Test status
Simulation time 62150096 ps
CPU time 1.64 seconds
Started Jun 28 05:54:12 PM PDT 24
Finished Jun 28 05:54:19 PM PDT 24
Peak memory 199780 kb
Host smart-825f83e6-2c6f-4003-bd63-56c217b29e89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936411970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.hmac_tl_errors.936411970
Directory /workspace/7.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_mem_rw_with_rand_reset.2174651883
Short name T830
Test name
Test status
Simulation time 308840287 ps
CPU time 1.8 seconds
Started Jun 28 05:54:11 PM PDT 24
Finished Jun 28 05:54:18 PM PDT 24
Peak memory 199956 kb
Host smart-7a5f1f4c-12a7-4daf-84dd-83e4d15f710b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174651883 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.hmac_csr_mem_rw_with_rand_reset.2174651883
Directory /workspace/8.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_csr_rw.1622871185
Short name T865
Test name
Test status
Simulation time 37952946 ps
CPU time 0.75 seconds
Started Jun 28 05:54:10 PM PDT 24
Finished Jun 28 05:54:16 PM PDT 24
Peak memory 197748 kb
Host smart-06728870-1339-4639-aed2-804f3e647ac5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622871185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_csr_rw.1622871185
Directory /workspace/8.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_intr_test.3220895840
Short name T839
Test name
Test status
Simulation time 17645327 ps
CPU time 0.71 seconds
Started Jun 28 05:54:10 PM PDT 24
Finished Jun 28 05:54:15 PM PDT 24
Peak memory 194636 kb
Host smart-5f9cb98c-7acf-4ce3-b000-0d18ce5cf5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220895840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_intr_test.3220895840
Directory /workspace/8.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_same_csr_outstanding.2846371034
Short name T906
Test name
Test status
Simulation time 74585842 ps
CPU time 1.14 seconds
Started Jun 28 05:54:11 PM PDT 24
Finished Jun 28 05:54:17 PM PDT 24
Peak memory 199604 kb
Host smart-2247e37e-2275-4de2-bfc8-c5cd580e6b39
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846371034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_same_csr
_outstanding.2846371034
Directory /workspace/8.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_errors.2455402122
Short name T850
Test name
Test status
Simulation time 52251140 ps
CPU time 2.64 seconds
Started Jun 28 05:54:10 PM PDT 24
Finished Jun 28 05:54:18 PM PDT 24
Peak memory 199832 kb
Host smart-fdd0fdbc-a5e1-4d76-a56a-e194ecb3b6d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455402122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_errors.2455402122
Directory /workspace/8.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.hmac_tl_intg_err.4105725621
Short name T60
Test name
Test status
Simulation time 957728709 ps
CPU time 4.43 seconds
Started Jun 28 05:54:10 PM PDT 24
Finished Jun 28 05:54:19 PM PDT 24
Peak memory 199848 kb
Host smart-f8d2946c-cbcc-448d-9207-fc9aac67f4be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105725621 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.hmac_tl_intg_err.4105725621
Directory /workspace/8.hmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_mem_rw_with_rand_reset.4242735768
Short name T820
Test name
Test status
Simulation time 89980660 ps
CPU time 1.4 seconds
Started Jun 28 05:54:11 PM PDT 24
Finished Jun 28 05:54:18 PM PDT 24
Peak memory 199896 kb
Host smart-20bf7e8c-ae3c-4723-a28c-2f7c3e2dedcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242735768 -assert nopostproc +UVM_TESTNAME
=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.hmac_csr_mem_rw_with_rand_reset.4242735768
Directory /workspace/9.hmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_csr_rw.1784715544
Short name T821
Test name
Test status
Simulation time 240685663 ps
CPU time 0.98 seconds
Started Jun 28 05:54:09 PM PDT 24
Finished Jun 28 05:54:14 PM PDT 24
Peak memory 199556 kb
Host smart-c71f2d40-df9e-4b0d-be3b-8f84276cfcff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784715544 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_csr_rw.1784715544
Directory /workspace/9.hmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_intr_test.2069695412
Short name T902
Test name
Test status
Simulation time 14666288 ps
CPU time 0.65 seconds
Started Jun 28 05:54:10 PM PDT 24
Finished Jun 28 05:54:15 PM PDT 24
Peak memory 194648 kb
Host smart-c57db3f3-6910-4507-8b1e-bb8dde1887ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069695412 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_intr_test.2069695412
Directory /workspace/9.hmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_same_csr_outstanding.3502688114
Short name T896
Test name
Test status
Simulation time 121259499 ps
CPU time 2.39 seconds
Started Jun 28 05:54:10 PM PDT 24
Finished Jun 28 05:54:17 PM PDT 24
Peak memory 199840 kb
Host smart-6959a0f4-8833-4791-a3a2-6c7331c30316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502688114 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_same_csr
_outstanding.3502688114
Directory /workspace/9.hmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_errors.722852491
Short name T812
Test name
Test status
Simulation time 78648872 ps
CPU time 4.16 seconds
Started Jun 28 05:54:13 PM PDT 24
Finished Jun 28 05:54:22 PM PDT 24
Peak memory 199780 kb
Host smart-5db10041-fed5-4f7a-8e10-130978d5b7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722852491 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_errors.722852491
Directory /workspace/9.hmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.hmac_tl_intg_err.1990003952
Short name T153
Test name
Test status
Simulation time 681307425 ps
CPU time 1.94 seconds
Started Jun 28 05:54:12 PM PDT 24
Finished Jun 28 05:54:19 PM PDT 24
Peak memory 199900 kb
Host smart-e3aa9516-0046-43f3-ac6f-0b7480f953b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990003952 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.hmac_tl_intg_err.1990003952
Directory /workspace/9.hmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.hmac_alert_test.505899377
Short name T609
Test name
Test status
Simulation time 23467061 ps
CPU time 0.59 seconds
Started Jun 28 04:59:54 PM PDT 24
Finished Jun 28 04:59:56 PM PDT 24
Peak memory 195816 kb
Host smart-1711f92d-ddcd-40d1-af81-d5caee2dd5f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505899377 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_alert_test.505899377
Directory /workspace/0.hmac_alert_test/latest

Test location /workspace/coverage/default/0.hmac_back_pressure.106049712
Short name T493
Test name
Test status
Simulation time 95268133 ps
CPU time 4.45 seconds
Started Jun 28 04:59:45 PM PDT 24
Finished Jun 28 04:59:50 PM PDT 24
Peak memory 200268 kb
Host smart-1d4e72cb-97cc-4e93-8fe9-4823a14590d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=106049712 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_back_pressure.106049712
Directory /workspace/0.hmac_back_pressure/latest

Test location /workspace/coverage/default/0.hmac_burst_wr.2266300039
Short name T38
Test name
Test status
Simulation time 8880089999 ps
CPU time 44.82 seconds
Started Jun 28 04:59:54 PM PDT 24
Finished Jun 28 05:00:40 PM PDT 24
Peak memory 200364 kb
Host smart-da404e86-d63e-40c9-8dc4-97fd007161e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266300039 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_burst_wr.2266300039
Directory /workspace/0.hmac_burst_wr/latest

Test location /workspace/coverage/default/0.hmac_error.2790975021
Short name T604
Test name
Test status
Simulation time 8407944632 ps
CPU time 30.15 seconds
Started Jun 28 04:59:56 PM PDT 24
Finished Jun 28 05:00:28 PM PDT 24
Peak memory 200252 kb
Host smart-fecfdcc9-107b-4509-902b-d65bbaf97ffc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790975021 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_error.2790975021
Directory /workspace/0.hmac_error/latest

Test location /workspace/coverage/default/0.hmac_long_msg.2111981249
Short name T173
Test name
Test status
Simulation time 11377817034 ps
CPU time 64.71 seconds
Started Jun 28 04:59:47 PM PDT 24
Finished Jun 28 05:00:53 PM PDT 24
Peak memory 216700 kb
Host smart-f666aa9b-2e03-4aaa-bdee-cecfb2186e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111981249 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_long_msg.2111981249
Directory /workspace/0.hmac_long_msg/latest

Test location /workspace/coverage/default/0.hmac_sec_cm.1976728816
Short name T52
Test name
Test status
Simulation time 302275222 ps
CPU time 0.85 seconds
Started Jun 28 04:59:55 PM PDT 24
Finished Jun 28 04:59:57 PM PDT 24
Peak memory 218644 kb
Host smart-273fded3-6441-4c0e-9b76-0f0b0994ff30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976728816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_sec_cm.1976728816
Directory /workspace/0.hmac_sec_cm/latest

Test location /workspace/coverage/default/0.hmac_smoke.2350543684
Short name T220
Test name
Test status
Simulation time 80319200 ps
CPU time 3.67 seconds
Started Jun 28 04:59:44 PM PDT 24
Finished Jun 28 04:59:48 PM PDT 24
Peak memory 200312 kb
Host smart-b2c59977-deb5-4d44-a60b-e249f2b35bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350543684 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_smoke.2350543684
Directory /workspace/0.hmac_smoke/latest

Test location /workspace/coverage/default/0.hmac_stress_all.3585154826
Short name T684
Test name
Test status
Simulation time 43550662149 ps
CPU time 1865.14 seconds
Started Jun 28 05:00:00 PM PDT 24
Finished Jun 28 05:31:06 PM PDT 24
Peak memory 216708 kb
Host smart-a0eeb4bb-76bb-4cfd-9ada-608e709a9b65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585154826 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.hmac_stress_all.3585154826
Directory /workspace/0.hmac_stress_all/latest

Test location /workspace/coverage/default/0.hmac_test_hmac256_vectors.90026395
Short name T309
Test name
Test status
Simulation time 5437788365 ps
CPU time 52.21 seconds
Started Jun 28 04:59:56 PM PDT 24
Finished Jun 28 05:00:50 PM PDT 24
Peak memory 200328 kb
Host smart-1df16f35-a38d-4ed5-b956-53c1075e145b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=90026395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac256_vectors.90026395
Directory /workspace/0.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac384_vectors.1083331611
Short name T692
Test name
Test status
Simulation time 13637452473 ps
CPU time 86.7 seconds
Started Jun 28 04:59:54 PM PDT 24
Finished Jun 28 05:01:22 PM PDT 24
Peak memory 200288 kb
Host smart-c5f04e98-baab-4a45-b8bd-63ccbf3abaf8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1083331611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac384_vectors.1083331611
Directory /workspace/0.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_hmac512_vectors.1735252836
Short name T700
Test name
Test status
Simulation time 13748131011 ps
CPU time 109.08 seconds
Started Jun 28 04:59:59 PM PDT 24
Finished Jun 28 05:01:49 PM PDT 24
Peak memory 200252 kb
Host smart-3f0e0425-02d5-4bde-913b-852aec1b39ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1735252836 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_hmac512_vectors.1735252836
Directory /workspace/0.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha256_vectors.3852266541
Short name T80
Test name
Test status
Simulation time 104997495741 ps
CPU time 501.17 seconds
Started Jun 28 04:59:56 PM PDT 24
Finished Jun 28 05:08:19 PM PDT 24
Peak memory 200276 kb
Host smart-78b1eb75-ee30-404b-9325-2a0b60f0ec54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3852266541 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha256_vectors.3852266541
Directory /workspace/0.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha384_vectors.1142036860
Short name T786
Test name
Test status
Simulation time 752532949624 ps
CPU time 1845.18 seconds
Started Jun 28 04:59:56 PM PDT 24
Finished Jun 28 05:30:43 PM PDT 24
Peak memory 215088 kb
Host smart-50986939-387f-44fe-bbc9-36d9a47ec9a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1142036860 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha384_vectors.1142036860
Directory /workspace/0.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/0.hmac_test_sha512_vectors.542115476
Short name T652
Test name
Test status
Simulation time 462012138329 ps
CPU time 2085.42 seconds
Started Jun 28 04:59:56 PM PDT 24
Finished Jun 28 05:34:43 PM PDT 24
Peak memory 216676 kb
Host smart-e0f91e56-d028-4475-96be-b985632284e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=542115476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_test_sha512_vectors.542115476
Directory /workspace/0.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/0.hmac_wipe_secret.3194674877
Short name T741
Test name
Test status
Simulation time 5804206406 ps
CPU time 29.68 seconds
Started Jun 28 04:59:55 PM PDT 24
Finished Jun 28 05:00:26 PM PDT 24
Peak memory 200304 kb
Host smart-0df306ce-207b-4926-9068-e71df0016952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194674877 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.hmac_wipe_secret.3194674877
Directory /workspace/0.hmac_wipe_secret/latest

Test location /workspace/coverage/default/1.hmac_alert_test.416782352
Short name T364
Test name
Test status
Simulation time 46568350 ps
CPU time 0.56 seconds
Started Jun 28 05:00:00 PM PDT 24
Finished Jun 28 05:00:01 PM PDT 24
Peak memory 195216 kb
Host smart-de1239a1-74c7-4745-a4d8-731ffa461baf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416782352 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_alert_test.416782352
Directory /workspace/1.hmac_alert_test/latest

Test location /workspace/coverage/default/1.hmac_back_pressure.4040736499
Short name T778
Test name
Test status
Simulation time 4063527580 ps
CPU time 49.69 seconds
Started Jun 28 04:59:57 PM PDT 24
Finished Jun 28 05:00:48 PM PDT 24
Peak memory 200344 kb
Host smart-06ea2280-a80d-4d4b-95e0-62f937247c9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040736499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_back_pressure.4040736499
Directory /workspace/1.hmac_back_pressure/latest

Test location /workspace/coverage/default/1.hmac_burst_wr.3284512482
Short name T729
Test name
Test status
Simulation time 7047557071 ps
CPU time 33.62 seconds
Started Jun 28 04:59:56 PM PDT 24
Finished Jun 28 05:00:31 PM PDT 24
Peak memory 200372 kb
Host smart-23d0af1d-7e30-4c03-962c-51c8859e9fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284512482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_burst_wr.3284512482
Directory /workspace/1.hmac_burst_wr/latest

Test location /workspace/coverage/default/1.hmac_datapath_stress.3301934232
Short name T496
Test name
Test status
Simulation time 3589895925 ps
CPU time 847.96 seconds
Started Jun 28 04:59:58 PM PDT 24
Finished Jun 28 05:14:07 PM PDT 24
Peak memory 719064 kb
Host smart-d921c883-51b1-4306-92c9-0d7821653239
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3301934232 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_datapath_stress.3301934232
Directory /workspace/1.hmac_datapath_stress/latest

Test location /workspace/coverage/default/1.hmac_error.3929959047
Short name T269
Test name
Test status
Simulation time 8338612762 ps
CPU time 80.58 seconds
Started Jun 28 04:59:53 PM PDT 24
Finished Jun 28 05:01:14 PM PDT 24
Peak memory 200332 kb
Host smart-348b2dd5-b944-4e0b-87b9-ecdb26a5a2ce
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929959047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_error.3929959047
Directory /workspace/1.hmac_error/latest

Test location /workspace/coverage/default/1.hmac_long_msg.657563819
Short name T324
Test name
Test status
Simulation time 11216184466 ps
CPU time 105.85 seconds
Started Jun 28 04:59:58 PM PDT 24
Finished Jun 28 05:01:45 PM PDT 24
Peak memory 216540 kb
Host smart-9ae8532c-a70a-45d8-94c7-869ddc410782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657563819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_long_msg.657563819
Directory /workspace/1.hmac_long_msg/latest

Test location /workspace/coverage/default/1.hmac_sec_cm.4264079384
Short name T49
Test name
Test status
Simulation time 37049291 ps
CPU time 0.82 seconds
Started Jun 28 04:59:58 PM PDT 24
Finished Jun 28 05:00:00 PM PDT 24
Peak memory 218536 kb
Host smart-758c424d-d9ae-433b-9c11-e77edb15c9b3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264079384 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_sec_cm.4264079384
Directory /workspace/1.hmac_sec_cm/latest

Test location /workspace/coverage/default/1.hmac_smoke.1612083416
Short name T193
Test name
Test status
Simulation time 325101795 ps
CPU time 5.19 seconds
Started Jun 28 04:59:57 PM PDT 24
Finished Jun 28 05:00:04 PM PDT 24
Peak memory 200232 kb
Host smart-99b07759-45b2-4788-84a8-6e0307848102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612083416 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_smoke.1612083416
Directory /workspace/1.hmac_smoke/latest

Test location /workspace/coverage/default/1.hmac_test_hmac256_vectors.4065174043
Short name T399
Test name
Test status
Simulation time 30816875554 ps
CPU time 60.91 seconds
Started Jun 28 04:59:55 PM PDT 24
Finished Jun 28 05:00:58 PM PDT 24
Peak memory 200268 kb
Host smart-1e8bce89-ed3e-4870-9bfe-8b60613f125c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4065174043 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac256_vectors.4065174043
Directory /workspace/1.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac384_vectors.726418250
Short name T357
Test name
Test status
Simulation time 4493528777 ps
CPU time 84.72 seconds
Started Jun 28 04:59:59 PM PDT 24
Finished Jun 28 05:01:24 PM PDT 24
Peak memory 200324 kb
Host smart-b40ee40e-f027-4144-a836-8f18db474f6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=726418250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac384_vectors.726418250
Directory /workspace/1.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_hmac512_vectors.2087312560
Short name T238
Test name
Test status
Simulation time 7918722629 ps
CPU time 55.25 seconds
Started Jun 28 04:59:55 PM PDT 24
Finished Jun 28 05:00:52 PM PDT 24
Peak memory 200300 kb
Host smart-fae16bdd-4281-4ec5-8c7c-d63a3e8f1ba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2087312560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_hmac512_vectors.2087312560
Directory /workspace/1.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha256_vectors.1009045170
Short name T39
Test name
Test status
Simulation time 175671860752 ps
CPU time 557.18 seconds
Started Jun 28 04:59:58 PM PDT 24
Finished Jun 28 05:09:16 PM PDT 24
Peak memory 200292 kb
Host smart-f83648c2-8fd2-436f-afd8-b043e6d90d52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1009045170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha256_vectors.1009045170
Directory /workspace/1.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha384_vectors.1362802167
Short name T166
Test name
Test status
Simulation time 118428762769 ps
CPU time 2120.01 seconds
Started Jun 28 04:59:59 PM PDT 24
Finished Jun 28 05:35:20 PM PDT 24
Peak memory 216464 kb
Host smart-70fb2d51-e9c0-4fcd-b80a-3bc77f024dcc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1362802167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha384_vectors.1362802167
Directory /workspace/1.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/1.hmac_test_sha512_vectors.4089009652
Short name T459
Test name
Test status
Simulation time 161789686158 ps
CPU time 2068.42 seconds
Started Jun 28 04:59:54 PM PDT 24
Finished Jun 28 05:34:23 PM PDT 24
Peak memory 215716 kb
Host smart-9358bcfc-8bd1-4acb-80a5-4ddc7fd3a2ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4089009652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_test_sha512_vectors.4089009652
Directory /workspace/1.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/1.hmac_wipe_secret.3738524694
Short name T183
Test name
Test status
Simulation time 2781349517 ps
CPU time 55.09 seconds
Started Jun 28 04:59:59 PM PDT 24
Finished Jun 28 05:00:55 PM PDT 24
Peak memory 200200 kb
Host smart-1162a6e4-9573-44d1-a9a9-6baa30c94ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738524694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.hmac_wipe_secret.3738524694
Directory /workspace/1.hmac_wipe_secret/latest

Test location /workspace/coverage/default/10.hmac_alert_test.3688257710
Short name T77
Test name
Test status
Simulation time 12120973 ps
CPU time 0.58 seconds
Started Jun 28 05:00:49 PM PDT 24
Finished Jun 28 05:00:50 PM PDT 24
Peak memory 196864 kb
Host smart-5d0af7df-1701-4778-a0b4-7870296e8b6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688257710 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_alert_test.3688257710
Directory /workspace/10.hmac_alert_test/latest

Test location /workspace/coverage/default/10.hmac_burst_wr.2193217108
Short name T253
Test name
Test status
Simulation time 3312664879 ps
CPU time 57.96 seconds
Started Jun 28 05:00:44 PM PDT 24
Finished Jun 28 05:01:43 PM PDT 24
Peak memory 200320 kb
Host smart-dc782691-2e3b-4564-8f0c-7bbd312d5a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193217108 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_burst_wr.2193217108
Directory /workspace/10.hmac_burst_wr/latest

Test location /workspace/coverage/default/10.hmac_datapath_stress.2975941941
Short name T98
Test name
Test status
Simulation time 3384367568 ps
CPU time 179.18 seconds
Started Jun 28 05:00:50 PM PDT 24
Finished Jun 28 05:03:49 PM PDT 24
Peak memory 643708 kb
Host smart-c9adbe99-6edf-4bdf-a59f-b803ec600890
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2975941941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_datapath_stress.2975941941
Directory /workspace/10.hmac_datapath_stress/latest

Test location /workspace/coverage/default/10.hmac_error.1340198110
Short name T205
Test name
Test status
Simulation time 2251908962 ps
CPU time 131.01 seconds
Started Jun 28 05:00:50 PM PDT 24
Finished Jun 28 05:03:01 PM PDT 24
Peak memory 200356 kb
Host smart-7b9e3403-4c74-48f9-b6eb-9c0935b616e5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340198110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_error.1340198110
Directory /workspace/10.hmac_error/latest

Test location /workspace/coverage/default/10.hmac_long_msg.3360697488
Short name T659
Test name
Test status
Simulation time 15217546070 ps
CPU time 43.78 seconds
Started Jun 28 05:00:54 PM PDT 24
Finished Jun 28 05:01:38 PM PDT 24
Peak memory 200256 kb
Host smart-69cfddef-0895-49c5-81ef-421678450b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360697488 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_long_msg.3360697488
Directory /workspace/10.hmac_long_msg/latest

Test location /workspace/coverage/default/10.hmac_smoke.3165918159
Short name T7
Test name
Test status
Simulation time 951088240 ps
CPU time 4.28 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 05:00:51 PM PDT 24
Peak memory 200336 kb
Host smart-60a8e4ab-86c2-4acd-804e-4d83dd06b11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165918159 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_smoke.3165918159
Directory /workspace/10.hmac_smoke/latest

Test location /workspace/coverage/default/10.hmac_stress_all.531799065
Short name T92
Test name
Test status
Simulation time 930884530968 ps
CPU time 5755.04 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 06:36:43 PM PDT 24
Peak memory 216752 kb
Host smart-ffff53cb-9537-4116-8e3b-af5d6b054e92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531799065 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.hmac_stress_all.531799065
Directory /workspace/10.hmac_stress_all/latest

Test location /workspace/coverage/default/10.hmac_test_hmac256_vectors.4197227309
Short name T488
Test name
Test status
Simulation time 5440927779 ps
CPU time 57.65 seconds
Started Jun 28 05:00:45 PM PDT 24
Finished Jun 28 05:01:44 PM PDT 24
Peak memory 200328 kb
Host smart-0799590a-b33e-43f6-80f2-13906bdefb6a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4197227309 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac256_vectors.4197227309
Directory /workspace/10.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_hmac384_vectors.4280223857
Short name T705
Test name
Test status
Simulation time 39527045183 ps
CPU time 44.17 seconds
Started Jun 28 05:00:47 PM PDT 24
Finished Jun 28 05:01:32 PM PDT 24
Peak memory 200312 kb
Host smart-6e07c367-8621-4a68-bbed-747f4a7f5563
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4280223857 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac384_vectors.4280223857
Directory /workspace/10.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_hmac512_vectors.3712341963
Short name T371
Test name
Test status
Simulation time 40932094461 ps
CPU time 115.86 seconds
Started Jun 28 05:00:45 PM PDT 24
Finished Jun 28 05:02:41 PM PDT 24
Peak memory 200360 kb
Host smart-d5a540e0-863c-4662-b061-62cea8693bb6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3712341963 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_hmac512_vectors.3712341963
Directory /workspace/10.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha256_vectors.1781729689
Short name T554
Test name
Test status
Simulation time 421166027289 ps
CPU time 439.15 seconds
Started Jun 28 05:00:47 PM PDT 24
Finished Jun 28 05:08:07 PM PDT 24
Peak memory 200232 kb
Host smart-3becbafa-8325-4b9e-a749-89e0d0b29538
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1781729689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha256_vectors.1781729689
Directory /workspace/10.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha384_vectors.3651716856
Short name T312
Test name
Test status
Simulation time 107276652555 ps
CPU time 1852.48 seconds
Started Jun 28 05:00:45 PM PDT 24
Finished Jun 28 05:31:39 PM PDT 24
Peak memory 216676 kb
Host smart-f7345a67-284d-4e08-a755-b581bb3a61b0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3651716856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha384_vectors.3651716856
Directory /workspace/10.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/10.hmac_test_sha512_vectors.3903258348
Short name T296
Test name
Test status
Simulation time 32143372838 ps
CPU time 1828.03 seconds
Started Jun 28 05:00:49 PM PDT 24
Finished Jun 28 05:31:17 PM PDT 24
Peak memory 215748 kb
Host smart-31c7858e-82b1-41b2-bc16-e6f1c76d33e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3903258348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_test_sha512_vectors.3903258348
Directory /workspace/10.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/10.hmac_wipe_secret.2189897327
Short name T204
Test name
Test status
Simulation time 2272582251 ps
CPU time 49.23 seconds
Started Jun 28 05:00:47 PM PDT 24
Finished Jun 28 05:01:38 PM PDT 24
Peak memory 200376 kb
Host smart-9fd8be3d-6895-4695-9073-16dbc497484c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189897327 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.hmac_wipe_secret.2189897327
Directory /workspace/10.hmac_wipe_secret/latest

Test location /workspace/coverage/default/11.hmac_back_pressure.516743594
Short name T506
Test name
Test status
Simulation time 1286775717 ps
CPU time 29.88 seconds
Started Jun 28 05:00:48 PM PDT 24
Finished Jun 28 05:01:19 PM PDT 24
Peak memory 200168 kb
Host smart-313fb513-1ec3-4e3d-bdeb-c5bb962189c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=516743594 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_back_pressure.516743594
Directory /workspace/11.hmac_back_pressure/latest

Test location /workspace/coverage/default/11.hmac_burst_wr.3852782807
Short name T433
Test name
Test status
Simulation time 2671025929 ps
CPU time 35.93 seconds
Started Jun 28 05:00:47 PM PDT 24
Finished Jun 28 05:01:24 PM PDT 24
Peak memory 200340 kb
Host smart-b26d1508-32bd-4e37-9771-3cbf48d93050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852782807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_burst_wr.3852782807
Directory /workspace/11.hmac_burst_wr/latest

Test location /workspace/coverage/default/11.hmac_datapath_stress.2360158533
Short name T513
Test name
Test status
Simulation time 5078217555 ps
CPU time 288.23 seconds
Started Jun 28 05:00:54 PM PDT 24
Finished Jun 28 05:05:43 PM PDT 24
Peak memory 443804 kb
Host smart-563f18c4-c59f-4f4d-b522-231e6bc26cd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2360158533 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_datapath_stress.2360158533
Directory /workspace/11.hmac_datapath_stress/latest

Test location /workspace/coverage/default/11.hmac_error.1924787735
Short name T310
Test name
Test status
Simulation time 12533192450 ps
CPU time 161.47 seconds
Started Jun 28 05:00:49 PM PDT 24
Finished Jun 28 05:03:31 PM PDT 24
Peak memory 200132 kb
Host smart-45f7aea9-dd40-4f48-ba26-a7aabe7e2644
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924787735 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_error.1924787735
Directory /workspace/11.hmac_error/latest

Test location /workspace/coverage/default/11.hmac_long_msg.2250686789
Short name T525
Test name
Test status
Simulation time 12535769710 ps
CPU time 62.08 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 05:01:49 PM PDT 24
Peak memory 200388 kb
Host smart-750d8b01-15f6-44ca-bb9f-f28166a4a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250686789 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_long_msg.2250686789
Directory /workspace/11.hmac_long_msg/latest

Test location /workspace/coverage/default/11.hmac_smoke.3844997896
Short name T580
Test name
Test status
Simulation time 409168484 ps
CPU time 3.71 seconds
Started Jun 28 05:00:44 PM PDT 24
Finished Jun 28 05:00:48 PM PDT 24
Peak memory 200292 kb
Host smart-6d25f58c-6daa-42f1-8bd9-a7e00201903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844997896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_smoke.3844997896
Directory /workspace/11.hmac_smoke/latest

Test location /workspace/coverage/default/11.hmac_stress_all.2376585708
Short name T24
Test name
Test status
Simulation time 59197657040 ps
CPU time 1759.35 seconds
Started Jun 28 05:00:52 PM PDT 24
Finished Jun 28 05:30:13 PM PDT 24
Peak memory 676040 kb
Host smart-55909f4b-43d6-4e4e-9be2-b19f80a2fa7d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376585708 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.hmac_stress_all.2376585708
Directory /workspace/11.hmac_stress_all/latest

Test location /workspace/coverage/default/11.hmac_test_hmac256_vectors.3910630645
Short name T181
Test name
Test status
Simulation time 7126546890 ps
CPU time 53.14 seconds
Started Jun 28 05:00:45 PM PDT 24
Finished Jun 28 05:01:39 PM PDT 24
Peak memory 200316 kb
Host smart-cbf367f5-c095-49e6-8b8b-e9db8c48d926
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3910630645 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac256_vectors.3910630645
Directory /workspace/11.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_hmac384_vectors.2780432013
Short name T689
Test name
Test status
Simulation time 5761676724 ps
CPU time 90.49 seconds
Started Jun 28 05:00:52 PM PDT 24
Finished Jun 28 05:02:23 PM PDT 24
Peak memory 200288 kb
Host smart-015d9fd6-da9e-4ffe-9ea7-f95b08f44d5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2780432013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac384_vectors.2780432013
Directory /workspace/11.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_hmac512_vectors.1908898809
Short name T671
Test name
Test status
Simulation time 26066898458 ps
CPU time 63.41 seconds
Started Jun 28 05:00:45 PM PDT 24
Finished Jun 28 05:01:49 PM PDT 24
Peak memory 200300 kb
Host smart-d2eac6e2-6244-443e-a9bf-99c3ef6a1d64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1908898809 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_hmac512_vectors.1908898809
Directory /workspace/11.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha256_vectors.2027037935
Short name T618
Test name
Test status
Simulation time 114144443705 ps
CPU time 538.23 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 05:09:45 PM PDT 24
Peak memory 200248 kb
Host smart-1e473457-a7ae-40e7-aba1-a68cd840b1d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2027037935 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha256_vectors.2027037935
Directory /workspace/11.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha384_vectors.1040205780
Short name T387
Test name
Test status
Simulation time 113927506497 ps
CPU time 2035.89 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 05:34:43 PM PDT 24
Peak memory 215808 kb
Host smart-a5223c6f-d0b1-45fb-a4b7-33849aae87b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1040205780 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha384_vectors.1040205780
Directory /workspace/11.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/11.hmac_test_sha512_vectors.255367348
Short name T583
Test name
Test status
Simulation time 61516566262 ps
CPU time 1727.43 seconds
Started Jun 28 05:00:48 PM PDT 24
Finished Jun 28 05:29:36 PM PDT 24
Peak memory 215772 kb
Host smart-18436023-8163-46dc-9645-19ef3772d8ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=255367348 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_test_sha512_vectors.255367348
Directory /workspace/11.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/11.hmac_wipe_secret.196593465
Short name T403
Test name
Test status
Simulation time 11341515335 ps
CPU time 71.07 seconds
Started Jun 28 05:00:47 PM PDT 24
Finished Jun 28 05:01:59 PM PDT 24
Peak memory 200296 kb
Host smart-9c5b94a8-ecd0-4ba8-bdb5-1eff005ab702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196593465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.hmac_wipe_secret.196593465
Directory /workspace/11.hmac_wipe_secret/latest

Test location /workspace/coverage/default/12.hmac_alert_test.4116272531
Short name T664
Test name
Test status
Simulation time 13114778 ps
CPU time 0.6 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 05:00:47 PM PDT 24
Peak memory 196264 kb
Host smart-6526017a-1911-4384-b985-6129a408490f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116272531 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_alert_test.4116272531
Directory /workspace/12.hmac_alert_test/latest

Test location /workspace/coverage/default/12.hmac_back_pressure.2006971089
Short name T773
Test name
Test status
Simulation time 141181724 ps
CPU time 6.71 seconds
Started Jun 28 05:00:52 PM PDT 24
Finished Jun 28 05:00:59 PM PDT 24
Peak memory 200188 kb
Host smart-7662cfbd-276d-4595-b7d0-2b96664ae256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2006971089 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_back_pressure.2006971089
Directory /workspace/12.hmac_back_pressure/latest

Test location /workspace/coverage/default/12.hmac_burst_wr.1362851506
Short name T321
Test name
Test status
Simulation time 3119290575 ps
CPU time 42.93 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 05:01:30 PM PDT 24
Peak memory 200244 kb
Host smart-90094d48-59a0-4b13-8561-b10c3c7d35df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362851506 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_burst_wr.1362851506
Directory /workspace/12.hmac_burst_wr/latest

Test location /workspace/coverage/default/12.hmac_datapath_stress.4089777653
Short name T523
Test name
Test status
Simulation time 4007703549 ps
CPU time 1190.5 seconds
Started Jun 28 05:00:53 PM PDT 24
Finished Jun 28 05:20:45 PM PDT 24
Peak memory 764324 kb
Host smart-d8d0e712-e3b5-4cd4-a0a2-f23f87c76b8f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4089777653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_datapath_stress.4089777653
Directory /workspace/12.hmac_datapath_stress/latest

Test location /workspace/coverage/default/12.hmac_error.3178918730
Short name T576
Test name
Test status
Simulation time 1656763058 ps
CPU time 91.83 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 05:02:19 PM PDT 24
Peak memory 200196 kb
Host smart-2a420847-606b-4e09-aba8-e08af28dd8a1
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178918730 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_error.3178918730
Directory /workspace/12.hmac_error/latest

Test location /workspace/coverage/default/12.hmac_long_msg.3670375884
Short name T217
Test name
Test status
Simulation time 3046175493 ps
CPU time 58.32 seconds
Started Jun 28 05:00:49 PM PDT 24
Finished Jun 28 05:01:47 PM PDT 24
Peak memory 200200 kb
Host smart-61283c38-f744-41f5-8cf4-c379aed83a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670375884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_long_msg.3670375884
Directory /workspace/12.hmac_long_msg/latest

Test location /workspace/coverage/default/12.hmac_smoke.4184703300
Short name T1
Test name
Test status
Simulation time 342076251 ps
CPU time 5.96 seconds
Started Jun 28 05:00:52 PM PDT 24
Finished Jun 28 05:00:59 PM PDT 24
Peak memory 200208 kb
Host smart-446d5718-573f-47e3-9e33-c7a55ae226a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184703300 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_smoke.4184703300
Directory /workspace/12.hmac_smoke/latest

Test location /workspace/coverage/default/12.hmac_stress_all.4152430624
Short name T91
Test name
Test status
Simulation time 759983317468 ps
CPU time 5313.39 seconds
Started Jun 28 05:00:49 PM PDT 24
Finished Jun 28 06:29:24 PM PDT 24
Peak memory 828768 kb
Host smart-e9b2251c-c9fa-4798-b4ad-8904f374d1aa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152430624 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.hmac_stress_all.4152430624
Directory /workspace/12.hmac_stress_all/latest

Test location /workspace/coverage/default/12.hmac_test_hmac256_vectors.4101435940
Short name T21
Test name
Test status
Simulation time 1018089668 ps
CPU time 36.65 seconds
Started Jun 28 05:00:47 PM PDT 24
Finished Jun 28 05:01:25 PM PDT 24
Peak memory 200240 kb
Host smart-adb171d8-4671-4946-a4ff-a3d904124853
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4101435940 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac256_vectors.4101435940
Directory /workspace/12.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_hmac384_vectors.1491802305
Short name T161
Test name
Test status
Simulation time 4073596368 ps
CPU time 45.09 seconds
Started Jun 28 05:00:47 PM PDT 24
Finished Jun 28 05:01:33 PM PDT 24
Peak memory 200292 kb
Host smart-6ba724c1-9c07-4467-8c10-0daeb2bd16b9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1491802305 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac384_vectors.1491802305
Directory /workspace/12.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_hmac512_vectors.2193509447
Short name T452
Test name
Test status
Simulation time 1963191242 ps
CPU time 64.03 seconds
Started Jun 28 05:00:53 PM PDT 24
Finished Jun 28 05:01:58 PM PDT 24
Peak memory 200308 kb
Host smart-320bb932-33a0-4d31-a7a0-497fbcbe504e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2193509447 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_hmac512_vectors.2193509447
Directory /workspace/12.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha256_vectors.1923821951
Short name T188
Test name
Test status
Simulation time 34222440925 ps
CPU time 408.24 seconds
Started Jun 28 05:01:00 PM PDT 24
Finished Jun 28 05:07:49 PM PDT 24
Peak memory 200152 kb
Host smart-0b4f38f0-f194-4dce-9910-15ef8ef8993f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1923821951 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha256_vectors.1923821951
Directory /workspace/12.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha384_vectors.1544132425
Short name T384
Test name
Test status
Simulation time 717393524512 ps
CPU time 2065.35 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 05:35:13 PM PDT 24
Peak memory 216204 kb
Host smart-6eaf65da-de0d-498b-bb3b-fa0ed19e5261
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1544132425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha384_vectors.1544132425
Directory /workspace/12.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/12.hmac_test_sha512_vectors.2043365454
Short name T58
Test name
Test status
Simulation time 218649600498 ps
CPU time 1866.48 seconds
Started Jun 28 05:00:52 PM PDT 24
Finished Jun 28 05:32:00 PM PDT 24
Peak memory 216472 kb
Host smart-8657ffb1-3ef3-4f73-af0d-89db1dabd776
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2043365454 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_test_sha512_vectors.2043365454
Directory /workspace/12.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/12.hmac_wipe_secret.1026685888
Short name T191
Test name
Test status
Simulation time 3143474257 ps
CPU time 55.51 seconds
Started Jun 28 05:01:00 PM PDT 24
Finished Jun 28 05:01:56 PM PDT 24
Peak memory 200320 kb
Host smart-5ea179b7-f443-449b-b8f7-d53eebc22437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026685888 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.hmac_wipe_secret.1026685888
Directory /workspace/12.hmac_wipe_secret/latest

Test location /workspace/coverage/default/13.hmac_alert_test.1024718794
Short name T480
Test name
Test status
Simulation time 13666011 ps
CPU time 0.6 seconds
Started Jun 28 05:01:03 PM PDT 24
Finished Jun 28 05:01:04 PM PDT 24
Peak memory 196268 kb
Host smart-d84c69fe-dcc4-400d-890f-a97e4eda4e5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024718794 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_alert_test.1024718794
Directory /workspace/13.hmac_alert_test/latest

Test location /workspace/coverage/default/13.hmac_back_pressure.1830238552
Short name T753
Test name
Test status
Simulation time 1600026341 ps
CPU time 37.09 seconds
Started Jun 28 05:00:52 PM PDT 24
Finished Jun 28 05:01:29 PM PDT 24
Peak memory 200236 kb
Host smart-2908fad2-bc58-4ec1-b1ad-063634b18748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1830238552 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_back_pressure.1830238552
Directory /workspace/13.hmac_back_pressure/latest

Test location /workspace/coverage/default/13.hmac_burst_wr.1109084933
Short name T349
Test name
Test status
Simulation time 1172523020 ps
CPU time 12.76 seconds
Started Jun 28 05:00:53 PM PDT 24
Finished Jun 28 05:01:07 PM PDT 24
Peak memory 200320 kb
Host smart-0bf4a79b-51d7-493d-be94-a06f44298d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109084933 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_burst_wr.1109084933
Directory /workspace/13.hmac_burst_wr/latest

Test location /workspace/coverage/default/13.hmac_datapath_stress.529898802
Short name T197
Test name
Test status
Simulation time 52176015680 ps
CPU time 1195.05 seconds
Started Jun 28 05:00:53 PM PDT 24
Finished Jun 28 05:20:49 PM PDT 24
Peak memory 777336 kb
Host smart-ab99fe0a-d9c9-4298-9d7e-6909a25ecc88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=529898802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_datapath_stress.529898802
Directory /workspace/13.hmac_datapath_stress/latest

Test location /workspace/coverage/default/13.hmac_error.3588293000
Short name T529
Test name
Test status
Simulation time 3221442329 ps
CPU time 138.29 seconds
Started Jun 28 05:00:55 PM PDT 24
Finished Jun 28 05:03:14 PM PDT 24
Peak memory 200316 kb
Host smart-0a2c3893-6905-4cf1-9d48-17c1c3b12f7f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588293000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_error.3588293000
Directory /workspace/13.hmac_error/latest

Test location /workspace/coverage/default/13.hmac_long_msg.746484509
Short name T726
Test name
Test status
Simulation time 9469376448 ps
CPU time 90.06 seconds
Started Jun 28 05:01:03 PM PDT 24
Finished Jun 28 05:02:33 PM PDT 24
Peak memory 200388 kb
Host smart-1a687267-aa65-4d55-9f7b-9a49bef2dd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746484509 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_long_msg.746484509
Directory /workspace/13.hmac_long_msg/latest

Test location /workspace/coverage/default/13.hmac_smoke.2646087796
Short name T733
Test name
Test status
Simulation time 1215811081 ps
CPU time 7.03 seconds
Started Jun 28 05:01:00 PM PDT 24
Finished Jun 28 05:01:07 PM PDT 24
Peak memory 200324 kb
Host smart-f4b8dba3-6cf0-41f8-8b28-d1cf63b2f85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646087796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_smoke.2646087796
Directory /workspace/13.hmac_smoke/latest

Test location /workspace/coverage/default/13.hmac_stress_all.622009340
Short name T660
Test name
Test status
Simulation time 416328747005 ps
CPU time 5231.12 seconds
Started Jun 28 05:00:56 PM PDT 24
Finished Jun 28 06:28:08 PM PDT 24
Peak memory 349728 kb
Host smart-50013e52-5126-4587-9823-5a6d2a4d0759
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622009340 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.hmac_stress_all.622009340
Directory /workspace/13.hmac_stress_all/latest

Test location /workspace/coverage/default/13.hmac_test_hmac256_vectors.2303571976
Short name T255
Test name
Test status
Simulation time 925223293 ps
CPU time 30.92 seconds
Started Jun 28 05:00:55 PM PDT 24
Finished Jun 28 05:01:27 PM PDT 24
Peak memory 200264 kb
Host smart-e48a3eb7-62b1-4b9a-886b-7cd3d6537c85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2303571976 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac256_vectors.2303571976
Directory /workspace/13.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_hmac384_vectors.2797291982
Short name T222
Test name
Test status
Simulation time 4084007847 ps
CPU time 74.15 seconds
Started Jun 28 05:00:52 PM PDT 24
Finished Jun 28 05:02:07 PM PDT 24
Peak memory 200292 kb
Host smart-97474f5b-fb91-48cb-ab60-323f84202707
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2797291982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac384_vectors.2797291982
Directory /workspace/13.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_hmac512_vectors.2868424755
Short name T756
Test name
Test status
Simulation time 2286387286 ps
CPU time 64.15 seconds
Started Jun 28 05:00:56 PM PDT 24
Finished Jun 28 05:02:00 PM PDT 24
Peak memory 200324 kb
Host smart-2230ec8d-2c8d-4aa9-ac33-cd55ac894c86
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2868424755 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_hmac512_vectors.2868424755
Directory /workspace/13.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha256_vectors.3693092785
Short name T777
Test name
Test status
Simulation time 130738990524 ps
CPU time 435.78 seconds
Started Jun 28 05:01:03 PM PDT 24
Finished Jun 28 05:08:19 PM PDT 24
Peak memory 200264 kb
Host smart-7c8532ce-82a0-4b07-8f59-27e9179bfbc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3693092785 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha256_vectors.3693092785
Directory /workspace/13.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha384_vectors.3159072169
Short name T226
Test name
Test status
Simulation time 124801061600 ps
CPU time 1761.31 seconds
Started Jun 28 05:00:53 PM PDT 24
Finished Jun 28 05:30:15 PM PDT 24
Peak memory 216548 kb
Host smart-2c5389fe-5cf1-4b43-9f95-82c652cc2b3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3159072169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha384_vectors.3159072169
Directory /workspace/13.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/13.hmac_test_sha512_vectors.4246487358
Short name T218
Test name
Test status
Simulation time 435182995973 ps
CPU time 2130.4 seconds
Started Jun 28 05:00:56 PM PDT 24
Finished Jun 28 05:36:27 PM PDT 24
Peak memory 215944 kb
Host smart-c7e796aa-247a-4ecb-ab1f-41797dd6cedf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4246487358 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_test_sha512_vectors.4246487358
Directory /workspace/13.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/13.hmac_wipe_secret.2487829753
Short name T619
Test name
Test status
Simulation time 649210239 ps
CPU time 19 seconds
Started Jun 28 05:00:53 PM PDT 24
Finished Jun 28 05:01:13 PM PDT 24
Peak memory 200240 kb
Host smart-3cebb786-7ad9-4a04-9673-32d7e20e493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487829753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.hmac_wipe_secret.2487829753
Directory /workspace/13.hmac_wipe_secret/latest

Test location /workspace/coverage/default/14.hmac_alert_test.1892071589
Short name T570
Test name
Test status
Simulation time 14016523 ps
CPU time 0.58 seconds
Started Jun 28 05:01:03 PM PDT 24
Finished Jun 28 05:01:05 PM PDT 24
Peak memory 195128 kb
Host smart-8399d5c4-ca64-48b0-b915-83e2ff9d00d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892071589 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_alert_test.1892071589
Directory /workspace/14.hmac_alert_test/latest

Test location /workspace/coverage/default/14.hmac_back_pressure.3166768750
Short name T441
Test name
Test status
Simulation time 406000801 ps
CPU time 18.32 seconds
Started Jun 28 05:00:53 PM PDT 24
Finished Jun 28 05:01:12 PM PDT 24
Peak memory 200260 kb
Host smart-58343adb-5d3b-4a02-9f19-db7eeea80cca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166768750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_back_pressure.3166768750
Directory /workspace/14.hmac_back_pressure/latest

Test location /workspace/coverage/default/14.hmac_burst_wr.3604909029
Short name T423
Test name
Test status
Simulation time 334900385 ps
CPU time 8.87 seconds
Started Jun 28 05:01:03 PM PDT 24
Finished Jun 28 05:01:13 PM PDT 24
Peak memory 200268 kb
Host smart-af2a5d2d-55b2-4c96-9b21-217d49dd6959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604909029 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_burst_wr.3604909029
Directory /workspace/14.hmac_burst_wr/latest

Test location /workspace/coverage/default/14.hmac_datapath_stress.1443566475
Short name T325
Test name
Test status
Simulation time 2096247323 ps
CPU time 395.63 seconds
Started Jun 28 05:00:53 PM PDT 24
Finished Jun 28 05:07:30 PM PDT 24
Peak memory 659180 kb
Host smart-d91542d8-d3bf-4061-830d-bebb7b50d51f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443566475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_datapath_stress.1443566475
Directory /workspace/14.hmac_datapath_stress/latest

Test location /workspace/coverage/default/14.hmac_error.1721066561
Short name T672
Test name
Test status
Simulation time 11108913041 ps
CPU time 159.94 seconds
Started Jun 28 05:01:03 PM PDT 24
Finished Jun 28 05:03:43 PM PDT 24
Peak memory 200324 kb
Host smart-c4bc475d-2651-4bb6-bb5f-6998b2ce5aa4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721066561 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_error.1721066561
Directory /workspace/14.hmac_error/latest

Test location /workspace/coverage/default/14.hmac_long_msg.8854922
Short name T373
Test name
Test status
Simulation time 12793973916 ps
CPU time 116.55 seconds
Started Jun 28 05:01:02 PM PDT 24
Finished Jun 28 05:02:59 PM PDT 24
Peak memory 200372 kb
Host smart-255840a4-a657-4053-914e-0f8914ca847e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8854922 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_long_msg.8854922
Directory /workspace/14.hmac_long_msg/latest

Test location /workspace/coverage/default/14.hmac_smoke.958669512
Short name T32
Test name
Test status
Simulation time 2445803926 ps
CPU time 8.09 seconds
Started Jun 28 05:00:53 PM PDT 24
Finished Jun 28 05:01:01 PM PDT 24
Peak memory 200308 kb
Host smart-7078a5e1-5498-478a-aa27-aae165156f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958669512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_smoke.958669512
Directory /workspace/14.hmac_smoke/latest

Test location /workspace/coverage/default/14.hmac_test_hmac256_vectors.3934985619
Short name T235
Test name
Test status
Simulation time 6790297456 ps
CPU time 58.05 seconds
Started Jun 28 05:01:04 PM PDT 24
Finished Jun 28 05:02:03 PM PDT 24
Peak memory 200320 kb
Host smart-5481d6cf-7498-467e-b4e9-c682bc0d478a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3934985619 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac256_vectors.3934985619
Directory /workspace/14.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_hmac384_vectors.4225042362
Short name T302
Test name
Test status
Simulation time 28201455680 ps
CPU time 54.29 seconds
Started Jun 28 05:01:04 PM PDT 24
Finished Jun 28 05:01:59 PM PDT 24
Peak memory 200244 kb
Host smart-6456accd-5d83-4cfe-b4f8-718312a75bd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4225042362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac384_vectors.4225042362
Directory /workspace/14.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_hmac512_vectors.2636609455
Short name T644
Test name
Test status
Simulation time 1780874230 ps
CPU time 54.34 seconds
Started Jun 28 05:01:04 PM PDT 24
Finished Jun 28 05:01:59 PM PDT 24
Peak memory 200264 kb
Host smart-290b3305-a09f-4c48-bcfb-9fbd056510de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2636609455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_hmac512_vectors.2636609455
Directory /workspace/14.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha256_vectors.2578892378
Short name T34
Test name
Test status
Simulation time 8145177652 ps
CPU time 476.88 seconds
Started Jun 28 05:01:05 PM PDT 24
Finished Jun 28 05:09:02 PM PDT 24
Peak memory 200184 kb
Host smart-7f19d210-2bdd-4347-bbcd-b9e38a334473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2578892378 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha256_vectors.2578892378
Directory /workspace/14.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/14.hmac_test_sha512_vectors.1059210042
Short name T620
Test name
Test status
Simulation time 120281838020 ps
CPU time 1847.31 seconds
Started Jun 28 05:01:03 PM PDT 24
Finished Jun 28 05:31:52 PM PDT 24
Peak memory 215772 kb
Host smart-e14f42e9-104c-451c-ac4a-346f356ac465
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1059210042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_test_sha512_vectors.1059210042
Directory /workspace/14.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/14.hmac_wipe_secret.1272802319
Short name T443
Test name
Test status
Simulation time 23520775132 ps
CPU time 77.6 seconds
Started Jun 28 05:01:06 PM PDT 24
Finished Jun 28 05:02:24 PM PDT 24
Peak memory 200304 kb
Host smart-2f0cb19b-6713-4395-a1a2-dd40d4c6f978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272802319 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.hmac_wipe_secret.1272802319
Directory /workspace/14.hmac_wipe_secret/latest

Test location /workspace/coverage/default/15.hmac_alert_test.661595418
Short name T234
Test name
Test status
Simulation time 35448407 ps
CPU time 0.58 seconds
Started Jun 28 05:01:14 PM PDT 24
Finished Jun 28 05:01:16 PM PDT 24
Peak memory 195156 kb
Host smart-b6cc9ec2-5099-4b57-baed-0b750c07bc7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661595418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_alert_test.661595418
Directory /workspace/15.hmac_alert_test/latest

Test location /workspace/coverage/default/15.hmac_back_pressure.4010458492
Short name T502
Test name
Test status
Simulation time 713201682 ps
CPU time 17.9 seconds
Started Jun 28 05:01:14 PM PDT 24
Finished Jun 28 05:01:32 PM PDT 24
Peak memory 200252 kb
Host smart-600eae58-de57-4cd0-a693-576634576e3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4010458492 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_back_pressure.4010458492
Directory /workspace/15.hmac_back_pressure/latest

Test location /workspace/coverage/default/15.hmac_burst_wr.1510950770
Short name T148
Test name
Test status
Simulation time 1016826657 ps
CPU time 57.38 seconds
Started Jun 28 05:01:18 PM PDT 24
Finished Jun 28 05:02:16 PM PDT 24
Peak memory 200332 kb
Host smart-a37d0148-53a8-498d-acc1-2d8a77774300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510950770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_burst_wr.1510950770
Directory /workspace/15.hmac_burst_wr/latest

Test location /workspace/coverage/default/15.hmac_datapath_stress.2163553398
Short name T352
Test name
Test status
Simulation time 9763710281 ps
CPU time 702.22 seconds
Started Jun 28 05:01:14 PM PDT 24
Finished Jun 28 05:12:57 PM PDT 24
Peak memory 691260 kb
Host smart-c6661aef-fc62-4d42-b5cf-386ed29a7fc2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2163553398 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_datapath_stress.2163553398
Directory /workspace/15.hmac_datapath_stress/latest

Test location /workspace/coverage/default/15.hmac_error.2637724520
Short name T44
Test name
Test status
Simulation time 2854462627 ps
CPU time 33.27 seconds
Started Jun 28 05:01:13 PM PDT 24
Finished Jun 28 05:01:46 PM PDT 24
Peak memory 200332 kb
Host smart-2ffab78e-4de5-4234-8130-bdb387c19b31
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637724520 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_error.2637724520
Directory /workspace/15.hmac_error/latest

Test location /workspace/coverage/default/15.hmac_long_msg.217669355
Short name T521
Test name
Test status
Simulation time 54030054620 ps
CPU time 144.99 seconds
Started Jun 28 05:01:17 PM PDT 24
Finished Jun 28 05:03:43 PM PDT 24
Peak memory 200392 kb
Host smart-867863ab-0d10-4670-a9ed-2fa727179180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217669355 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_long_msg.217669355
Directory /workspace/15.hmac_long_msg/latest

Test location /workspace/coverage/default/15.hmac_smoke.1399474811
Short name T764
Test name
Test status
Simulation time 974149787 ps
CPU time 10.87 seconds
Started Jun 28 05:01:03 PM PDT 24
Finished Jun 28 05:01:14 PM PDT 24
Peak memory 200248 kb
Host smart-6eff832e-bebc-4289-bb3d-3df59d72a333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399474811 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_smoke.1399474811
Directory /workspace/15.hmac_smoke/latest

Test location /workspace/coverage/default/15.hmac_stress_all.3795276727
Short name T653
Test name
Test status
Simulation time 531686375574 ps
CPU time 2665.87 seconds
Started Jun 28 05:01:14 PM PDT 24
Finished Jun 28 05:45:41 PM PDT 24
Peak memory 216636 kb
Host smart-f9b9c283-bef1-4a1f-b2cf-3f3e14b574a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795276727 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.hmac_stress_all.3795276727
Directory /workspace/15.hmac_stress_all/latest

Test location /workspace/coverage/default/15.hmac_test_hmac256_vectors.3161116588
Short name T503
Test name
Test status
Simulation time 104001065446 ps
CPU time 69.33 seconds
Started Jun 28 05:01:20 PM PDT 24
Finished Jun 28 05:02:30 PM PDT 24
Peak memory 200368 kb
Host smart-2d1e9ac2-745f-4074-b9ae-41b8c194a97f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3161116588 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac256_vectors.3161116588
Directory /workspace/15.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_hmac384_vectors.565112590
Short name T242
Test name
Test status
Simulation time 43363467636 ps
CPU time 83.06 seconds
Started Jun 28 05:01:22 PM PDT 24
Finished Jun 28 05:02:45 PM PDT 24
Peak memory 200332 kb
Host smart-82e32afd-5f2a-4be6-bc62-bb49630e5a35
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=565112590 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac384_vectors.565112590
Directory /workspace/15.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_hmac512_vectors.2430949251
Short name T487
Test name
Test status
Simulation time 7319686393 ps
CPU time 50.39 seconds
Started Jun 28 05:01:15 PM PDT 24
Finished Jun 28 05:02:05 PM PDT 24
Peak memory 200320 kb
Host smart-0ed5a27e-4e71-441e-a5ac-14300dd51fb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2430949251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_hmac512_vectors.2430949251
Directory /workspace/15.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha256_vectors.3379701547
Short name T272
Test name
Test status
Simulation time 7966041717 ps
CPU time 435.95 seconds
Started Jun 28 05:01:13 PM PDT 24
Finished Jun 28 05:08:29 PM PDT 24
Peak memory 200200 kb
Host smart-3f273379-1f33-433f-8e05-bac92c497b12
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3379701547 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha256_vectors.3379701547
Directory /workspace/15.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha384_vectors.336049763
Short name T392
Test name
Test status
Simulation time 765409650592 ps
CPU time 1760 seconds
Started Jun 28 05:01:17 PM PDT 24
Finished Jun 28 05:30:38 PM PDT 24
Peak memory 216672 kb
Host smart-3b1951c5-65b5-44b8-b3d6-ffa822b054c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=336049763 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha384_vectors.336049763
Directory /workspace/15.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/15.hmac_test_sha512_vectors.1300372102
Short name T244
Test name
Test status
Simulation time 32044583087 ps
CPU time 1771.13 seconds
Started Jun 28 05:01:13 PM PDT 24
Finished Jun 28 05:30:45 PM PDT 24
Peak memory 216168 kb
Host smart-b118a6a3-eb20-478d-a79a-6dcfbce8b42f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1300372102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_test_sha512_vectors.1300372102
Directory /workspace/15.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/15.hmac_wipe_secret.3734140396
Short name T385
Test name
Test status
Simulation time 28441816487 ps
CPU time 90.01 seconds
Started Jun 28 05:01:12 PM PDT 24
Finished Jun 28 05:02:43 PM PDT 24
Peak memory 200508 kb
Host smart-49b487bf-8173-4c0b-b259-758da452f840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734140396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.hmac_wipe_secret.3734140396
Directory /workspace/15.hmac_wipe_secret/latest

Test location /workspace/coverage/default/16.hmac_alert_test.2100656807
Short name T394
Test name
Test status
Simulation time 11153806 ps
CPU time 0.59 seconds
Started Jun 28 05:01:36 PM PDT 24
Finished Jun 28 05:01:37 PM PDT 24
Peak memory 196924 kb
Host smart-eca6cf0b-44df-4b9e-b3d7-de07d2970f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100656807 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_alert_test.2100656807
Directory /workspace/16.hmac_alert_test/latest

Test location /workspace/coverage/default/16.hmac_back_pressure.3430965483
Short name T28
Test name
Test status
Simulation time 966928723 ps
CPU time 48.64 seconds
Started Jun 28 05:01:24 PM PDT 24
Finished Jun 28 05:02:13 PM PDT 24
Peak memory 200272 kb
Host smart-e248c369-0d95-4680-80a2-e7bfa6bdcd82
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3430965483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_back_pressure.3430965483
Directory /workspace/16.hmac_back_pressure/latest

Test location /workspace/coverage/default/16.hmac_burst_wr.4210811195
Short name T647
Test name
Test status
Simulation time 257513568 ps
CPU time 1.74 seconds
Started Jun 28 05:01:25 PM PDT 24
Finished Jun 28 05:01:28 PM PDT 24
Peak memory 200152 kb
Host smart-10cd9021-4797-4a1e-b6c7-18850b76ee32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210811195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_burst_wr.4210811195
Directory /workspace/16.hmac_burst_wr/latest

Test location /workspace/coverage/default/16.hmac_datapath_stress.734236225
Short name T780
Test name
Test status
Simulation time 1705078899 ps
CPU time 29.23 seconds
Started Jun 28 05:01:26 PM PDT 24
Finished Jun 28 05:01:56 PM PDT 24
Peak memory 295728 kb
Host smart-4cb9d028-540a-4cb3-a82e-ea6b5591c3f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734236225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_datapath_stress.734236225
Directory /workspace/16.hmac_datapath_stress/latest

Test location /workspace/coverage/default/16.hmac_error.1207018190
Short name T216
Test name
Test status
Simulation time 1009702207 ps
CPU time 55.77 seconds
Started Jun 28 05:01:25 PM PDT 24
Finished Jun 28 05:02:22 PM PDT 24
Peak memory 200260 kb
Host smart-2b1b382e-d2ee-47d5-8a5d-e7aef09e46ca
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207018190 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_error.1207018190
Directory /workspace/16.hmac_error/latest

Test location /workspace/coverage/default/16.hmac_long_msg.292924070
Short name T680
Test name
Test status
Simulation time 7498252852 ps
CPU time 143.25 seconds
Started Jun 28 05:01:26 PM PDT 24
Finished Jun 28 05:03:50 PM PDT 24
Peak memory 200272 kb
Host smart-52d477a3-1fa8-41db-a8eb-44902602c012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292924070 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_long_msg.292924070
Directory /workspace/16.hmac_long_msg/latest

Test location /workspace/coverage/default/16.hmac_smoke.3265532209
Short name T788
Test name
Test status
Simulation time 2701007740 ps
CPU time 15.92 seconds
Started Jun 28 05:01:25 PM PDT 24
Finished Jun 28 05:01:41 PM PDT 24
Peak memory 200320 kb
Host smart-9a5b70f1-f48e-401b-b926-5dc3c19c82da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265532209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_smoke.3265532209
Directory /workspace/16.hmac_smoke/latest

Test location /workspace/coverage/default/16.hmac_stress_all.2275950951
Short name T559
Test name
Test status
Simulation time 22763522614 ps
CPU time 200.89 seconds
Started Jun 28 05:01:25 PM PDT 24
Finished Jun 28 05:04:47 PM PDT 24
Peak memory 345936 kb
Host smart-86fb89ca-1d46-4684-9897-7dcccca08b21
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275950951 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.hmac_stress_all.2275950951
Directory /workspace/16.hmac_stress_all/latest

Test location /workspace/coverage/default/16.hmac_test_hmac256_vectors.2401011844
Short name T451
Test name
Test status
Simulation time 2819802760 ps
CPU time 55.97 seconds
Started Jun 28 05:01:26 PM PDT 24
Finished Jun 28 05:02:22 PM PDT 24
Peak memory 200320 kb
Host smart-edf838af-073d-4971-9f6b-ce0f747ce750
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2401011844 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac256_vectors.2401011844
Directory /workspace/16.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_hmac384_vectors.1459358788
Short name T248
Test name
Test status
Simulation time 4239419816 ps
CPU time 44.58 seconds
Started Jun 28 05:01:27 PM PDT 24
Finished Jun 28 05:02:12 PM PDT 24
Peak memory 200328 kb
Host smart-b84cc844-b6c1-4bcb-8c6f-9a3f6d8e8564
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1459358788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac384_vectors.1459358788
Directory /workspace/16.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_hmac512_vectors.237584831
Short name T654
Test name
Test status
Simulation time 9937364512 ps
CPU time 111.19 seconds
Started Jun 28 05:01:25 PM PDT 24
Finished Jun 28 05:03:17 PM PDT 24
Peak memory 200336 kb
Host smart-86f82eb0-61cf-441b-9598-1fd8411a8996
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=237584831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_hmac512_vectors.237584831
Directory /workspace/16.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha256_vectors.807415856
Short name T243
Test name
Test status
Simulation time 42290272194 ps
CPU time 524.43 seconds
Started Jun 28 05:01:26 PM PDT 24
Finished Jun 28 05:10:11 PM PDT 24
Peak memory 200236 kb
Host smart-d25a3938-703a-4932-bbd1-cbb0cd57ae25
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=807415856 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha256_vectors.807415856
Directory /workspace/16.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/16.hmac_test_sha384_vectors.1683978912
Short name T335
Test name
Test status
Simulation time 33492680044 ps
CPU time 1835.34 seconds
Started Jun 28 05:01:26 PM PDT 24
Finished Jun 28 05:32:03 PM PDT 24
Peak memory 215784 kb
Host smart-cf307efe-052b-4950-bdde-25b4931c7e65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1683978912 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_test_sha384_vectors.1683978912
Directory /workspace/16.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/16.hmac_wipe_secret.899556884
Short name T133
Test name
Test status
Simulation time 2035347645 ps
CPU time 83.78 seconds
Started Jun 28 05:01:26 PM PDT 24
Finished Jun 28 05:02:51 PM PDT 24
Peak memory 200244 kb
Host smart-e5627f69-fc6b-480f-9a0e-32148df1452e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899556884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.hmac_wipe_secret.899556884
Directory /workspace/16.hmac_wipe_secret/latest

Test location /workspace/coverage/default/17.hmac_alert_test.3295668465
Short name T658
Test name
Test status
Simulation time 39301206 ps
CPU time 0.56 seconds
Started Jun 28 05:01:35 PM PDT 24
Finished Jun 28 05:01:37 PM PDT 24
Peak memory 195344 kb
Host smart-9f0b3a5f-6076-4e83-a0fa-10f24774ae1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295668465 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_alert_test.3295668465
Directory /workspace/17.hmac_alert_test/latest

Test location /workspace/coverage/default/17.hmac_back_pressure.1574984770
Short name T706
Test name
Test status
Simulation time 1881006004 ps
CPU time 14.13 seconds
Started Jun 28 05:01:36 PM PDT 24
Finished Jun 28 05:01:51 PM PDT 24
Peak memory 200196 kb
Host smart-e9546c37-4ee6-4521-8241-1940854723a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1574984770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_back_pressure.1574984770
Directory /workspace/17.hmac_back_pressure/latest

Test location /workspace/coverage/default/17.hmac_burst_wr.1859992550
Short name T334
Test name
Test status
Simulation time 7899717680 ps
CPU time 57.48 seconds
Started Jun 28 05:01:35 PM PDT 24
Finished Jun 28 05:02:33 PM PDT 24
Peak memory 208500 kb
Host smart-133b1e7b-4a81-4887-a0b2-1a4320f765a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859992550 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_burst_wr.1859992550
Directory /workspace/17.hmac_burst_wr/latest

Test location /workspace/coverage/default/17.hmac_datapath_stress.3166836957
Short name T141
Test name
Test status
Simulation time 3576669184 ps
CPU time 933.76 seconds
Started Jun 28 05:01:37 PM PDT 24
Finished Jun 28 05:17:11 PM PDT 24
Peak memory 744340 kb
Host smart-1613f683-bf91-4067-827f-145977122585
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166836957 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_datapath_stress.3166836957
Directory /workspace/17.hmac_datapath_stress/latest

Test location /workspace/coverage/default/17.hmac_error.3533923540
Short name T402
Test name
Test status
Simulation time 4149365947 ps
CPU time 72.37 seconds
Started Jun 28 05:01:36 PM PDT 24
Finished Jun 28 05:02:49 PM PDT 24
Peak memory 200260 kb
Host smart-2e3524cb-87db-46ee-9721-e710fb82ff98
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533923540 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_error.3533923540
Directory /workspace/17.hmac_error/latest

Test location /workspace/coverage/default/17.hmac_long_msg.742350772
Short name T228
Test name
Test status
Simulation time 1189197418 ps
CPU time 66.97 seconds
Started Jun 28 05:01:35 PM PDT 24
Finished Jun 28 05:02:43 PM PDT 24
Peak memory 200256 kb
Host smart-08b8ea01-45fe-4cf3-b446-76c36018a5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742350772 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_long_msg.742350772
Directory /workspace/17.hmac_long_msg/latest

Test location /workspace/coverage/default/17.hmac_smoke.2559160861
Short name T388
Test name
Test status
Simulation time 174963549 ps
CPU time 8.4 seconds
Started Jun 28 05:01:40 PM PDT 24
Finished Jun 28 05:01:49 PM PDT 24
Peak memory 200280 kb
Host smart-5310acaf-69ee-46e7-b1d6-69036b2b1464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559160861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_smoke.2559160861
Directory /workspace/17.hmac_smoke/latest

Test location /workspace/coverage/default/17.hmac_test_hmac256_vectors.3057214047
Short name T492
Test name
Test status
Simulation time 13462082555 ps
CPU time 40.37 seconds
Started Jun 28 05:01:42 PM PDT 24
Finished Jun 28 05:02:22 PM PDT 24
Peak memory 200304 kb
Host smart-41dbfc7b-ace1-4d7e-bc25-16989ee85e1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3057214047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac256_vectors.3057214047
Directory /workspace/17.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_hmac384_vectors.2733042904
Short name T171
Test name
Test status
Simulation time 2114594169 ps
CPU time 75.09 seconds
Started Jun 28 05:01:37 PM PDT 24
Finished Jun 28 05:02:53 PM PDT 24
Peak memory 200264 kb
Host smart-ba1bdd67-3f26-4519-9372-f973836a1bf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2733042904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac384_vectors.2733042904
Directory /workspace/17.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_hmac512_vectors.3385180195
Short name T308
Test name
Test status
Simulation time 35138596297 ps
CPU time 58.74 seconds
Started Jun 28 05:01:36 PM PDT 24
Finished Jun 28 05:02:35 PM PDT 24
Peak memory 200316 kb
Host smart-d332d152-b285-4aa9-ba9e-fc8f3c4530bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3385180195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_hmac512_vectors.3385180195
Directory /workspace/17.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha256_vectors.2583324385
Short name T267
Test name
Test status
Simulation time 147970662505 ps
CPU time 485.12 seconds
Started Jun 28 05:01:38 PM PDT 24
Finished Jun 28 05:09:44 PM PDT 24
Peak memory 200256 kb
Host smart-659c3902-5d3e-48ac-a205-7d826e4fb6ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2583324385 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha256_vectors.2583324385
Directory /workspace/17.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha384_vectors.1362148871
Short name T578
Test name
Test status
Simulation time 214267591014 ps
CPU time 1795.84 seconds
Started Jun 28 05:01:45 PM PDT 24
Finished Jun 28 05:31:41 PM PDT 24
Peak memory 215708 kb
Host smart-dcf82021-1111-452f-9e89-1d5d28bbeb52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1362148871 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha384_vectors.1362148871
Directory /workspace/17.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/17.hmac_test_sha512_vectors.1373459908
Short name T13
Test name
Test status
Simulation time 66605802000 ps
CPU time 1841.25 seconds
Started Jun 28 05:01:40 PM PDT 24
Finished Jun 28 05:32:22 PM PDT 24
Peak memory 216232 kb
Host smart-c6c15791-dcfc-4a23-a1ae-c82b065bb04e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1373459908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_test_sha512_vectors.1373459908
Directory /workspace/17.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/17.hmac_wipe_secret.293656230
Short name T254
Test name
Test status
Simulation time 778757275 ps
CPU time 36.83 seconds
Started Jun 28 05:01:37 PM PDT 24
Finished Jun 28 05:02:15 PM PDT 24
Peak memory 200272 kb
Host smart-f0161743-7882-4a57-a060-35b36a9cf98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293656230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.hmac_wipe_secret.293656230
Directory /workspace/17.hmac_wipe_secret/latest

Test location /workspace/coverage/default/18.hmac_alert_test.2061066868
Short name T407
Test name
Test status
Simulation time 15180772 ps
CPU time 0.59 seconds
Started Jun 28 05:01:48 PM PDT 24
Finished Jun 28 05:01:49 PM PDT 24
Peak memory 195208 kb
Host smart-b5c0f932-d5dd-4193-bab5-463453af6ce5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061066868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_alert_test.2061066868
Directory /workspace/18.hmac_alert_test/latest

Test location /workspace/coverage/default/18.hmac_back_pressure.2358135804
Short name T381
Test name
Test status
Simulation time 3153166326 ps
CPU time 21.31 seconds
Started Jun 28 05:01:36 PM PDT 24
Finished Jun 28 05:01:58 PM PDT 24
Peak memory 200348 kb
Host smart-6f7831bb-a2cb-465a-82d6-b42112ce5d55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358135804 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_back_pressure.2358135804
Directory /workspace/18.hmac_back_pressure/latest

Test location /workspace/coverage/default/18.hmac_burst_wr.4143931766
Short name T499
Test name
Test status
Simulation time 346583571 ps
CPU time 20.61 seconds
Started Jun 28 05:01:36 PM PDT 24
Finished Jun 28 05:01:57 PM PDT 24
Peak memory 200248 kb
Host smart-2e1b3065-dea1-40ef-9d70-bd68633c27a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143931766 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_burst_wr.4143931766
Directory /workspace/18.hmac_burst_wr/latest

Test location /workspace/coverage/default/18.hmac_datapath_stress.3270669999
Short name T679
Test name
Test status
Simulation time 6521130626 ps
CPU time 372.27 seconds
Started Jun 28 05:01:35 PM PDT 24
Finished Jun 28 05:07:48 PM PDT 24
Peak memory 691640 kb
Host smart-ab3849c0-0676-42e4-b04a-a689534b517a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3270669999 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_datapath_stress.3270669999
Directory /workspace/18.hmac_datapath_stress/latest

Test location /workspace/coverage/default/18.hmac_error.2757490289
Short name T646
Test name
Test status
Simulation time 13050324972 ps
CPU time 226.39 seconds
Started Jun 28 05:01:38 PM PDT 24
Finished Jun 28 05:05:25 PM PDT 24
Peak memory 200352 kb
Host smart-a0ffa2f7-760d-4839-bc64-99a31d9b7e54
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757490289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_error.2757490289
Directory /workspace/18.hmac_error/latest

Test location /workspace/coverage/default/18.hmac_long_msg.1468310614
Short name T223
Test name
Test status
Simulation time 559000731 ps
CPU time 31.85 seconds
Started Jun 28 05:01:38 PM PDT 24
Finished Jun 28 05:02:10 PM PDT 24
Peak memory 200328 kb
Host smart-d7b36195-20ce-4052-9127-a845c9011159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468310614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_long_msg.1468310614
Directory /workspace/18.hmac_long_msg/latest

Test location /workspace/coverage/default/18.hmac_smoke.3448557739
Short name T737
Test name
Test status
Simulation time 430311042 ps
CPU time 6.22 seconds
Started Jun 28 05:01:40 PM PDT 24
Finished Jun 28 05:01:46 PM PDT 24
Peak memory 200316 kb
Host smart-e46e7f46-3bb6-40b5-aca9-ec2d27f02312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448557739 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_smoke.3448557739
Directory /workspace/18.hmac_smoke/latest

Test location /workspace/coverage/default/18.hmac_stress_all.1303569333
Short name T90
Test name
Test status
Simulation time 1353193282034 ps
CPU time 2538.04 seconds
Started Jun 28 05:01:48 PM PDT 24
Finished Jun 28 05:44:07 PM PDT 24
Peak memory 208568 kb
Host smart-f6c01750-f95b-40aa-a4b1-e811b3435934
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303569333 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.hmac_stress_all.1303569333
Directory /workspace/18.hmac_stress_all/latest

Test location /workspace/coverage/default/18.hmac_test_hmac256_vectors.1050679938
Short name T567
Test name
Test status
Simulation time 2472229238 ps
CPU time 40.01 seconds
Started Jun 28 05:01:51 PM PDT 24
Finished Jun 28 05:02:32 PM PDT 24
Peak memory 200328 kb
Host smart-081fadea-32de-4665-a2f6-fcc915461740
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1050679938 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac256_vectors.1050679938
Directory /workspace/18.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_hmac384_vectors.2713966986
Short name T587
Test name
Test status
Simulation time 6314810739 ps
CPU time 50.85 seconds
Started Jun 28 05:01:47 PM PDT 24
Finished Jun 28 05:02:38 PM PDT 24
Peak memory 200324 kb
Host smart-c4b67b3c-99c2-4daa-b0d3-ca51445a2f69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2713966986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac384_vectors.2713966986
Directory /workspace/18.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_hmac512_vectors.756291008
Short name T758
Test name
Test status
Simulation time 21518447861 ps
CPU time 120.35 seconds
Started Jun 28 05:01:46 PM PDT 24
Finished Jun 28 05:03:47 PM PDT 24
Peak memory 200276 kb
Host smart-a199b251-a6c9-4db6-88da-f26a113c5426
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=756291008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_hmac512_vectors.756291008
Directory /workspace/18.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha256_vectors.426309066
Short name T265
Test name
Test status
Simulation time 16834097593 ps
CPU time 464.03 seconds
Started Jun 28 05:01:36 PM PDT 24
Finished Jun 28 05:09:21 PM PDT 24
Peak memory 200224 kb
Host smart-6fb2883a-60fd-49c9-b2fa-48c22cac6495
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=426309066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha256_vectors.426309066
Directory /workspace/18.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha384_vectors.3392976679
Short name T176
Test name
Test status
Simulation time 108659384121 ps
CPU time 2001.4 seconds
Started Jun 28 05:01:35 PM PDT 24
Finished Jun 28 05:34:58 PM PDT 24
Peak memory 215908 kb
Host smart-0c944520-702f-4d25-9481-13f598a3035e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3392976679 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha384_vectors.3392976679
Directory /workspace/18.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/18.hmac_test_sha512_vectors.2619214157
Short name T360
Test name
Test status
Simulation time 224050855674 ps
CPU time 1822.1 seconds
Started Jun 28 05:01:36 PM PDT 24
Finished Jun 28 05:31:59 PM PDT 24
Peak memory 215676 kb
Host smart-46d6709e-fd14-4b85-a4ec-1f3eaae5e6ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2619214157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_test_sha512_vectors.2619214157
Directory /workspace/18.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/18.hmac_wipe_secret.2802102497
Short name T136
Test name
Test status
Simulation time 9272543369 ps
CPU time 46.33 seconds
Started Jun 28 05:01:37 PM PDT 24
Finished Jun 28 05:02:24 PM PDT 24
Peak memory 200376 kb
Host smart-acf7424b-b3de-47a5-908a-b721b3d2879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802102497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.hmac_wipe_secret.2802102497
Directory /workspace/18.hmac_wipe_secret/latest

Test location /workspace/coverage/default/19.hmac_alert_test.193016476
Short name T772
Test name
Test status
Simulation time 13034107 ps
CPU time 0.6 seconds
Started Jun 28 05:01:49 PM PDT 24
Finished Jun 28 05:01:50 PM PDT 24
Peak memory 196272 kb
Host smart-e9601475-0206-49ad-8ecb-7482c8310835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193016476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_alert_test.193016476
Directory /workspace/19.hmac_alert_test/latest

Test location /workspace/coverage/default/19.hmac_back_pressure.4282920746
Short name T29
Test name
Test status
Simulation time 641290060 ps
CPU time 27.89 seconds
Started Jun 28 05:01:57 PM PDT 24
Finished Jun 28 05:02:26 PM PDT 24
Peak memory 200296 kb
Host smart-c0646d1c-28f9-4bd7-aa02-f488ac2f38d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282920746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_back_pressure.4282920746
Directory /workspace/19.hmac_back_pressure/latest

Test location /workspace/coverage/default/19.hmac_burst_wr.2744104556
Short name T716
Test name
Test status
Simulation time 27470959433 ps
CPU time 53.31 seconds
Started Jun 28 05:01:51 PM PDT 24
Finished Jun 28 05:02:45 PM PDT 24
Peak memory 216764 kb
Host smart-6d192b40-234b-4643-a47d-4f0d7c6e8c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744104556 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_burst_wr.2744104556
Directory /workspace/19.hmac_burst_wr/latest

Test location /workspace/coverage/default/19.hmac_datapath_stress.39442149
Short name T377
Test name
Test status
Simulation time 14849794614 ps
CPU time 1055.88 seconds
Started Jun 28 05:01:47 PM PDT 24
Finished Jun 28 05:19:23 PM PDT 24
Peak memory 731024 kb
Host smart-212a1f06-d5d3-46a3-a4e1-628f51fd544a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39442149 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_datapath_stress.39442149
Directory /workspace/19.hmac_datapath_stress/latest

Test location /workspace/coverage/default/19.hmac_long_msg.799394424
Short name T404
Test name
Test status
Simulation time 319951874 ps
CPU time 17.93 seconds
Started Jun 28 05:01:46 PM PDT 24
Finished Jun 28 05:02:04 PM PDT 24
Peak memory 200316 kb
Host smart-eb254291-605c-44e2-842a-e6a2a9c8e004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799394424 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_long_msg.799394424
Directory /workspace/19.hmac_long_msg/latest

Test location /workspace/coverage/default/19.hmac_smoke.591505122
Short name T602
Test name
Test status
Simulation time 29181604 ps
CPU time 1.63 seconds
Started Jun 28 05:01:47 PM PDT 24
Finished Jun 28 05:01:49 PM PDT 24
Peak memory 200116 kb
Host smart-143549c3-bdfe-449d-b26e-e8d61923384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591505122 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_smoke.591505122
Directory /workspace/19.hmac_smoke/latest

Test location /workspace/coverage/default/19.hmac_stress_all.1430523845
Short name T572
Test name
Test status
Simulation time 2890828778 ps
CPU time 46.06 seconds
Started Jun 28 05:01:48 PM PDT 24
Finished Jun 28 05:02:34 PM PDT 24
Peak memory 200328 kb
Host smart-418f19a4-2401-4f0f-9f15-b564d1b9b7c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430523845 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.hmac_stress_all.1430523845
Directory /workspace/19.hmac_stress_all/latest

Test location /workspace/coverage/default/19.hmac_test_hmac256_vectors.4083766671
Short name T290
Test name
Test status
Simulation time 32540636875 ps
CPU time 71.04 seconds
Started Jun 28 05:01:58 PM PDT 24
Finished Jun 28 05:03:10 PM PDT 24
Peak memory 200312 kb
Host smart-d1de44bf-c945-4b6f-bee0-b6a230f3caf0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4083766671 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac256_vectors.4083766671
Directory /workspace/19.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_hmac384_vectors.3010802410
Short name T424
Test name
Test status
Simulation time 1515935809 ps
CPU time 49.17 seconds
Started Jun 28 05:01:53 PM PDT 24
Finished Jun 28 05:02:42 PM PDT 24
Peak memory 200268 kb
Host smart-7ec06027-8d91-4014-9cad-6418c0828b1a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3010802410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac384_vectors.3010802410
Directory /workspace/19.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_hmac512_vectors.21454819
Short name T543
Test name
Test status
Simulation time 19566312361 ps
CPU time 54.97 seconds
Started Jun 28 05:01:47 PM PDT 24
Finished Jun 28 05:02:42 PM PDT 24
Peak memory 200336 kb
Host smart-4af5e19f-014e-4d89-b841-0ed2ed1aa1c8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=21454819 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_hmac512_vectors.21454819
Directory /workspace/19.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha256_vectors.470578056
Short name T194
Test name
Test status
Simulation time 36535269455 ps
CPU time 490.92 seconds
Started Jun 28 05:01:47 PM PDT 24
Finished Jun 28 05:09:58 PM PDT 24
Peak memory 200188 kb
Host smart-eb1b8b4c-83f7-4e2f-85da-98f956a528ba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=470578056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha256_vectors.470578056
Directory /workspace/19.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha384_vectors.306466703
Short name T464
Test name
Test status
Simulation time 415383793857 ps
CPU time 1873.04 seconds
Started Jun 28 05:01:57 PM PDT 24
Finished Jun 28 05:33:12 PM PDT 24
Peak memory 216548 kb
Host smart-4bf1190d-40d7-4d8f-a979-9a58165524fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=306466703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha384_vectors.306466703
Directory /workspace/19.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/19.hmac_test_sha512_vectors.314779968
Short name T698
Test name
Test status
Simulation time 682734760682 ps
CPU time 2138.2 seconds
Started Jun 28 05:01:58 PM PDT 24
Finished Jun 28 05:37:37 PM PDT 24
Peak memory 216308 kb
Host smart-d48c16dc-2d67-4830-8537-1d684ac1798c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=314779968 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_test_sha512_vectors.314779968
Directory /workspace/19.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/19.hmac_wipe_secret.708500311
Short name T135
Test name
Test status
Simulation time 3727469205 ps
CPU time 76.7 seconds
Started Jun 28 05:01:57 PM PDT 24
Finished Jun 28 05:03:14 PM PDT 24
Peak memory 200340 kb
Host smart-d8ad2efa-a0c1-4a10-89f5-9128869643b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708500311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.hmac_wipe_secret.708500311
Directory /workspace/19.hmac_wipe_secret/latest

Test location /workspace/coverage/default/2.hmac_alert_test.1198526295
Short name T81
Test name
Test status
Simulation time 46693339 ps
CPU time 0.63 seconds
Started Jun 28 05:00:05 PM PDT 24
Finished Jun 28 05:00:06 PM PDT 24
Peak memory 197000 kb
Host smart-594dd5e8-5a97-4ff8-bca3-7f169a145579
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198526295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_alert_test.1198526295
Directory /workspace/2.hmac_alert_test/latest

Test location /workspace/coverage/default/2.hmac_back_pressure.3654435826
Short name T27
Test name
Test status
Simulation time 196676893 ps
CPU time 10.21 seconds
Started Jun 28 04:59:55 PM PDT 24
Finished Jun 28 05:00:06 PM PDT 24
Peak memory 200232 kb
Host smart-21a7abf8-0636-4a63-ba05-2c7ef1a09e4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3654435826 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_back_pressure.3654435826
Directory /workspace/2.hmac_back_pressure/latest

Test location /workspace/coverage/default/2.hmac_burst_wr.3414423659
Short name T332
Test name
Test status
Simulation time 15924287973 ps
CPU time 75.89 seconds
Started Jun 28 04:59:59 PM PDT 24
Finished Jun 28 05:01:15 PM PDT 24
Peak memory 208584 kb
Host smart-f1429fae-3ee4-4148-840f-d87b8ccf0d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414423659 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_burst_wr.3414423659
Directory /workspace/2.hmac_burst_wr/latest

Test location /workspace/coverage/default/2.hmac_datapath_stress.2366804668
Short name T582
Test name
Test status
Simulation time 109411769 ps
CPU time 1.11 seconds
Started Jun 28 04:59:54 PM PDT 24
Finished Jun 28 04:59:56 PM PDT 24
Peak memory 199944 kb
Host smart-638d4894-ec06-4e69-848a-1736bd77f2df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2366804668 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_datapath_stress.2366804668
Directory /workspace/2.hmac_datapath_stress/latest

Test location /workspace/coverage/default/2.hmac_error.444258575
Short name T386
Test name
Test status
Simulation time 7723567531 ps
CPU time 30.18 seconds
Started Jun 28 04:59:56 PM PDT 24
Finished Jun 28 05:00:27 PM PDT 24
Peak memory 200192 kb
Host smart-51686675-c9c1-4383-a1ff-0d713353f5dc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444258575 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_error.444258575
Directory /workspace/2.hmac_error/latest

Test location /workspace/coverage/default/2.hmac_long_msg.2023375560
Short name T382
Test name
Test status
Simulation time 5419748751 ps
CPU time 79.25 seconds
Started Jun 28 04:59:54 PM PDT 24
Finished Jun 28 05:01:15 PM PDT 24
Peak memory 216596 kb
Host smart-1a66d5f1-8058-44ef-a2f9-8a19110f736f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023375560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_long_msg.2023375560
Directory /workspace/2.hmac_long_msg/latest

Test location /workspace/coverage/default/2.hmac_sec_cm.3682239107
Short name T50
Test name
Test status
Simulation time 60544688 ps
CPU time 0.87 seconds
Started Jun 28 05:00:04 PM PDT 24
Finished Jun 28 05:00:06 PM PDT 24
Peak memory 218780 kb
Host smart-e91e73e6-a891-4990-b62f-8f7ea261184a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682239107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_sec_cm.3682239107
Directory /workspace/2.hmac_sec_cm/latest

Test location /workspace/coverage/default/2.hmac_smoke.1700453868
Short name T617
Test name
Test status
Simulation time 376979359 ps
CPU time 9.3 seconds
Started Jun 28 04:59:53 PM PDT 24
Finished Jun 28 05:00:04 PM PDT 24
Peak memory 200248 kb
Host smart-05d7fa63-4172-4104-99b1-75218dc8174b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700453868 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_smoke.1700453868
Directory /workspace/2.hmac_smoke/latest

Test location /workspace/coverage/default/2.hmac_test_hmac256_vectors.2831106815
Short name T518
Test name
Test status
Simulation time 4149326364 ps
CPU time 64.77 seconds
Started Jun 28 05:00:04 PM PDT 24
Finished Jun 28 05:01:10 PM PDT 24
Peak memory 200380 kb
Host smart-a7fca96e-e2b6-4af9-9553-d9a9ef31c175
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2831106815 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac256_vectors.2831106815
Directory /workspace/2.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac384_vectors.3770256148
Short name T270
Test name
Test status
Simulation time 10209732676 ps
CPU time 85.43 seconds
Started Jun 28 05:00:04 PM PDT 24
Finished Jun 28 05:01:30 PM PDT 24
Peak memory 200324 kb
Host smart-bcaf4cdc-5330-4e68-abad-98ea036757a2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3770256148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac384_vectors.3770256148
Directory /workspace/2.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_hmac512_vectors.3728433032
Short name T439
Test name
Test status
Simulation time 4705244048 ps
CPU time 57.19 seconds
Started Jun 28 05:00:05 PM PDT 24
Finished Jun 28 05:01:03 PM PDT 24
Peak memory 200280 kb
Host smart-f311d571-e194-4d5d-8c61-2e27d72d7171
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3728433032 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_hmac512_vectors.3728433032
Directory /workspace/2.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha256_vectors.1373640120
Short name T174
Test name
Test status
Simulation time 28330952799 ps
CPU time 402.94 seconds
Started Jun 28 05:00:03 PM PDT 24
Finished Jun 28 05:06:47 PM PDT 24
Peak memory 200264 kb
Host smart-5c30c9ef-c545-4d31-8f37-10385205d271
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1373640120 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha256_vectors.1373640120
Directory /workspace/2.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha384_vectors.2315053582
Short name T479
Test name
Test status
Simulation time 102737911019 ps
CPU time 1850.18 seconds
Started Jun 28 05:00:08 PM PDT 24
Finished Jun 28 05:30:59 PM PDT 24
Peak memory 215856 kb
Host smart-d5fae809-1588-4ba8-b10c-8183ab91f497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2315053582 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha384_vectors.2315053582
Directory /workspace/2.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/2.hmac_test_sha512_vectors.1022321220
Short name T434
Test name
Test status
Simulation time 445514403861 ps
CPU time 1826.9 seconds
Started Jun 28 05:00:09 PM PDT 24
Finished Jun 28 05:30:36 PM PDT 24
Peak memory 215932 kb
Host smart-b1c0135c-08c6-4a96-aa41-fbe74b253edc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1022321220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_test_sha512_vectors.1022321220
Directory /workspace/2.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/2.hmac_wipe_secret.3065666969
Short name T449
Test name
Test status
Simulation time 1844620439 ps
CPU time 33.56 seconds
Started Jun 28 04:59:53 PM PDT 24
Finished Jun 28 05:00:28 PM PDT 24
Peak memory 200308 kb
Host smart-60614c73-1dcc-47b9-9cff-e41515995f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065666969 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.hmac_wipe_secret.3065666969
Directory /workspace/2.hmac_wipe_secret/latest

Test location /workspace/coverage/default/20.hmac_alert_test.178814879
Short name T544
Test name
Test status
Simulation time 18643114 ps
CPU time 0.61 seconds
Started Jun 28 05:01:59 PM PDT 24
Finished Jun 28 05:02:00 PM PDT 24
Peak memory 196260 kb
Host smart-d49796b9-5b9b-4013-a707-1b78be001c61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178814879 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_alert_test.178814879
Directory /workspace/20.hmac_alert_test/latest

Test location /workspace/coverage/default/20.hmac_back_pressure.2791502201
Short name T354
Test name
Test status
Simulation time 995553861 ps
CPU time 47.72 seconds
Started Jun 28 05:01:57 PM PDT 24
Finished Jun 28 05:02:45 PM PDT 24
Peak memory 200280 kb
Host smart-3bc9f593-d884-4dce-99ec-b655f8e12b54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791502201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_back_pressure.2791502201
Directory /workspace/20.hmac_back_pressure/latest

Test location /workspace/coverage/default/20.hmac_burst_wr.3463135228
Short name T158
Test name
Test status
Simulation time 1815978271 ps
CPU time 24.14 seconds
Started Jun 28 05:01:47 PM PDT 24
Finished Jun 28 05:02:12 PM PDT 24
Peak memory 200244 kb
Host smart-15749ff8-0aad-4230-9c0e-12bdb9761bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463135228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_burst_wr.3463135228
Directory /workspace/20.hmac_burst_wr/latest

Test location /workspace/coverage/default/20.hmac_datapath_stress.2393040678
Short name T546
Test name
Test status
Simulation time 535897437 ps
CPU time 143.27 seconds
Started Jun 28 05:01:49 PM PDT 24
Finished Jun 28 05:04:13 PM PDT 24
Peak memory 437948 kb
Host smart-4e32fb16-a4a5-4d60-b298-efaa8d9e78af
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2393040678 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_datapath_stress.2393040678
Directory /workspace/20.hmac_datapath_stress/latest

Test location /workspace/coverage/default/20.hmac_error.3176643833
Short name T95
Test name
Test status
Simulation time 25844496366 ps
CPU time 195.44 seconds
Started Jun 28 05:01:56 PM PDT 24
Finished Jun 28 05:05:12 PM PDT 24
Peak memory 200324 kb
Host smart-c4948c01-2530-4e24-a3e0-b90c23b34588
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176643833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_error.3176643833
Directory /workspace/20.hmac_error/latest

Test location /workspace/coverage/default/20.hmac_long_msg.1281261516
Short name T769
Test name
Test status
Simulation time 9593072933 ps
CPU time 68.45 seconds
Started Jun 28 05:01:47 PM PDT 24
Finished Jun 28 05:02:56 PM PDT 24
Peak memory 200480 kb
Host smart-30ed3f45-8d92-499b-8f27-60e17abed842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281261516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_long_msg.1281261516
Directory /workspace/20.hmac_long_msg/latest

Test location /workspace/coverage/default/20.hmac_smoke.220213344
Short name T742
Test name
Test status
Simulation time 16585281 ps
CPU time 0.83 seconds
Started Jun 28 05:01:48 PM PDT 24
Finished Jun 28 05:01:50 PM PDT 24
Peak memory 198824 kb
Host smart-9646e2ad-9657-46ab-996c-41abe49f4d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220213344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_smoke.220213344
Directory /workspace/20.hmac_smoke/latest

Test location /workspace/coverage/default/20.hmac_test_hmac256_vectors.1084828823
Short name T520
Test name
Test status
Simulation time 15214219940 ps
CPU time 62.13 seconds
Started Jun 28 05:02:03 PM PDT 24
Finished Jun 28 05:03:06 PM PDT 24
Peak memory 200324 kb
Host smart-42189e81-645a-4e68-8799-0644dd87256d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1084828823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac256_vectors.1084828823
Directory /workspace/20.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_hmac384_vectors.2815673441
Short name T693
Test name
Test status
Simulation time 7650206832 ps
CPU time 87.57 seconds
Started Jun 28 05:01:58 PM PDT 24
Finished Jun 28 05:03:26 PM PDT 24
Peak memory 200324 kb
Host smart-2e5db95c-8424-4c1c-9325-193ef46c575e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2815673441 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac384_vectors.2815673441
Directory /workspace/20.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_hmac512_vectors.625360577
Short name T164
Test name
Test status
Simulation time 2643422987 ps
CPU time 96.53 seconds
Started Jun 28 05:01:58 PM PDT 24
Finished Jun 28 05:03:35 PM PDT 24
Peak memory 200328 kb
Host smart-46bad0fc-9ef3-4fea-bbd6-fcc72100dc97
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=625360577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_hmac512_vectors.625360577
Directory /workspace/20.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha256_vectors.1769694900
Short name T195
Test name
Test status
Simulation time 8195444630 ps
CPU time 447.43 seconds
Started Jun 28 05:01:48 PM PDT 24
Finished Jun 28 05:09:16 PM PDT 24
Peak memory 200260 kb
Host smart-1c9436ee-8816-412b-bf82-ef628b51729f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1769694900 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha256_vectors.1769694900
Directory /workspace/20.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha384_vectors.2781876641
Short name T397
Test name
Test status
Simulation time 30079591144 ps
CPU time 1686.24 seconds
Started Jun 28 05:01:58 PM PDT 24
Finished Jun 28 05:30:05 PM PDT 24
Peak memory 215676 kb
Host smart-fcdf6715-47d2-403c-b789-27ef3f2233db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2781876641 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha384_vectors.2781876641
Directory /workspace/20.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/20.hmac_test_sha512_vectors.2605123618
Short name T639
Test name
Test status
Simulation time 228793388428 ps
CPU time 2080.41 seconds
Started Jun 28 05:01:59 PM PDT 24
Finished Jun 28 05:36:40 PM PDT 24
Peak memory 216204 kb
Host smart-ab1c652a-e0c9-43c9-a6ec-67a8fc8768e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2605123618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_test_sha512_vectors.2605123618
Directory /workspace/20.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/20.hmac_wipe_secret.2320898117
Short name T607
Test name
Test status
Simulation time 2187912521 ps
CPU time 29.66 seconds
Started Jun 28 05:01:47 PM PDT 24
Finished Jun 28 05:02:17 PM PDT 24
Peak memory 200304 kb
Host smart-bf4022aa-f512-4444-8aad-7a4a73fffcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320898117 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.hmac_wipe_secret.2320898117
Directory /workspace/20.hmac_wipe_secret/latest

Test location /workspace/coverage/default/21.hmac_alert_test.2757865223
Short name T429
Test name
Test status
Simulation time 37595605 ps
CPU time 0.58 seconds
Started Jun 28 05:02:09 PM PDT 24
Finished Jun 28 05:02:10 PM PDT 24
Peak memory 196316 kb
Host smart-0348053a-776c-4bab-b0a2-c0221dd97ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757865223 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_alert_test.2757865223
Directory /workspace/21.hmac_alert_test/latest

Test location /workspace/coverage/default/21.hmac_back_pressure.1398167467
Short name T347
Test name
Test status
Simulation time 251289034 ps
CPU time 6.29 seconds
Started Jun 28 05:01:59 PM PDT 24
Finished Jun 28 05:02:06 PM PDT 24
Peak memory 200256 kb
Host smart-def28713-5a4d-4fa7-a2e7-9ba73fba53c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1398167467 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_back_pressure.1398167467
Directory /workspace/21.hmac_back_pressure/latest

Test location /workspace/coverage/default/21.hmac_burst_wr.2607487709
Short name T721
Test name
Test status
Simulation time 2989783560 ps
CPU time 23.23 seconds
Started Jun 28 05:01:59 PM PDT 24
Finished Jun 28 05:02:23 PM PDT 24
Peak memory 200268 kb
Host smart-4d8fb271-8d54-4ded-9ae4-e8da4dbaaaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607487709 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_burst_wr.2607487709
Directory /workspace/21.hmac_burst_wr/latest

Test location /workspace/coverage/default/21.hmac_datapath_stress.3641690829
Short name T673
Test name
Test status
Simulation time 2751013519 ps
CPU time 244.93 seconds
Started Jun 28 05:02:03 PM PDT 24
Finished Jun 28 05:06:09 PM PDT 24
Peak memory 607504 kb
Host smart-59f671bc-ec07-4e9f-a9b9-48361f766c4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3641690829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_datapath_stress.3641690829
Directory /workspace/21.hmac_datapath_stress/latest

Test location /workspace/coverage/default/21.hmac_error.670304570
Short name T2
Test name
Test status
Simulation time 11176086032 ps
CPU time 197.37 seconds
Started Jun 28 05:01:58 PM PDT 24
Finished Jun 28 05:05:16 PM PDT 24
Peak memory 200312 kb
Host smart-5636d3d5-276d-4c06-8334-0241c4e0e91c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670304570 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_error.670304570
Directory /workspace/21.hmac_error/latest

Test location /workspace/coverage/default/21.hmac_long_msg.1005823779
Short name T457
Test name
Test status
Simulation time 445649114 ps
CPU time 25.04 seconds
Started Jun 28 05:01:59 PM PDT 24
Finished Jun 28 05:02:24 PM PDT 24
Peak memory 200196 kb
Host smart-3bca6b72-6f15-4e24-b29c-f536a92c3050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005823779 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_long_msg.1005823779
Directory /workspace/21.hmac_long_msg/latest

Test location /workspace/coverage/default/21.hmac_smoke.4270916001
Short name T714
Test name
Test status
Simulation time 465773686 ps
CPU time 11.35 seconds
Started Jun 28 05:01:58 PM PDT 24
Finished Jun 28 05:02:10 PM PDT 24
Peak memory 200112 kb
Host smart-11f2c7c7-69c7-485f-b890-5af3ef5edb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270916001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_smoke.4270916001
Directory /workspace/21.hmac_smoke/latest

Test location /workspace/coverage/default/21.hmac_stress_all.3122340407
Short name T293
Test name
Test status
Simulation time 8282457733 ps
CPU time 105.02 seconds
Started Jun 28 05:02:10 PM PDT 24
Finished Jun 28 05:03:55 PM PDT 24
Peak memory 200288 kb
Host smart-0915ed17-6729-4390-ab86-a550f1cceac4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122340407 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.hmac_stress_all.3122340407
Directory /workspace/21.hmac_stress_all/latest

Test location /workspace/coverage/default/21.hmac_test_hmac256_vectors.4150102290
Short name T438
Test name
Test status
Simulation time 908408151 ps
CPU time 31 seconds
Started Jun 28 05:02:00 PM PDT 24
Finished Jun 28 05:02:31 PM PDT 24
Peak memory 200300 kb
Host smart-b7545572-27a9-46bb-8061-d7b2bdd6a18f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4150102290 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac256_vectors.4150102290
Directory /workspace/21.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_hmac384_vectors.397468391
Short name T588
Test name
Test status
Simulation time 1396662440 ps
CPU time 40.41 seconds
Started Jun 28 05:01:57 PM PDT 24
Finished Jun 28 05:02:39 PM PDT 24
Peak memory 200268 kb
Host smart-af4951e7-b3de-4f2c-a32c-0338af01214e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=397468391 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac384_vectors.397468391
Directory /workspace/21.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_hmac512_vectors.1296454773
Short name T15
Test name
Test status
Simulation time 15879385480 ps
CPU time 61.62 seconds
Started Jun 28 05:02:08 PM PDT 24
Finished Jun 28 05:03:11 PM PDT 24
Peak memory 200324 kb
Host smart-943170d4-7c1e-4ee1-85cf-216dd13b3ec3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1296454773 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_hmac512_vectors.1296454773
Directory /workspace/21.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha256_vectors.1387481823
Short name T190
Test name
Test status
Simulation time 59620389729 ps
CPU time 445.08 seconds
Started Jun 28 05:01:57 PM PDT 24
Finished Jun 28 05:09:23 PM PDT 24
Peak memory 200232 kb
Host smart-73904a70-4231-407c-bfa2-f51cc650bffe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1387481823 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha256_vectors.1387481823
Directory /workspace/21.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha384_vectors.2938105322
Short name T766
Test name
Test status
Simulation time 96459682836 ps
CPU time 1868.85 seconds
Started Jun 28 05:01:58 PM PDT 24
Finished Jun 28 05:33:08 PM PDT 24
Peak memory 216252 kb
Host smart-339c8ab1-2450-4e54-962d-7a69da4f3ae3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2938105322 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha384_vectors.2938105322
Directory /workspace/21.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/21.hmac_test_sha512_vectors.2096231425
Short name T326
Test name
Test status
Simulation time 111300609683 ps
CPU time 2042.79 seconds
Started Jun 28 05:01:58 PM PDT 24
Finished Jun 28 05:36:01 PM PDT 24
Peak memory 215956 kb
Host smart-d3bca98b-1740-460e-be4c-760e9f725ae1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2096231425 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_test_sha512_vectors.2096231425
Directory /workspace/21.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/21.hmac_wipe_secret.3235787066
Short name T398
Test name
Test status
Simulation time 932852356 ps
CPU time 16.47 seconds
Started Jun 28 05:02:03 PM PDT 24
Finished Jun 28 05:02:20 PM PDT 24
Peak memory 200280 kb
Host smart-f2495511-71ee-4391-b401-7385fc94fef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235787066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.hmac_wipe_secret.3235787066
Directory /workspace/21.hmac_wipe_secret/latest

Test location /workspace/coverage/default/22.hmac_alert_test.3507431000
Short name T581
Test name
Test status
Simulation time 250983728 ps
CPU time 0.6 seconds
Started Jun 28 05:02:20 PM PDT 24
Finished Jun 28 05:02:22 PM PDT 24
Peak memory 196224 kb
Host smart-5d230bbc-b3d2-477e-88e8-08d17198f6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507431000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_alert_test.3507431000
Directory /workspace/22.hmac_alert_test/latest

Test location /workspace/coverage/default/22.hmac_back_pressure.3168568966
Short name T311
Test name
Test status
Simulation time 385248379 ps
CPU time 17.73 seconds
Started Jun 28 05:02:08 PM PDT 24
Finished Jun 28 05:02:26 PM PDT 24
Peak memory 200304 kb
Host smart-6512f718-f6ae-43c6-b51e-268129113c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168568966 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_back_pressure.3168568966
Directory /workspace/22.hmac_back_pressure/latest

Test location /workspace/coverage/default/22.hmac_burst_wr.2101444323
Short name T83
Test name
Test status
Simulation time 1095252815 ps
CPU time 30.48 seconds
Started Jun 28 05:02:10 PM PDT 24
Finished Jun 28 05:02:41 PM PDT 24
Peak memory 200276 kb
Host smart-3f9eab26-d4da-4e13-8047-e83b6579e25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101444323 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_burst_wr.2101444323
Directory /workspace/22.hmac_burst_wr/latest

Test location /workspace/coverage/default/22.hmac_datapath_stress.918084524
Short name T614
Test name
Test status
Simulation time 749671242 ps
CPU time 112.76 seconds
Started Jun 28 05:02:08 PM PDT 24
Finished Jun 28 05:04:01 PM PDT 24
Peak memory 374092 kb
Host smart-450ba866-4126-4a5a-ac04-95ec97b32702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=918084524 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_datapath_stress.918084524
Directory /workspace/22.hmac_datapath_stress/latest

Test location /workspace/coverage/default/22.hmac_error.1776629236
Short name T99
Test name
Test status
Simulation time 736073337 ps
CPU time 42.57 seconds
Started Jun 28 05:02:08 PM PDT 24
Finished Jun 28 05:02:51 PM PDT 24
Peak memory 200456 kb
Host smart-a48fb7f8-171b-44af-afc8-7594f281bf9b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776629236 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_error.1776629236
Directory /workspace/22.hmac_error/latest

Test location /workspace/coverage/default/22.hmac_long_msg.3241692130
Short name T516
Test name
Test status
Simulation time 9452207632 ps
CPU time 70.38 seconds
Started Jun 28 05:02:13 PM PDT 24
Finished Jun 28 05:03:24 PM PDT 24
Peak memory 216616 kb
Host smart-093181af-c335-4b27-a5e1-5851b2e1fd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241692130 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_long_msg.3241692130
Directory /workspace/22.hmac_long_msg/latest

Test location /workspace/coverage/default/22.hmac_smoke.2224215053
Short name T482
Test name
Test status
Simulation time 43437851 ps
CPU time 1.78 seconds
Started Jun 28 05:02:13 PM PDT 24
Finished Jun 28 05:02:16 PM PDT 24
Peak memory 200320 kb
Host smart-525444e7-2e20-41b3-b7fc-f19de35923ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224215053 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_smoke.2224215053
Directory /workspace/22.hmac_smoke/latest

Test location /workspace/coverage/default/22.hmac_test_hmac256_vectors.1762005548
Short name T628
Test name
Test status
Simulation time 1686220202 ps
CPU time 29.56 seconds
Started Jun 28 05:02:11 PM PDT 24
Finished Jun 28 05:02:40 PM PDT 24
Peak memory 200208 kb
Host smart-a8a57e2a-3f92-4a91-96e5-66d807da6b70
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1762005548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac256_vectors.1762005548
Directory /workspace/22.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_hmac384_vectors.407514367
Short name T320
Test name
Test status
Simulation time 57720428100 ps
CPU time 44.73 seconds
Started Jun 28 05:02:11 PM PDT 24
Finished Jun 28 05:02:56 PM PDT 24
Peak memory 200360 kb
Host smart-62eeb567-42d0-48df-8cd7-94f84d031366
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=407514367 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac384_vectors.407514367
Directory /workspace/22.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_hmac512_vectors.1417444797
Short name T416
Test name
Test status
Simulation time 9337202410 ps
CPU time 73.17 seconds
Started Jun 28 05:02:08 PM PDT 24
Finished Jun 28 05:03:21 PM PDT 24
Peak memory 200324 kb
Host smart-d8e6a3e6-5cad-4d5a-aa22-6af1ae73c555
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1417444797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_hmac512_vectors.1417444797
Directory /workspace/22.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha256_vectors.2091844796
Short name T603
Test name
Test status
Simulation time 23685528614 ps
CPU time 419.97 seconds
Started Jun 28 05:02:13 PM PDT 24
Finished Jun 28 05:09:13 PM PDT 24
Peak memory 200260 kb
Host smart-67d49161-1c6d-494e-a0d9-2174c5d32be5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2091844796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha256_vectors.2091844796
Directory /workspace/22.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha384_vectors.1813632251
Short name T682
Test name
Test status
Simulation time 117281399501 ps
CPU time 1700.46 seconds
Started Jun 28 05:02:08 PM PDT 24
Finished Jun 28 05:30:30 PM PDT 24
Peak memory 215676 kb
Host smart-809bc222-e92e-4c69-a25f-d39fb741ba5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1813632251 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha384_vectors.1813632251
Directory /workspace/22.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/22.hmac_test_sha512_vectors.3283192703
Short name T510
Test name
Test status
Simulation time 107114732408 ps
CPU time 1629.94 seconds
Started Jun 28 05:02:10 PM PDT 24
Finished Jun 28 05:29:20 PM PDT 24
Peak memory 216240 kb
Host smart-6ec22139-4984-49b6-ae99-1369a7e386cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3283192703 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_test_sha512_vectors.3283192703
Directory /workspace/22.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/22.hmac_wipe_secret.3612790796
Short name T605
Test name
Test status
Simulation time 1579662269 ps
CPU time 18.49 seconds
Started Jun 28 05:02:09 PM PDT 24
Finished Jun 28 05:02:28 PM PDT 24
Peak memory 200244 kb
Host smart-786cfa91-f08a-4c05-875b-34c1a4e5cc50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612790796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.hmac_wipe_secret.3612790796
Directory /workspace/22.hmac_wipe_secret/latest

Test location /workspace/coverage/default/23.hmac_alert_test.4032838316
Short name T461
Test name
Test status
Simulation time 190785569 ps
CPU time 0.56 seconds
Started Jun 28 05:02:21 PM PDT 24
Finished Jun 28 05:02:22 PM PDT 24
Peak memory 196308 kb
Host smart-f72a411c-2d80-402e-908c-b651d2e872f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032838316 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_alert_test.4032838316
Directory /workspace/23.hmac_alert_test/latest

Test location /workspace/coverage/default/23.hmac_back_pressure.3024179661
Short name T783
Test name
Test status
Simulation time 621118011 ps
CPU time 26.58 seconds
Started Jun 28 05:02:21 PM PDT 24
Finished Jun 28 05:02:48 PM PDT 24
Peak memory 200212 kb
Host smart-956c0372-efda-4bfc-95d9-0ad3fe626c25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3024179661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_back_pressure.3024179661
Directory /workspace/23.hmac_back_pressure/latest

Test location /workspace/coverage/default/23.hmac_burst_wr.223903843
Short name T790
Test name
Test status
Simulation time 2015338088 ps
CPU time 33.15 seconds
Started Jun 28 05:02:22 PM PDT 24
Finished Jun 28 05:02:56 PM PDT 24
Peak memory 200280 kb
Host smart-5946fedb-a56c-407e-bb04-e287d4f8fe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223903843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_burst_wr.223903843
Directory /workspace/23.hmac_burst_wr/latest

Test location /workspace/coverage/default/23.hmac_datapath_stress.3284375797
Short name T465
Test name
Test status
Simulation time 2103277953 ps
CPU time 100.44 seconds
Started Jun 28 05:02:20 PM PDT 24
Finished Jun 28 05:04:01 PM PDT 24
Peak memory 350984 kb
Host smart-7c03411a-ff1c-4528-9d7d-7f624a1e0e1c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3284375797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_datapath_stress.3284375797
Directory /workspace/23.hmac_datapath_stress/latest

Test location /workspace/coverage/default/23.hmac_error.2808800292
Short name T691
Test name
Test status
Simulation time 1065005649 ps
CPU time 17.62 seconds
Started Jun 28 05:02:22 PM PDT 24
Finished Jun 28 05:02:40 PM PDT 24
Peak memory 200132 kb
Host smart-a0506288-bedf-4c0f-9316-61f85e19895e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808800292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_error.2808800292
Directory /workspace/23.hmac_error/latest

Test location /workspace/coverage/default/23.hmac_long_msg.3012695206
Short name T723
Test name
Test status
Simulation time 1678495948 ps
CPU time 16.78 seconds
Started Jun 28 05:02:21 PM PDT 24
Finished Jun 28 05:02:38 PM PDT 24
Peak memory 200328 kb
Host smart-169ce90e-45d6-484d-8b0a-be964f5d9a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012695206 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_long_msg.3012695206
Directory /workspace/23.hmac_long_msg/latest

Test location /workspace/coverage/default/23.hmac_smoke.2696194729
Short name T37
Test name
Test status
Simulation time 189552690 ps
CPU time 2.48 seconds
Started Jun 28 05:02:20 PM PDT 24
Finished Jun 28 05:02:24 PM PDT 24
Peak memory 200264 kb
Host smart-3805f297-8b6d-4fcf-8035-6c5d71b29c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696194729 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_smoke.2696194729
Directory /workspace/23.hmac_smoke/latest

Test location /workspace/coverage/default/23.hmac_stress_all.4053527921
Short name T54
Test name
Test status
Simulation time 22296512 ps
CPU time 0.62 seconds
Started Jun 28 05:02:22 PM PDT 24
Finished Jun 28 05:02:23 PM PDT 24
Peak memory 195892 kb
Host smart-1f33b78a-ceac-41bd-9b29-e37d13d2dca8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053527921 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.hmac_stress_all.4053527921
Directory /workspace/23.hmac_stress_all/latest

Test location /workspace/coverage/default/23.hmac_test_hmac256_vectors.3428149799
Short name T690
Test name
Test status
Simulation time 1383631338 ps
CPU time 54.01 seconds
Started Jun 28 05:02:22 PM PDT 24
Finished Jun 28 05:03:16 PM PDT 24
Peak memory 200272 kb
Host smart-8c959075-c3e9-4136-88f0-32d1e0232c3b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3428149799 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac256_vectors.3428149799
Directory /workspace/23.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_hmac384_vectors.3602427360
Short name T687
Test name
Test status
Simulation time 12153855241 ps
CPU time 85.72 seconds
Started Jun 28 05:02:20 PM PDT 24
Finished Jun 28 05:03:47 PM PDT 24
Peak memory 200360 kb
Host smart-02e80fb0-9966-4681-8a07-6ca1a31ede5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3602427360 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac384_vectors.3602427360
Directory /workspace/23.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_hmac512_vectors.1780581896
Short name T337
Test name
Test status
Simulation time 3928969996 ps
CPU time 56.07 seconds
Started Jun 28 05:02:21 PM PDT 24
Finished Jun 28 05:03:18 PM PDT 24
Peak memory 200328 kb
Host smart-5d93caac-8238-4f7d-bc80-c8101a17d63b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1780581896 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_hmac512_vectors.1780581896
Directory /workspace/23.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha256_vectors.714360296
Short name T53
Test name
Test status
Simulation time 24942348828 ps
CPU time 472.49 seconds
Started Jun 28 05:02:22 PM PDT 24
Finished Jun 28 05:10:15 PM PDT 24
Peak memory 200260 kb
Host smart-1bc2e66e-fc9c-4835-bf66-78fb8d38f4af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=714360296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha256_vectors.714360296
Directory /workspace/23.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha384_vectors.1849755420
Short name T271
Test name
Test status
Simulation time 42011933262 ps
CPU time 1710.65 seconds
Started Jun 28 05:02:21 PM PDT 24
Finished Jun 28 05:30:53 PM PDT 24
Peak memory 215600 kb
Host smart-db008d77-10cb-422a-967b-4e8720660128
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1849755420 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha384_vectors.1849755420
Directory /workspace/23.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/23.hmac_test_sha512_vectors.2891446222
Short name T390
Test name
Test status
Simulation time 151183344114 ps
CPU time 1871.18 seconds
Started Jun 28 05:02:20 PM PDT 24
Finished Jun 28 05:33:31 PM PDT 24
Peak memory 216816 kb
Host smart-56dc7b12-b1d5-4d87-b958-289752088cff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2891446222 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_test_sha512_vectors.2891446222
Directory /workspace/23.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/23.hmac_wipe_secret.1940181421
Short name T79
Test name
Test status
Simulation time 1476237597 ps
CPU time 67.59 seconds
Started Jun 28 05:02:21 PM PDT 24
Finished Jun 28 05:03:29 PM PDT 24
Peak memory 200288 kb
Host smart-c2b95cfb-85ee-4701-90cb-c720c128190c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940181421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.hmac_wipe_secret.1940181421
Directory /workspace/23.hmac_wipe_secret/latest

Test location /workspace/coverage/default/24.hmac_alert_test.1942645757
Short name T446
Test name
Test status
Simulation time 21533975 ps
CPU time 0.59 seconds
Started Jun 28 05:02:31 PM PDT 24
Finished Jun 28 05:02:32 PM PDT 24
Peak memory 195216 kb
Host smart-97a851c6-188f-46cb-ae28-99fec9c44d7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942645757 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_alert_test.1942645757
Directory /workspace/24.hmac_alert_test/latest

Test location /workspace/coverage/default/24.hmac_back_pressure.2301159344
Short name T759
Test name
Test status
Simulation time 4014427927 ps
CPU time 38.68 seconds
Started Jun 28 05:02:30 PM PDT 24
Finished Jun 28 05:03:09 PM PDT 24
Peak memory 200360 kb
Host smart-8395aaa1-d722-44b1-874f-980929e4d5bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2301159344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_back_pressure.2301159344
Directory /workspace/24.hmac_back_pressure/latest

Test location /workspace/coverage/default/24.hmac_burst_wr.1653682818
Short name T535
Test name
Test status
Simulation time 687442299 ps
CPU time 34.85 seconds
Started Jun 28 05:02:36 PM PDT 24
Finished Jun 28 05:03:11 PM PDT 24
Peak memory 200320 kb
Host smart-fecb757b-651a-44e9-a6d0-c660cf3f14b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653682818 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_burst_wr.1653682818
Directory /workspace/24.hmac_burst_wr/latest

Test location /workspace/coverage/default/24.hmac_datapath_stress.4029800748
Short name T252
Test name
Test status
Simulation time 1939526735 ps
CPU time 481.05 seconds
Started Jun 28 05:02:34 PM PDT 24
Finished Jun 28 05:10:36 PM PDT 24
Peak memory 647756 kb
Host smart-35e6be98-da9e-42dc-b7c1-54e705b6ecd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4029800748 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_datapath_stress.4029800748
Directory /workspace/24.hmac_datapath_stress/latest

Test location /workspace/coverage/default/24.hmac_error.4181936141
Short name T319
Test name
Test status
Simulation time 3023383995 ps
CPU time 43.98 seconds
Started Jun 28 05:02:32 PM PDT 24
Finished Jun 28 05:03:16 PM PDT 24
Peak memory 200264 kb
Host smart-ad9a1918-43ef-454e-8e23-3bcbe4d42a74
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181936141 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_error.4181936141
Directory /workspace/24.hmac_error/latest

Test location /workspace/coverage/default/24.hmac_long_msg.1210662362
Short name T353
Test name
Test status
Simulation time 3412287638 ps
CPU time 32.94 seconds
Started Jun 28 05:02:20 PM PDT 24
Finished Jun 28 05:02:54 PM PDT 24
Peak memory 200340 kb
Host smart-7fb64871-dc3b-4dfd-ab0e-3f91175a13b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210662362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_long_msg.1210662362
Directory /workspace/24.hmac_long_msg/latest

Test location /workspace/coverage/default/24.hmac_smoke.2111130810
Short name T593
Test name
Test status
Simulation time 290333798 ps
CPU time 3.15 seconds
Started Jun 28 05:02:23 PM PDT 24
Finished Jun 28 05:02:26 PM PDT 24
Peak memory 200320 kb
Host smart-0848b3a2-44cd-484f-8bd8-a3de8cb4b298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111130810 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_smoke.2111130810
Directory /workspace/24.hmac_smoke/latest

Test location /workspace/coverage/default/24.hmac_test_hmac256_vectors.3243317213
Short name T531
Test name
Test status
Simulation time 904588858 ps
CPU time 29.34 seconds
Started Jun 28 05:02:32 PM PDT 24
Finished Jun 28 05:03:03 PM PDT 24
Peak memory 200160 kb
Host smart-695116cf-858f-48ba-a308-10e8f3f20c3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3243317213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac256_vectors.3243317213
Directory /workspace/24.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_hmac384_vectors.4042318045
Short name T686
Test name
Test status
Simulation time 5676265376 ps
CPU time 39.73 seconds
Started Jun 28 05:02:34 PM PDT 24
Finished Jun 28 05:03:14 PM PDT 24
Peak memory 200360 kb
Host smart-c212b10d-ac0a-4856-b174-111bcb47b503
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4042318045 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac384_vectors.4042318045
Directory /workspace/24.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_hmac512_vectors.1585099623
Short name T498
Test name
Test status
Simulation time 6757227146 ps
CPU time 103.14 seconds
Started Jun 28 05:02:34 PM PDT 24
Finished Jun 28 05:04:18 PM PDT 24
Peak memory 200344 kb
Host smart-fa3609db-a10a-496c-83a8-648a7780825b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1585099623 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_hmac512_vectors.1585099623
Directory /workspace/24.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha256_vectors.644587066
Short name T536
Test name
Test status
Simulation time 26900544604 ps
CPU time 450.76 seconds
Started Jun 28 05:02:32 PM PDT 24
Finished Jun 28 05:10:04 PM PDT 24
Peak memory 200200 kb
Host smart-c5ef79d1-7b97-4dff-972a-f34eefda4de4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=644587066 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha256_vectors.644587066
Directory /workspace/24.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha384_vectors.2474750359
Short name T447
Test name
Test status
Simulation time 129259163288 ps
CPU time 1864.41 seconds
Started Jun 28 05:02:34 PM PDT 24
Finished Jun 28 05:33:39 PM PDT 24
Peak memory 215804 kb
Host smart-c4c9526e-b8ed-466f-9082-2caeae18d4ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2474750359 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha384_vectors.2474750359
Directory /workspace/24.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/24.hmac_test_sha512_vectors.3495791335
Short name T279
Test name
Test status
Simulation time 113999525796 ps
CPU time 2121.82 seconds
Started Jun 28 05:02:33 PM PDT 24
Finished Jun 28 05:37:56 PM PDT 24
Peak memory 216596 kb
Host smart-7e96c881-863e-4a35-962c-bbae22f3d4a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3495791335 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_test_sha512_vectors.3495791335
Directory /workspace/24.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/24.hmac_wipe_secret.670555170
Short name T210
Test name
Test status
Simulation time 459163405 ps
CPU time 10.81 seconds
Started Jun 28 05:02:32 PM PDT 24
Finished Jun 28 05:02:43 PM PDT 24
Peak memory 200316 kb
Host smart-9f2ec236-f816-4972-9215-34cd81c3bc9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670555170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.hmac_wipe_secret.670555170
Directory /workspace/24.hmac_wipe_secret/latest

Test location /workspace/coverage/default/25.hmac_alert_test.2393645994
Short name T674
Test name
Test status
Simulation time 27115261 ps
CPU time 0.59 seconds
Started Jun 28 05:02:50 PM PDT 24
Finished Jun 28 05:02:51 PM PDT 24
Peak memory 196332 kb
Host smart-f8fee9b7-a2ba-41b2-a579-cc5f4b2bcb19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393645994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_alert_test.2393645994
Directory /workspace/25.hmac_alert_test/latest

Test location /workspace/coverage/default/25.hmac_back_pressure.2254381152
Short name T358
Test name
Test status
Simulation time 389362148 ps
CPU time 5.04 seconds
Started Jun 28 05:02:33 PM PDT 24
Finished Jun 28 05:02:39 PM PDT 24
Peak memory 200256 kb
Host smart-0fa5a018-65d1-4a3e-bd52-db0828b30e88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2254381152 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_back_pressure.2254381152
Directory /workspace/25.hmac_back_pressure/latest

Test location /workspace/coverage/default/25.hmac_burst_wr.3041038183
Short name T474
Test name
Test status
Simulation time 23432998327 ps
CPU time 76.89 seconds
Started Jun 28 05:02:34 PM PDT 24
Finished Jun 28 05:03:52 PM PDT 24
Peak memory 200320 kb
Host smart-2b8b90f7-74c9-40b5-a0af-c5c8ec1e655d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041038183 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_burst_wr.3041038183
Directory /workspace/25.hmac_burst_wr/latest

Test location /workspace/coverage/default/25.hmac_datapath_stress.80303738
Short name T146
Test name
Test status
Simulation time 35723865313 ps
CPU time 534.79 seconds
Started Jun 28 05:02:36 PM PDT 24
Finished Jun 28 05:11:32 PM PDT 24
Peak memory 658372 kb
Host smart-de0e486a-1b02-4e7f-af16-97b2bc705daf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80303738 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_datapath_stress.80303738
Directory /workspace/25.hmac_datapath_stress/latest

Test location /workspace/coverage/default/25.hmac_error.115975220
Short name T215
Test name
Test status
Simulation time 2748487790 ps
CPU time 51.89 seconds
Started Jun 28 05:02:31 PM PDT 24
Finished Jun 28 05:03:24 PM PDT 24
Peak memory 200576 kb
Host smart-9fd65764-f29c-4ff4-adf7-7360d9cc0292
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115975220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_error.115975220
Directory /workspace/25.hmac_error/latest

Test location /workspace/coverage/default/25.hmac_long_msg.4272304500
Short name T615
Test name
Test status
Simulation time 4516463545 ps
CPU time 86.24 seconds
Started Jun 28 05:02:32 PM PDT 24
Finished Jun 28 05:04:00 PM PDT 24
Peak memory 200340 kb
Host smart-c088cde1-1991-4afb-8508-f74130ab0d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272304500 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_long_msg.4272304500
Directory /workspace/25.hmac_long_msg/latest

Test location /workspace/coverage/default/25.hmac_smoke.2207724677
Short name T328
Test name
Test status
Simulation time 18700217 ps
CPU time 1.13 seconds
Started Jun 28 05:02:33 PM PDT 24
Finished Jun 28 05:02:35 PM PDT 24
Peak memory 199940 kb
Host smart-491daa04-b0cd-4b3b-826c-6d0ac0627977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207724677 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_smoke.2207724677
Directory /workspace/25.hmac_smoke/latest

Test location /workspace/coverage/default/25.hmac_stress_all.3082673375
Short name T626
Test name
Test status
Simulation time 275142471515 ps
CPU time 4184.55 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 06:12:34 PM PDT 24
Peak memory 698716 kb
Host smart-f4eafa56-9da3-42fd-85c5-41d69cde1bd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082673375 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.hmac_stress_all.3082673375
Directory /workspace/25.hmac_stress_all/latest

Test location /workspace/coverage/default/25.hmac_test_hmac256_vectors.1399877884
Short name T356
Test name
Test status
Simulation time 21053475472 ps
CPU time 68.95 seconds
Started Jun 28 05:02:32 PM PDT 24
Finished Jun 28 05:03:42 PM PDT 24
Peak memory 200324 kb
Host smart-97325172-733d-492b-827c-de8c085f25c2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1399877884 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac256_vectors.1399877884
Directory /workspace/25.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_hmac384_vectors.399035918
Short name T375
Test name
Test status
Simulation time 29845714728 ps
CPU time 87.52 seconds
Started Jun 28 05:02:33 PM PDT 24
Finished Jun 28 05:04:01 PM PDT 24
Peak memory 200324 kb
Host smart-f5abef18-e7ec-4801-9dc3-0166d13d1845
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=399035918 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac384_vectors.399035918
Directory /workspace/25.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_hmac512_vectors.1970414068
Short name T425
Test name
Test status
Simulation time 3749000925 ps
CPU time 52.62 seconds
Started Jun 28 05:02:36 PM PDT 24
Finished Jun 28 05:03:29 PM PDT 24
Peak memory 200328 kb
Host smart-ceca1e39-a898-4fe6-99f2-09e0cda7ad48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1970414068 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_hmac512_vectors.1970414068
Directory /workspace/25.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha256_vectors.388144248
Short name T237
Test name
Test status
Simulation time 296225192862 ps
CPU time 487.53 seconds
Started Jun 28 05:02:34 PM PDT 24
Finished Jun 28 05:10:42 PM PDT 24
Peak memory 200188 kb
Host smart-0fa0fd06-23a6-4536-8289-6bd93067f71e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=388144248 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha256_vectors.388144248
Directory /workspace/25.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha384_vectors.3422482272
Short name T584
Test name
Test status
Simulation time 294150688525 ps
CPU time 1547.19 seconds
Started Jun 28 05:02:31 PM PDT 24
Finished Jun 28 05:28:19 PM PDT 24
Peak memory 216628 kb
Host smart-bea4ede5-b4e7-4eb1-9347-521e5f25ca3a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3422482272 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha384_vectors.3422482272
Directory /workspace/25.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/25.hmac_test_sha512_vectors.3792532965
Short name T150
Test name
Test status
Simulation time 572461596087 ps
CPU time 2020.51 seconds
Started Jun 28 05:02:33 PM PDT 24
Finished Jun 28 05:36:15 PM PDT 24
Peak memory 216164 kb
Host smart-07d46169-8335-43fe-9606-76a4178906bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3792532965 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_test_sha512_vectors.3792532965
Directory /workspace/25.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/25.hmac_wipe_secret.3008582294
Short name T333
Test name
Test status
Simulation time 6705570706 ps
CPU time 15.34 seconds
Started Jun 28 05:02:34 PM PDT 24
Finished Jun 28 05:02:50 PM PDT 24
Peak memory 200276 kb
Host smart-9501edd2-22d6-4129-96ac-e0913602f96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008582294 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.hmac_wipe_secret.3008582294
Directory /workspace/25.hmac_wipe_secret/latest

Test location /workspace/coverage/default/26.hmac_alert_test.1782904119
Short name T17
Test name
Test status
Simulation time 50156059 ps
CPU time 0.6 seconds
Started Jun 28 05:02:49 PM PDT 24
Finished Jun 28 05:02:50 PM PDT 24
Peak memory 196996 kb
Host smart-7423e40c-69e5-4f47-8b22-6618a6aac035
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782904119 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_alert_test.1782904119
Directory /workspace/26.hmac_alert_test/latest

Test location /workspace/coverage/default/26.hmac_back_pressure.2261319331
Short name T16
Test name
Test status
Simulation time 1574687829 ps
CPU time 4.58 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 05:02:53 PM PDT 24
Peak memory 200260 kb
Host smart-934eecd2-2e50-4f35-9c19-b75efbe24032
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2261319331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_back_pressure.2261319331
Directory /workspace/26.hmac_back_pressure/latest

Test location /workspace/coverage/default/26.hmac_burst_wr.554174601
Short name T750
Test name
Test status
Simulation time 77762944 ps
CPU time 2.16 seconds
Started Jun 28 05:02:50 PM PDT 24
Finished Jun 28 05:02:52 PM PDT 24
Peak memory 200212 kb
Host smart-388a912c-e23e-4d5c-aabc-665f666a1dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554174601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_burst_wr.554174601
Directory /workspace/26.hmac_burst_wr/latest

Test location /workspace/coverage/default/26.hmac_datapath_stress.3012079908
Short name T140
Test name
Test status
Simulation time 2184342537 ps
CPU time 321.97 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 05:08:11 PM PDT 24
Peak memory 667624 kb
Host smart-a188eae7-4cb3-4bcd-b46d-da51ef95832e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3012079908 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_datapath_stress.3012079908
Directory /workspace/26.hmac_datapath_stress/latest

Test location /workspace/coverage/default/26.hmac_error.953486803
Short name T137
Test name
Test status
Simulation time 3663447369 ps
CPU time 197.88 seconds
Started Jun 28 05:02:47 PM PDT 24
Finished Jun 28 05:06:05 PM PDT 24
Peak memory 200248 kb
Host smart-f26a22de-de7f-41aa-9f9c-4f86bcbfe8f3
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953486803 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_error.953486803
Directory /workspace/26.hmac_error/latest

Test location /workspace/coverage/default/26.hmac_long_msg.442781611
Short name T708
Test name
Test status
Simulation time 734636070 ps
CPU time 46.53 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 05:03:36 PM PDT 24
Peak memory 200252 kb
Host smart-4380dba3-afa4-439d-a1f4-019d69cfd29f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442781611 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_long_msg.442781611
Directory /workspace/26.hmac_long_msg/latest

Test location /workspace/coverage/default/26.hmac_smoke.2263515821
Short name T307
Test name
Test status
Simulation time 148391083 ps
CPU time 2.19 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 05:02:51 PM PDT 24
Peak memory 200124 kb
Host smart-0ab9aa74-72ed-4e24-bd12-9e0e2915e712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263515821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_smoke.2263515821
Directory /workspace/26.hmac_smoke/latest

Test location /workspace/coverage/default/26.hmac_stress_all.3220067794
Short name T87
Test name
Test status
Simulation time 364336958266 ps
CPU time 5949.9 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 06:42:00 PM PDT 24
Peak memory 733836 kb
Host smart-54914c65-5abc-469f-8800-dab864f6a6ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220067794 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.hmac_stress_all.3220067794
Directory /workspace/26.hmac_stress_all/latest

Test location /workspace/coverage/default/26.hmac_test_hmac256_vectors.443268876
Short name T557
Test name
Test status
Simulation time 21245860091 ps
CPU time 34.7 seconds
Started Jun 28 05:02:47 PM PDT 24
Finished Jun 28 05:03:22 PM PDT 24
Peak memory 200236 kb
Host smart-baef9a25-f25f-4d7f-be35-001e12eb8186
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=443268876 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac256_vectors.443268876
Directory /workspace/26.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_hmac384_vectors.2824808490
Short name T202
Test name
Test status
Simulation time 5344311978 ps
CPU time 85.01 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 05:04:14 PM PDT 24
Peak memory 200324 kb
Host smart-f25c4598-d4d8-41e1-8c5d-86cbd0eb643c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2824808490 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac384_vectors.2824808490
Directory /workspace/26.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_hmac512_vectors.1654804101
Short name T551
Test name
Test status
Simulation time 15108710455 ps
CPU time 54.69 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 05:03:43 PM PDT 24
Peak memory 200324 kb
Host smart-8bcf75db-6e44-43ec-8f2a-12c43e223ce4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1654804101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_hmac512_vectors.1654804101
Directory /workspace/26.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha256_vectors.3279758140
Short name T561
Test name
Test status
Simulation time 264269185139 ps
CPU time 550.7 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 05:11:59 PM PDT 24
Peak memory 200192 kb
Host smart-f7be1343-6615-40cc-8897-7275a46bdc78
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3279758140 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha256_vectors.3279758140
Directory /workspace/26.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha384_vectors.2735174230
Short name T437
Test name
Test status
Simulation time 39041870346 ps
CPU time 1947.81 seconds
Started Jun 28 05:02:49 PM PDT 24
Finished Jun 28 05:35:17 PM PDT 24
Peak memory 216516 kb
Host smart-aceeb095-75aa-4138-a7c7-a153b2667bd8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2735174230 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha384_vectors.2735174230
Directory /workspace/26.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/26.hmac_test_sha512_vectors.3630230320
Short name T744
Test name
Test status
Simulation time 162550693244 ps
CPU time 2075.55 seconds
Started Jun 28 05:02:47 PM PDT 24
Finished Jun 28 05:37:23 PM PDT 24
Peak memory 208548 kb
Host smart-84ca4203-87ae-4413-b324-7c156e976d02
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3630230320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_test_sha512_vectors.3630230320
Directory /workspace/26.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/26.hmac_wipe_secret.1786439049
Short name T631
Test name
Test status
Simulation time 3864457071 ps
CPU time 15.01 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 05:03:04 PM PDT 24
Peak memory 200248 kb
Host smart-81cbcc63-a005-42b8-88f0-3ef0bdbc17bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786439049 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.hmac_wipe_secret.1786439049
Directory /workspace/26.hmac_wipe_secret/latest

Test location /workspace/coverage/default/27.hmac_alert_test.147521708
Short name T286
Test name
Test status
Simulation time 54820223 ps
CPU time 0.59 seconds
Started Jun 28 05:02:59 PM PDT 24
Finished Jun 28 05:03:00 PM PDT 24
Peak memory 196992 kb
Host smart-60761945-5f0c-4983-b917-3574b6cd2400
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147521708 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_alert_test.147521708
Directory /workspace/27.hmac_alert_test/latest

Test location /workspace/coverage/default/27.hmac_back_pressure.4046035701
Short name T380
Test name
Test status
Simulation time 2547380583 ps
CPU time 31.65 seconds
Started Jun 28 05:03:02 PM PDT 24
Finished Jun 28 05:03:34 PM PDT 24
Peak memory 200292 kb
Host smart-75a6f710-1323-45e0-9cc3-3824c6a8bb0a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046035701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_back_pressure.4046035701
Directory /workspace/27.hmac_back_pressure/latest

Test location /workspace/coverage/default/27.hmac_burst_wr.2917865768
Short name T395
Test name
Test status
Simulation time 1088735087 ps
CPU time 62.6 seconds
Started Jun 28 05:02:58 PM PDT 24
Finished Jun 28 05:04:02 PM PDT 24
Peak memory 200296 kb
Host smart-d57d43d1-d59b-4c5d-b019-8390e54adf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917865768 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_burst_wr.2917865768
Directory /workspace/27.hmac_burst_wr/latest

Test location /workspace/coverage/default/27.hmac_datapath_stress.530040380
Short name T213
Test name
Test status
Simulation time 3920432883 ps
CPU time 289.58 seconds
Started Jun 28 05:02:57 PM PDT 24
Finished Jun 28 05:07:48 PM PDT 24
Peak memory 687540 kb
Host smart-8286a2fc-6316-4a72-9f74-3fb52df44ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=530040380 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_datapath_stress.530040380
Directory /workspace/27.hmac_datapath_stress/latest

Test location /workspace/coverage/default/27.hmac_error.4039655170
Short name T186
Test name
Test status
Simulation time 4506609493 ps
CPU time 61.73 seconds
Started Jun 28 05:02:59 PM PDT 24
Finished Jun 28 05:04:01 PM PDT 24
Peak memory 200256 kb
Host smart-64737f36-0a00-444f-b182-1ef1dc4b5056
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039655170 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_error.4039655170
Directory /workspace/27.hmac_error/latest

Test location /workspace/coverage/default/27.hmac_long_msg.3270272661
Short name T594
Test name
Test status
Simulation time 6499307966 ps
CPU time 83.52 seconds
Started Jun 28 05:02:58 PM PDT 24
Finished Jun 28 05:04:22 PM PDT 24
Peak memory 200340 kb
Host smart-be15cd77-36aa-47f9-a9d4-d6c13b490f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270272661 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_long_msg.3270272661
Directory /workspace/27.hmac_long_msg/latest

Test location /workspace/coverage/default/27.hmac_smoke.1356668240
Short name T770
Test name
Test status
Simulation time 49963108 ps
CPU time 1.38 seconds
Started Jun 28 05:02:48 PM PDT 24
Finished Jun 28 05:02:50 PM PDT 24
Peak memory 200280 kb
Host smart-f8cea95a-1160-4da4-9537-65591d07aa6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356668240 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_smoke.1356668240
Directory /workspace/27.hmac_smoke/latest

Test location /workspace/coverage/default/27.hmac_stress_all.2075506995
Short name T670
Test name
Test status
Simulation time 10104332088 ps
CPU time 178.1 seconds
Started Jun 28 05:02:59 PM PDT 24
Finished Jun 28 05:05:58 PM PDT 24
Peak memory 216704 kb
Host smart-bc6d2c91-1a39-4995-beae-83bc5335cba0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075506995 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.hmac_stress_all.2075506995
Directory /workspace/27.hmac_stress_all/latest

Test location /workspace/coverage/default/27.hmac_test_hmac256_vectors.1748503201
Short name T731
Test name
Test status
Simulation time 3708214821 ps
CPU time 64.82 seconds
Started Jun 28 05:02:59 PM PDT 24
Finished Jun 28 05:04:05 PM PDT 24
Peak memory 200328 kb
Host smart-28785801-e52d-4cd0-9bbe-67296e9a3d4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1748503201 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac256_vectors.1748503201
Directory /workspace/27.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_hmac384_vectors.992542984
Short name T539
Test name
Test status
Simulation time 19526738878 ps
CPU time 98.61 seconds
Started Jun 28 05:02:58 PM PDT 24
Finished Jun 28 05:04:37 PM PDT 24
Peak memory 200328 kb
Host smart-8e648cd5-9335-448f-a8d1-758d159ed783
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=992542984 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac384_vectors.992542984
Directory /workspace/27.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_hmac512_vectors.3597563418
Short name T389
Test name
Test status
Simulation time 1882040240 ps
CPU time 53.18 seconds
Started Jun 28 05:02:58 PM PDT 24
Finished Jun 28 05:03:52 PM PDT 24
Peak memory 200264 kb
Host smart-2dc91d7d-74f8-41c6-9e92-712f29cfc423
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3597563418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_hmac512_vectors.3597563418
Directory /workspace/27.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha256_vectors.3569939189
Short name T511
Test name
Test status
Simulation time 15555108459 ps
CPU time 496.25 seconds
Started Jun 28 05:02:58 PM PDT 24
Finished Jun 28 05:11:15 PM PDT 24
Peak memory 200260 kb
Host smart-7212c788-1373-4a7a-a342-bdc049db610b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3569939189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha256_vectors.3569939189
Directory /workspace/27.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha384_vectors.3830679458
Short name T755
Test name
Test status
Simulation time 43467812760 ps
CPU time 1708.25 seconds
Started Jun 28 05:02:58 PM PDT 24
Finished Jun 28 05:31:27 PM PDT 24
Peak memory 215772 kb
Host smart-7aeb0b50-fb47-4288-949d-53437e4df221
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3830679458 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha384_vectors.3830679458
Directory /workspace/27.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/27.hmac_test_sha512_vectors.464222177
Short name T236
Test name
Test status
Simulation time 150057698974 ps
CPU time 2054.89 seconds
Started Jun 28 05:02:58 PM PDT 24
Finished Jun 28 05:37:14 PM PDT 24
Peak memory 215728 kb
Host smart-aa7a8b00-f777-45f9-acaa-25cb4483d665
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=464222177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_test_sha512_vectors.464222177
Directory /workspace/27.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/27.hmac_wipe_secret.2232700638
Short name T23
Test name
Test status
Simulation time 3733807883 ps
CPU time 55.42 seconds
Started Jun 28 05:02:58 PM PDT 24
Finished Jun 28 05:03:54 PM PDT 24
Peak memory 200380 kb
Host smart-60edefc0-ce34-44d0-8dc5-610158b0acfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232700638 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.hmac_wipe_secret.2232700638
Directory /workspace/27.hmac_wipe_secret/latest

Test location /workspace/coverage/default/28.hmac_alert_test.1512002674
Short name T78
Test name
Test status
Simulation time 14587003 ps
CPU time 0.59 seconds
Started Jun 28 05:03:10 PM PDT 24
Finished Jun 28 05:03:11 PM PDT 24
Peak memory 196284 kb
Host smart-b3450eb2-76c8-4cbc-ad7e-b4abbe2da1e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512002674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_alert_test.1512002674
Directory /workspace/28.hmac_alert_test/latest

Test location /workspace/coverage/default/28.hmac_back_pressure.4270476188
Short name T277
Test name
Test status
Simulation time 667943214 ps
CPU time 31.19 seconds
Started Jun 28 05:03:04 PM PDT 24
Finished Jun 28 05:03:35 PM PDT 24
Peak memory 200200 kb
Host smart-e541e291-1c25-48ad-83e6-675db00bc934
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4270476188 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_back_pressure.4270476188
Directory /workspace/28.hmac_back_pressure/latest

Test location /workspace/coverage/default/28.hmac_burst_wr.3592713946
Short name T157
Test name
Test status
Simulation time 120048396 ps
CPU time 6.55 seconds
Started Jun 28 05:02:59 PM PDT 24
Finished Jun 28 05:03:06 PM PDT 24
Peak memory 200196 kb
Host smart-a64d1203-ce62-4331-bbe6-246c8ce35174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592713946 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_burst_wr.3592713946
Directory /workspace/28.hmac_burst_wr/latest

Test location /workspace/coverage/default/28.hmac_datapath_stress.1813032527
Short name T532
Test name
Test status
Simulation time 1773950706 ps
CPU time 410.61 seconds
Started Jun 28 05:02:57 PM PDT 24
Finished Jun 28 05:09:49 PM PDT 24
Peak memory 692576 kb
Host smart-7559adbf-2e1b-4ae1-b0ea-0a25b3421f73
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1813032527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_datapath_stress.1813032527
Directory /workspace/28.hmac_datapath_stress/latest

Test location /workspace/coverage/default/28.hmac_error.3102907427
Short name T250
Test name
Test status
Simulation time 17042885108 ps
CPU time 69.7 seconds
Started Jun 28 05:03:03 PM PDT 24
Finished Jun 28 05:04:13 PM PDT 24
Peak memory 200248 kb
Host smart-d2ed1d64-bb44-4a57-82ae-a90f4334315c
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102907427 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_error.3102907427
Directory /workspace/28.hmac_error/latest

Test location /workspace/coverage/default/28.hmac_long_msg.4151445650
Short name T379
Test name
Test status
Simulation time 18560992183 ps
CPU time 112.5 seconds
Started Jun 28 05:02:58 PM PDT 24
Finished Jun 28 05:04:51 PM PDT 24
Peak memory 200336 kb
Host smart-038c39ed-57ab-45f8-906f-b153563ea19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151445650 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_long_msg.4151445650
Directory /workspace/28.hmac_long_msg/latest

Test location /workspace/coverage/default/28.hmac_smoke.2891030278
Short name T754
Test name
Test status
Simulation time 157118793 ps
CPU time 7.46 seconds
Started Jun 28 05:02:59 PM PDT 24
Finished Jun 28 05:03:07 PM PDT 24
Peak memory 200284 kb
Host smart-9777eb91-6c21-4047-946e-ebcd0570426a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891030278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_smoke.2891030278
Directory /workspace/28.hmac_smoke/latest

Test location /workspace/coverage/default/28.hmac_stress_all.1440786501
Short name T765
Test name
Test status
Simulation time 19201707705 ps
CPU time 1386.54 seconds
Started Jun 28 05:03:15 PM PDT 24
Finished Jun 28 05:26:22 PM PDT 24
Peak memory 665800 kb
Host smart-adbfb8a2-b9e6-407e-8cb9-ffd212ba43a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440786501 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.hmac_stress_all.1440786501
Directory /workspace/28.hmac_stress_all/latest

Test location /workspace/coverage/default/28.hmac_test_hmac256_vectors.1516468340
Short name T214
Test name
Test status
Simulation time 17197393327 ps
CPU time 59.35 seconds
Started Jun 28 05:02:57 PM PDT 24
Finished Jun 28 05:03:58 PM PDT 24
Peak memory 200244 kb
Host smart-221da5e2-e868-458f-9aaf-66b9ac7fe167
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1516468340 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac256_vectors.1516468340
Directory /workspace/28.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_hmac384_vectors.833624800
Short name T406
Test name
Test status
Simulation time 5241684573 ps
CPU time 74.65 seconds
Started Jun 28 05:02:58 PM PDT 24
Finished Jun 28 05:04:13 PM PDT 24
Peak memory 200332 kb
Host smart-357a25ec-6633-4885-bebd-e02a8415378d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=833624800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac384_vectors.833624800
Directory /workspace/28.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_hmac512_vectors.4074243728
Short name T563
Test name
Test status
Simulation time 21874078778 ps
CPU time 61.04 seconds
Started Jun 28 05:03:11 PM PDT 24
Finished Jun 28 05:04:13 PM PDT 24
Peak memory 200324 kb
Host smart-01e9d9a7-757d-4d6e-950d-368a4d25a56b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4074243728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_hmac512_vectors.4074243728
Directory /workspace/28.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha256_vectors.737940016
Short name T246
Test name
Test status
Simulation time 32259488291 ps
CPU time 451.01 seconds
Started Jun 28 05:02:59 PM PDT 24
Finished Jun 28 05:10:31 PM PDT 24
Peak memory 200292 kb
Host smart-6932692d-6692-4b1c-a1d6-996a02cb21d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=737940016 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha256_vectors.737940016
Directory /workspace/28.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha384_vectors.2552825415
Short name T422
Test name
Test status
Simulation time 34998627053 ps
CPU time 1777.6 seconds
Started Jun 28 05:03:03 PM PDT 24
Finished Jun 28 05:32:41 PM PDT 24
Peak memory 216568 kb
Host smart-ce0619e6-e82f-4853-8670-94ae03bc4141
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2552825415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha384_vectors.2552825415
Directory /workspace/28.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/28.hmac_test_sha512_vectors.1859550254
Short name T240
Test name
Test status
Simulation time 175918404372 ps
CPU time 2106.28 seconds
Started Jun 28 05:02:59 PM PDT 24
Finished Jun 28 05:38:06 PM PDT 24
Peak memory 215836 kb
Host smart-a54da8e1-8b0c-44ff-80fa-4a313b01b4c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1859550254 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_test_sha512_vectors.1859550254
Directory /workspace/28.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/28.hmac_wipe_secret.4128108731
Short name T515
Test name
Test status
Simulation time 2832475028 ps
CPU time 58.76 seconds
Started Jun 28 05:02:59 PM PDT 24
Finished Jun 28 05:03:58 PM PDT 24
Peak memory 200308 kb
Host smart-870a91b6-9662-46cd-9b97-d97eb47d1e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128108731 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.hmac_wipe_secret.4128108731
Directory /workspace/28.hmac_wipe_secret/latest

Test location /workspace/coverage/default/29.hmac_alert_test.1117323357
Short name T789
Test name
Test status
Simulation time 24072382 ps
CPU time 0.59 seconds
Started Jun 28 05:03:11 PM PDT 24
Finished Jun 28 05:03:12 PM PDT 24
Peak memory 196920 kb
Host smart-9d883689-0f24-427c-94ad-311bb5cbb36a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117323357 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_alert_test.1117323357
Directory /workspace/29.hmac_alert_test/latest

Test location /workspace/coverage/default/29.hmac_back_pressure.1900493446
Short name T478
Test name
Test status
Simulation time 494593823 ps
CPU time 27.13 seconds
Started Jun 28 05:03:12 PM PDT 24
Finished Jun 28 05:03:40 PM PDT 24
Peak memory 200264 kb
Host smart-4fd48fec-3a30-4ebe-b0d2-38e43e071f07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1900493446 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_back_pressure.1900493446
Directory /workspace/29.hmac_back_pressure/latest

Test location /workspace/coverage/default/29.hmac_burst_wr.3412620215
Short name T346
Test name
Test status
Simulation time 2792142715 ps
CPU time 51.94 seconds
Started Jun 28 05:03:11 PM PDT 24
Finished Jun 28 05:04:04 PM PDT 24
Peak memory 200340 kb
Host smart-8f58815d-c2c7-4c8a-964c-537a25acc0ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412620215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_burst_wr.3412620215
Directory /workspace/29.hmac_burst_wr/latest

Test location /workspace/coverage/default/29.hmac_datapath_stress.2805265209
Short name T445
Test name
Test status
Simulation time 4697663723 ps
CPU time 216.53 seconds
Started Jun 28 05:03:12 PM PDT 24
Finished Jun 28 05:06:49 PM PDT 24
Peak memory 479636 kb
Host smart-b2d1dce5-bca7-4354-991a-6a58ed1b41fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805265209 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_datapath_stress.2805265209
Directory /workspace/29.hmac_datapath_stress/latest

Test location /workspace/coverage/default/29.hmac_error.1713055344
Short name T199
Test name
Test status
Simulation time 4377330665 ps
CPU time 79.91 seconds
Started Jun 28 05:03:12 PM PDT 24
Finished Jun 28 05:04:32 PM PDT 24
Peak memory 200580 kb
Host smart-192a627c-97b6-4e36-b30b-bd411dc871cb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713055344 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_error.1713055344
Directory /workspace/29.hmac_error/latest

Test location /workspace/coverage/default/29.hmac_long_msg.2567810691
Short name T662
Test name
Test status
Simulation time 443939596 ps
CPU time 6.93 seconds
Started Jun 28 05:03:12 PM PDT 24
Finished Jun 28 05:03:20 PM PDT 24
Peak memory 200140 kb
Host smart-c5353a43-d411-4543-bd54-0875b8423314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567810691 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_long_msg.2567810691
Directory /workspace/29.hmac_long_msg/latest

Test location /workspace/coverage/default/29.hmac_smoke.422723954
Short name T305
Test name
Test status
Simulation time 1879149472 ps
CPU time 11.87 seconds
Started Jun 28 05:03:12 PM PDT 24
Finished Jun 28 05:03:25 PM PDT 24
Peak memory 200276 kb
Host smart-375b73e9-f64b-4bc0-8152-bfdf17f40a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422723954 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_smoke.422723954
Directory /workspace/29.hmac_smoke/latest

Test location /workspace/coverage/default/29.hmac_stress_all.97725239
Short name T393
Test name
Test status
Simulation time 318148915 ps
CPU time 0.67 seconds
Started Jun 28 05:03:10 PM PDT 24
Finished Jun 28 05:03:11 PM PDT 24
Peak memory 195988 kb
Host smart-fd496ab2-cc09-4baa-be7b-734b2ae6eabd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97725239 -assert nopostp
roc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 29.hmac_stress_all.97725239
Directory /workspace/29.hmac_stress_all/latest

Test location /workspace/coverage/default/29.hmac_test_hmac256_vectors.2507048682
Short name T760
Test name
Test status
Simulation time 2004519935 ps
CPU time 35.83 seconds
Started Jun 28 05:03:12 PM PDT 24
Finished Jun 28 05:03:49 PM PDT 24
Peak memory 200308 kb
Host smart-3f802ac2-e170-478b-8802-8360ad43685f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2507048682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac256_vectors.2507048682
Directory /workspace/29.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_hmac384_vectors.1186637442
Short name T475
Test name
Test status
Simulation time 7969373042 ps
CPU time 84.24 seconds
Started Jun 28 05:03:15 PM PDT 24
Finished Jun 28 05:04:40 PM PDT 24
Peak memory 200364 kb
Host smart-4ead4e10-780e-47cb-860c-a7e63a7f5935
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1186637442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac384_vectors.1186637442
Directory /workspace/29.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_hmac512_vectors.2702888983
Short name T414
Test name
Test status
Simulation time 3879189024 ps
CPU time 57.7 seconds
Started Jun 28 05:03:10 PM PDT 24
Finished Jun 28 05:04:08 PM PDT 24
Peak memory 200292 kb
Host smart-019954b3-489e-4c2b-a6aa-8d56e4386f85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2702888983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_hmac512_vectors.2702888983
Directory /workspace/29.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha256_vectors.1762474155
Short name T747
Test name
Test status
Simulation time 39464428523 ps
CPU time 553.55 seconds
Started Jun 28 05:03:14 PM PDT 24
Finished Jun 28 05:12:28 PM PDT 24
Peak memory 200220 kb
Host smart-e95c3754-46ba-425c-8f58-924ff3fc9918
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1762474155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha256_vectors.1762474155
Directory /workspace/29.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha384_vectors.3271507464
Short name T697
Test name
Test status
Simulation time 310464467400 ps
CPU time 2070.05 seconds
Started Jun 28 05:03:13 PM PDT 24
Finished Jun 28 05:37:44 PM PDT 24
Peak memory 215672 kb
Host smart-2e3446e7-c687-47ca-acf9-ac00da02fbef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3271507464 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha384_vectors.3271507464
Directory /workspace/29.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/29.hmac_test_sha512_vectors.792140790
Short name T343
Test name
Test status
Simulation time 110967815322 ps
CPU time 2062.35 seconds
Started Jun 28 05:03:12 PM PDT 24
Finished Jun 28 05:37:35 PM PDT 24
Peak memory 215740 kb
Host smart-96ed988c-6a23-4104-b801-9ba3b2892727
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=792140790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_test_sha512_vectors.792140790
Directory /workspace/29.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/29.hmac_wipe_secret.1442927493
Short name T545
Test name
Test status
Simulation time 52134092 ps
CPU time 3.04 seconds
Started Jun 28 05:03:12 PM PDT 24
Finished Jun 28 05:03:16 PM PDT 24
Peak memory 200208 kb
Host smart-c1723e98-dec5-4530-9c4f-d9d55620ec00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442927493 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.hmac_wipe_secret.1442927493
Directory /workspace/29.hmac_wipe_secret/latest

Test location /workspace/coverage/default/3.hmac_alert_test.2267326228
Short name T338
Test name
Test status
Simulation time 15717211 ps
CPU time 0.6 seconds
Started Jun 28 05:00:04 PM PDT 24
Finished Jun 28 05:00:05 PM PDT 24
Peak memory 196316 kb
Host smart-532b221b-0261-4d42-bd65-2cc5c206bc06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267326228 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_alert_test.2267326228
Directory /workspace/3.hmac_alert_test/latest

Test location /workspace/coverage/default/3.hmac_back_pressure.21197579
Short name T26
Test name
Test status
Simulation time 790127007 ps
CPU time 32.95 seconds
Started Jun 28 05:00:03 PM PDT 24
Finished Jun 28 05:00:37 PM PDT 24
Peak memory 200444 kb
Host smart-76f14160-b4a1-42bd-9dbd-30b8d3fdc9aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=21197579 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_back_pressure.21197579
Directory /workspace/3.hmac_back_pressure/latest

Test location /workspace/coverage/default/3.hmac_burst_wr.230389050
Short name T355
Test name
Test status
Simulation time 9105416088 ps
CPU time 33.02 seconds
Started Jun 28 05:00:05 PM PDT 24
Finished Jun 28 05:00:39 PM PDT 24
Peak memory 200300 kb
Host smart-7fb8a347-0eb7-4cf4-8ee2-b71b71418eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230389050 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_burst_wr.230389050
Directory /workspace/3.hmac_burst_wr/latest

Test location /workspace/coverage/default/3.hmac_datapath_stress.2055471604
Short name T688
Test name
Test status
Simulation time 17176836904 ps
CPU time 1239.32 seconds
Started Jun 28 05:00:04 PM PDT 24
Finished Jun 28 05:20:45 PM PDT 24
Peak memory 756056 kb
Host smart-c6fd8882-fcea-4d70-8bff-a22fdbaf56ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2055471604 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_datapath_stress.2055471604
Directory /workspace/3.hmac_datapath_stress/latest

Test location /workspace/coverage/default/3.hmac_error.435988185
Short name T467
Test name
Test status
Simulation time 5350720464 ps
CPU time 68.63 seconds
Started Jun 28 05:00:09 PM PDT 24
Finished Jun 28 05:01:18 PM PDT 24
Peak memory 200280 kb
Host smart-186071f5-792b-4f15-8514-54fb5f2e9b8b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435988185 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_error.435988185
Directory /workspace/3.hmac_error/latest

Test location /workspace/coverage/default/3.hmac_long_msg.3572767135
Short name T497
Test name
Test status
Simulation time 55032767083 ps
CPU time 122.89 seconds
Started Jun 28 05:00:03 PM PDT 24
Finished Jun 28 05:02:07 PM PDT 24
Peak memory 200656 kb
Host smart-1fbce0ab-3c53-4b45-a9ae-52675f0ac05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572767135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_long_msg.3572767135
Directory /workspace/3.hmac_long_msg/latest

Test location /workspace/coverage/default/3.hmac_smoke.471752769
Short name T31
Test name
Test status
Simulation time 3195855321 ps
CPU time 15.73 seconds
Started Jun 28 05:00:05 PM PDT 24
Finished Jun 28 05:00:21 PM PDT 24
Peak memory 200264 kb
Host smart-7dff8523-22d3-4d3d-8240-fe121d1c896a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471752769 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_smoke.471752769
Directory /workspace/3.hmac_smoke/latest

Test location /workspace/coverage/default/3.hmac_stress_all.356850778
Short name T501
Test name
Test status
Simulation time 880024909504 ps
CPU time 8232.76 seconds
Started Jun 28 05:00:09 PM PDT 24
Finished Jun 28 07:17:24 PM PDT 24
Peak memory 769100 kb
Host smart-e450eafd-414a-4d85-a430-d60159b07910
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356850778 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.hmac_stress_all.356850778
Directory /workspace/3.hmac_stress_all/latest

Test location /workspace/coverage/default/3.hmac_test_hmac256_vectors.2450813682
Short name T20
Test name
Test status
Simulation time 1388177518 ps
CPU time 57.68 seconds
Started Jun 28 05:00:03 PM PDT 24
Finished Jun 28 05:01:01 PM PDT 24
Peak memory 200192 kb
Host smart-eec95082-d83d-40a8-b43b-9f72787604d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2450813682 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac256_vectors.2450813682
Directory /workspace/3.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac384_vectors.1600959204
Short name T481
Test name
Test status
Simulation time 5099159910 ps
CPU time 55.13 seconds
Started Jun 28 05:00:04 PM PDT 24
Finished Jun 28 05:01:00 PM PDT 24
Peak memory 200296 kb
Host smart-b8a4cc24-7979-4dea-8627-26688eec4d8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1600959204 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac384_vectors.1600959204
Directory /workspace/3.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_hmac512_vectors.2005052725
Short name T556
Test name
Test status
Simulation time 7360032100 ps
CPU time 52.98 seconds
Started Jun 28 05:00:09 PM PDT 24
Finished Jun 28 05:01:02 PM PDT 24
Peak memory 200360 kb
Host smart-012a9bd4-c55e-48b0-8f63-8092cf80ea09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2005052725 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_hmac512_vectors.2005052725
Directory /workspace/3.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha256_vectors.984659599
Short name T331
Test name
Test status
Simulation time 50542890934 ps
CPU time 467.52 seconds
Started Jun 28 05:00:04 PM PDT 24
Finished Jun 28 05:07:53 PM PDT 24
Peak memory 200256 kb
Host smart-40cdfca1-4729-4135-af04-3e0d599342d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=984659599 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha256_vectors.984659599
Directory /workspace/3.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha384_vectors.2901415548
Short name T418
Test name
Test status
Simulation time 444436034665 ps
CPU time 2009.57 seconds
Started Jun 28 05:00:09 PM PDT 24
Finished Jun 28 05:33:40 PM PDT 24
Peak memory 215028 kb
Host smart-3bdf0f51-05ec-405d-8fa2-8740c7a5eea1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2901415548 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha384_vectors.2901415548
Directory /workspace/3.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/3.hmac_test_sha512_vectors.1881267262
Short name T370
Test name
Test status
Simulation time 736406385095 ps
CPU time 2269.77 seconds
Started Jun 28 05:00:02 PM PDT 24
Finished Jun 28 05:37:53 PM PDT 24
Peak memory 215020 kb
Host smart-bff68072-934f-4a28-93ae-0e18a1027448
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1881267262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.hmac_test_sha512_vectors.1881267262
Directory /workspace/3.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_alert_test.584756909
Short name T366
Test name
Test status
Simulation time 27743442 ps
CPU time 0.61 seconds
Started Jun 28 05:03:23 PM PDT 24
Finished Jun 28 05:03:24 PM PDT 24
Peak memory 196244 kb
Host smart-3559425a-0eb6-4b2b-aade-a7c26d19f039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584756909 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_alert_test.584756909
Directory /workspace/30.hmac_alert_test/latest

Test location /workspace/coverage/default/30.hmac_back_pressure.434691388
Short name T285
Test name
Test status
Simulation time 1000005324 ps
CPU time 44.7 seconds
Started Jun 28 05:03:11 PM PDT 24
Finished Jun 28 05:03:57 PM PDT 24
Peak memory 200196 kb
Host smart-3e6fb426-8ea6-4453-8223-963e5820466e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=434691388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_back_pressure.434691388
Directory /workspace/30.hmac_back_pressure/latest

Test location /workspace/coverage/default/30.hmac_burst_wr.3340482239
Short name T707
Test name
Test status
Simulation time 3054665743 ps
CPU time 38.77 seconds
Started Jun 28 05:03:11 PM PDT 24
Finished Jun 28 05:03:50 PM PDT 24
Peak memory 200272 kb
Host smart-716e00bb-620d-4497-b19b-6dc1e204f3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340482239 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_burst_wr.3340482239
Directory /workspace/30.hmac_burst_wr/latest

Test location /workspace/coverage/default/30.hmac_datapath_stress.73880600
Short name T273
Test name
Test status
Simulation time 7392464649 ps
CPU time 1038.85 seconds
Started Jun 28 05:03:11 PM PDT 24
Finished Jun 28 05:20:30 PM PDT 24
Peak memory 760260 kb
Host smart-afb5ea7d-a19e-487f-8169-869bf5966969
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=73880600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_datapath_stress.73880600
Directory /workspace/30.hmac_datapath_stress/latest

Test location /workspace/coverage/default/30.hmac_error.1973158155
Short name T771
Test name
Test status
Simulation time 18985825359 ps
CPU time 80.15 seconds
Started Jun 28 05:03:13 PM PDT 24
Finished Jun 28 05:04:34 PM PDT 24
Peak memory 200256 kb
Host smart-fd085db1-1566-4222-8d60-0b4c4fd6238e
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973158155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_error.1973158155
Directory /workspace/30.hmac_error/latest

Test location /workspace/coverage/default/30.hmac_long_msg.1104807616
Short name T665
Test name
Test status
Simulation time 29460823261 ps
CPU time 103.78 seconds
Started Jun 28 05:03:11 PM PDT 24
Finished Jun 28 05:04:56 PM PDT 24
Peak memory 208576 kb
Host smart-a6883694-5d41-4983-bf2c-869f76af0ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104807616 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_long_msg.1104807616
Directory /workspace/30.hmac_long_msg/latest

Test location /workspace/coverage/default/30.hmac_smoke.3681633144
Short name T550
Test name
Test status
Simulation time 2111395183 ps
CPU time 15.22 seconds
Started Jun 28 05:03:14 PM PDT 24
Finished Jun 28 05:03:29 PM PDT 24
Peak memory 200336 kb
Host smart-2abbd236-9d13-4547-a105-ba8b57572045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681633144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_smoke.3681633144
Directory /workspace/30.hmac_smoke/latest

Test location /workspace/coverage/default/30.hmac_stress_all.2311414836
Short name T86
Test name
Test status
Simulation time 175871335963 ps
CPU time 574.67 seconds
Started Jun 28 05:03:23 PM PDT 24
Finished Jun 28 05:12:59 PM PDT 24
Peak memory 208548 kb
Host smart-3a416c77-8ccd-4e97-ba6d-1553bdf34e54
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311414836 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.hmac_stress_all.2311414836
Directory /workspace/30.hmac_stress_all/latest

Test location /workspace/coverage/default/30.hmac_test_hmac256_vectors.999369000
Short name T182
Test name
Test status
Simulation time 3073043738 ps
CPU time 63.15 seconds
Started Jun 28 05:03:23 PM PDT 24
Finished Jun 28 05:04:27 PM PDT 24
Peak memory 200260 kb
Host smart-2d8f960e-1a66-4102-960c-72985786a7a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=999369000 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac256_vectors.999369000
Directory /workspace/30.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_hmac384_vectors.289579649
Short name T66
Test name
Test status
Simulation time 1521508666 ps
CPU time 46.85 seconds
Started Jun 28 05:03:22 PM PDT 24
Finished Jun 28 05:04:09 PM PDT 24
Peak memory 200236 kb
Host smart-043d85dc-c25c-4ac5-86ef-37e1e778252a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=289579649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac384_vectors.289579649
Directory /workspace/30.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_hmac512_vectors.2018230806
Short name T35
Test name
Test status
Simulation time 15118174403 ps
CPU time 63.19 seconds
Started Jun 28 05:03:23 PM PDT 24
Finished Jun 28 05:04:27 PM PDT 24
Peak memory 200364 kb
Host smart-b0a903af-7829-4338-b56a-dad0a8754111
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2018230806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_hmac512_vectors.2018230806
Directory /workspace/30.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha256_vectors.4150726431
Short name T327
Test name
Test status
Simulation time 51567000569 ps
CPU time 494.25 seconds
Started Jun 28 05:03:11 PM PDT 24
Finished Jun 28 05:11:26 PM PDT 24
Peak memory 200260 kb
Host smart-873db3d5-b76d-4612-adf9-e6eaccff0df4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4150726431 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha256_vectors.4150726431
Directory /workspace/30.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha384_vectors.4218366654
Short name T696
Test name
Test status
Simulation time 105659780431 ps
CPU time 1951.16 seconds
Started Jun 28 05:03:13 PM PDT 24
Finished Jun 28 05:35:45 PM PDT 24
Peak memory 215752 kb
Host smart-7fb6e0f8-8087-4a56-bfaa-ee0a713432ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4218366654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha384_vectors.4218366654
Directory /workspace/30.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/30.hmac_test_sha512_vectors.1938001212
Short name T421
Test name
Test status
Simulation time 150670194256 ps
CPU time 1991.51 seconds
Started Jun 28 05:03:12 PM PDT 24
Finished Jun 28 05:36:25 PM PDT 24
Peak memory 216256 kb
Host smart-69f231c1-f224-46e3-86d8-d10df043a4b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1938001212 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_test_sha512_vectors.1938001212
Directory /workspace/30.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/30.hmac_wipe_secret.2176708998
Short name T612
Test name
Test status
Simulation time 4072151119 ps
CPU time 55.07 seconds
Started Jun 28 05:03:15 PM PDT 24
Finished Jun 28 05:04:11 PM PDT 24
Peak memory 200356 kb
Host smart-6b3702a2-c037-4ebf-92f9-7df03a84fcd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176708998 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.hmac_wipe_secret.2176708998
Directory /workspace/30.hmac_wipe_secret/latest

Test location /workspace/coverage/default/31.hmac_alert_test.134129207
Short name T365
Test name
Test status
Simulation time 45451669 ps
CPU time 0.6 seconds
Started Jun 28 05:03:22 PM PDT 24
Finished Jun 28 05:03:24 PM PDT 24
Peak memory 196992 kb
Host smart-b849d1d9-a08d-4ca0-828d-87d05e9d2574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134129207 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_alert_test.134129207
Directory /workspace/31.hmac_alert_test/latest

Test location /workspace/coverage/default/31.hmac_back_pressure.3394328687
Short name T10
Test name
Test status
Simulation time 539954756 ps
CPU time 13.12 seconds
Started Jun 28 05:03:22 PM PDT 24
Finished Jun 28 05:03:37 PM PDT 24
Peak memory 200308 kb
Host smart-33fac2ea-8fc6-4d18-9781-25552dab8f5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3394328687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_back_pressure.3394328687
Directory /workspace/31.hmac_back_pressure/latest

Test location /workspace/coverage/default/31.hmac_burst_wr.1741948652
Short name T159
Test name
Test status
Simulation time 1161456955 ps
CPU time 32.4 seconds
Started Jun 28 05:03:23 PM PDT 24
Finished Jun 28 05:03:56 PM PDT 24
Peak memory 200260 kb
Host smart-9cbde0bf-4be3-4502-9fe6-61229a280a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741948652 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_burst_wr.1741948652
Directory /workspace/31.hmac_burst_wr/latest

Test location /workspace/coverage/default/31.hmac_datapath_stress.3330100063
Short name T455
Test name
Test status
Simulation time 30806505902 ps
CPU time 824.7 seconds
Started Jun 28 05:03:22 PM PDT 24
Finished Jun 28 05:17:08 PM PDT 24
Peak memory 716152 kb
Host smart-31967b45-9597-4560-8136-659ec433d2d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3330100063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_datapath_stress.3330100063
Directory /workspace/31.hmac_datapath_stress/latest

Test location /workspace/coverage/default/31.hmac_error.3487014802
Short name T196
Test name
Test status
Simulation time 22751764237 ps
CPU time 148.23 seconds
Started Jun 28 05:03:25 PM PDT 24
Finished Jun 28 05:05:53 PM PDT 24
Peak memory 200296 kb
Host smart-80b8b554-1684-4fc8-95d1-3e5f12816432
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487014802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_error.3487014802
Directory /workspace/31.hmac_error/latest

Test location /workspace/coverage/default/31.hmac_long_msg.2125368681
Short name T55
Test name
Test status
Simulation time 1175441421 ps
CPU time 73.36 seconds
Started Jun 28 05:03:21 PM PDT 24
Finished Jun 28 05:04:35 PM PDT 24
Peak memory 200324 kb
Host smart-999a77a2-6148-4b7f-85d8-008cf4bdd7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125368681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_long_msg.2125368681
Directory /workspace/31.hmac_long_msg/latest

Test location /workspace/coverage/default/31.hmac_smoke.4255034331
Short name T163
Test name
Test status
Simulation time 64041998 ps
CPU time 1.68 seconds
Started Jun 28 05:03:27 PM PDT 24
Finished Jun 28 05:03:29 PM PDT 24
Peak memory 200280 kb
Host smart-d6bd987a-3066-47b0-95bf-32b7ab02c6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255034331 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_smoke.4255034331
Directory /workspace/31.hmac_smoke/latest

Test location /workspace/coverage/default/31.hmac_stress_all.3647359842
Short name T143
Test name
Test status
Simulation time 245388281576 ps
CPU time 5544.15 seconds
Started Jun 28 05:03:23 PM PDT 24
Finished Jun 28 06:35:49 PM PDT 24
Peak memory 822280 kb
Host smart-05dc8961-4cff-4945-a8a4-6124568a8cec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647359842 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.hmac_stress_all.3647359842
Directory /workspace/31.hmac_stress_all/latest

Test location /workspace/coverage/default/31.hmac_test_hmac256_vectors.933318169
Short name T430
Test name
Test status
Simulation time 26135536313 ps
CPU time 63.43 seconds
Started Jun 28 05:03:22 PM PDT 24
Finished Jun 28 05:04:26 PM PDT 24
Peak memory 200364 kb
Host smart-b063e5e6-657e-44e3-a2ce-89f709b2f959
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=933318169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac256_vectors.933318169
Directory /workspace/31.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_hmac384_vectors.1732250701
Short name T466
Test name
Test status
Simulation time 14401159787 ps
CPU time 52.27 seconds
Started Jun 28 05:03:23 PM PDT 24
Finished Jun 28 05:04:16 PM PDT 24
Peak memory 200324 kb
Host smart-79ae7581-8fd0-4273-a678-54617e28adac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1732250701 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac384_vectors.1732250701
Directory /workspace/31.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_hmac512_vectors.2741784774
Short name T330
Test name
Test status
Simulation time 10204762774 ps
CPU time 94.93 seconds
Started Jun 28 05:03:24 PM PDT 24
Finished Jun 28 05:04:59 PM PDT 24
Peak memory 200324 kb
Host smart-ed598e69-7a24-44dc-afcf-bac1ad920dfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2741784774 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_hmac512_vectors.2741784774
Directory /workspace/31.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha256_vectors.215360950
Short name T508
Test name
Test status
Simulation time 37052158217 ps
CPU time 433.38 seconds
Started Jun 28 05:03:24 PM PDT 24
Finished Jun 28 05:10:38 PM PDT 24
Peak memory 200292 kb
Host smart-2e4e2027-4447-4ab9-afb9-58877f6f1b6b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=215360950 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha256_vectors.215360950
Directory /workspace/31.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha384_vectors.2426795469
Short name T732
Test name
Test status
Simulation time 107411302656 ps
CPU time 2064.86 seconds
Started Jun 28 05:03:23 PM PDT 24
Finished Jun 28 05:37:49 PM PDT 24
Peak memory 216680 kb
Host smart-217e8095-eba8-476c-b8e6-8f26f7f9306e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2426795469 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha384_vectors.2426795469
Directory /workspace/31.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/31.hmac_test_sha512_vectors.3851347654
Short name T374
Test name
Test status
Simulation time 33961401178 ps
CPU time 1997.17 seconds
Started Jun 28 05:03:23 PM PDT 24
Finished Jun 28 05:36:41 PM PDT 24
Peak memory 216296 kb
Host smart-7b9d14a7-9d7e-4135-ac31-aaf8d8273695
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3851347654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_test_sha512_vectors.3851347654
Directory /workspace/31.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/31.hmac_wipe_secret.4247933724
Short name T262
Test name
Test status
Simulation time 8723557864 ps
CPU time 46.32 seconds
Started Jun 28 05:03:22 PM PDT 24
Finished Jun 28 05:04:09 PM PDT 24
Peak memory 200368 kb
Host smart-0750214d-4057-46cc-aad8-3a2ea69701cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247933724 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.hmac_wipe_secret.4247933724
Directory /workspace/31.hmac_wipe_secret/latest

Test location /workspace/coverage/default/32.hmac_alert_test.2781426793
Short name T376
Test name
Test status
Simulation time 14304213 ps
CPU time 0.62 seconds
Started Jun 28 05:03:33 PM PDT 24
Finished Jun 28 05:03:34 PM PDT 24
Peak memory 195196 kb
Host smart-6f267d67-30cc-454f-baeb-eeea7de814b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781426793 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_alert_test.2781426793
Directory /workspace/32.hmac_alert_test/latest

Test location /workspace/coverage/default/32.hmac_back_pressure.3079139145
Short name T782
Test name
Test status
Simulation time 3392578174 ps
CPU time 42.12 seconds
Started Jun 28 05:03:22 PM PDT 24
Finished Jun 28 05:04:06 PM PDT 24
Peak memory 200364 kb
Host smart-c6054628-6854-47e8-8d5d-7bfb07c04f31
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3079139145 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_back_pressure.3079139145
Directory /workspace/32.hmac_back_pressure/latest

Test location /workspace/coverage/default/32.hmac_burst_wr.1278262292
Short name T192
Test name
Test status
Simulation time 4595225608 ps
CPU time 43.61 seconds
Started Jun 28 05:03:35 PM PDT 24
Finished Jun 28 05:04:19 PM PDT 24
Peak memory 200340 kb
Host smart-e2c5cefb-6915-4fcf-87f8-4ecb0119b0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278262292 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_burst_wr.1278262292
Directory /workspace/32.hmac_burst_wr/latest

Test location /workspace/coverage/default/32.hmac_datapath_stress.653745192
Short name T739
Test name
Test status
Simulation time 2652653708 ps
CPU time 692.97 seconds
Started Jun 28 05:03:22 PM PDT 24
Finished Jun 28 05:14:56 PM PDT 24
Peak memory 717108 kb
Host smart-caf44325-f4f1-4b67-b509-3a4f972bf231
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=653745192 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_datapath_stress.653745192
Directory /workspace/32.hmac_datapath_stress/latest

Test location /workspace/coverage/default/32.hmac_error.3842970653
Short name T231
Test name
Test status
Simulation time 14095827648 ps
CPU time 181.84 seconds
Started Jun 28 05:03:33 PM PDT 24
Finished Jun 28 05:06:36 PM PDT 24
Peak memory 200324 kb
Host smart-745014d7-6512-4724-b7f5-fbecedc5ba0a
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842970653 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_error.3842970653
Directory /workspace/32.hmac_error/latest

Test location /workspace/coverage/default/32.hmac_long_msg.3409817958
Short name T640
Test name
Test status
Simulation time 18369420891 ps
CPU time 85.66 seconds
Started Jun 28 05:03:22 PM PDT 24
Finished Jun 28 05:04:49 PM PDT 24
Peak memory 200664 kb
Host smart-fd07b5f8-5006-4caa-81ce-81d72b39cb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409817958 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_long_msg.3409817958
Directory /workspace/32.hmac_long_msg/latest

Test location /workspace/coverage/default/32.hmac_smoke.1018117349
Short name T675
Test name
Test status
Simulation time 2505286948 ps
CPU time 14.36 seconds
Started Jun 28 05:03:23 PM PDT 24
Finished Jun 28 05:03:38 PM PDT 24
Peak memory 200304 kb
Host smart-4f935fb5-cd67-4c8d-bf24-5fbfcb26e16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018117349 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_smoke.1018117349
Directory /workspace/32.hmac_smoke/latest

Test location /workspace/coverage/default/32.hmac_test_hmac256_vectors.2009029797
Short name T541
Test name
Test status
Simulation time 16392716697 ps
CPU time 34.06 seconds
Started Jun 28 05:03:36 PM PDT 24
Finished Jun 28 05:04:10 PM PDT 24
Peak memory 200256 kb
Host smart-6fca18c5-5e3e-4bd2-950a-14b81a1ab04b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2009029797 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac256_vectors.2009029797
Directory /workspace/32.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_hmac384_vectors.2402885572
Short name T621
Test name
Test status
Simulation time 5914176089 ps
CPU time 95.61 seconds
Started Jun 28 05:03:35 PM PDT 24
Finished Jun 28 05:05:11 PM PDT 24
Peak memory 200328 kb
Host smart-c66e21d2-094e-4aa5-ac0b-8e3f72822626
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2402885572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac384_vectors.2402885572
Directory /workspace/32.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_hmac512_vectors.3010333437
Short name T345
Test name
Test status
Simulation time 157727556557 ps
CPU time 117.62 seconds
Started Jun 28 05:03:35 PM PDT 24
Finished Jun 28 05:05:33 PM PDT 24
Peak memory 200328 kb
Host smart-143531de-6a9f-492a-8dee-b52d74e8c473
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3010333437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_hmac512_vectors.3010333437
Directory /workspace/32.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha256_vectors.1957056250
Short name T676
Test name
Test status
Simulation time 7623430353 ps
CPU time 426.33 seconds
Started Jun 28 05:03:33 PM PDT 24
Finished Jun 28 05:10:40 PM PDT 24
Peak memory 200340 kb
Host smart-f8b86598-001b-47bc-bcab-573ed73af3e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1957056250 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha256_vectors.1957056250
Directory /workspace/32.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha384_vectors.3800028216
Short name T209
Test name
Test status
Simulation time 66234636629 ps
CPU time 1764.54 seconds
Started Jun 28 05:03:34 PM PDT 24
Finished Jun 28 05:33:00 PM PDT 24
Peak memory 215732 kb
Host smart-932f7b8d-f2d6-4022-a1b1-76f72bc10ad1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3800028216 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha384_vectors.3800028216
Directory /workspace/32.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/32.hmac_test_sha512_vectors.2939853389
Short name T420
Test name
Test status
Simulation time 33592900968 ps
CPU time 1872.28 seconds
Started Jun 28 05:03:34 PM PDT 24
Finished Jun 28 05:34:47 PM PDT 24
Peak memory 216416 kb
Host smart-79ad3769-15f5-4b79-a86a-1f9ceef69e11
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2939853389 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_test_sha512_vectors.2939853389
Directory /workspace/32.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/32.hmac_wipe_secret.2021639840
Short name T298
Test name
Test status
Simulation time 4686195222 ps
CPU time 66.15 seconds
Started Jun 28 05:03:34 PM PDT 24
Finished Jun 28 05:04:41 PM PDT 24
Peak memory 200508 kb
Host smart-f7f334c7-74ea-40cb-8ff5-272a7090e671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021639840 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.hmac_wipe_secret.2021639840
Directory /workspace/32.hmac_wipe_secret/latest

Test location /workspace/coverage/default/33.hmac_alert_test.1330285833
Short name T102
Test name
Test status
Simulation time 13005522 ps
CPU time 0.57 seconds
Started Jun 28 05:03:38 PM PDT 24
Finished Jun 28 05:03:39 PM PDT 24
Peak memory 195940 kb
Host smart-fe6628ba-8f43-4314-b2af-4e6642af20ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330285833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_alert_test.1330285833
Directory /workspace/33.hmac_alert_test/latest

Test location /workspace/coverage/default/33.hmac_back_pressure.3267794080
Short name T30
Test name
Test status
Simulation time 1251610623 ps
CPU time 26.58 seconds
Started Jun 28 05:03:37 PM PDT 24
Finished Jun 28 05:04:04 PM PDT 24
Peak memory 200248 kb
Host smart-69c7d181-e60b-463e-aeab-92a7bd1f519e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3267794080 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_back_pressure.3267794080
Directory /workspace/33.hmac_back_pressure/latest

Test location /workspace/coverage/default/33.hmac_burst_wr.1725242861
Short name T169
Test name
Test status
Simulation time 1799121074 ps
CPU time 9.8 seconds
Started Jun 28 05:03:38 PM PDT 24
Finished Jun 28 05:03:48 PM PDT 24
Peak memory 200128 kb
Host smart-933b8413-4e4c-40d8-996e-655d055f64f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725242861 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_burst_wr.1725242861
Directory /workspace/33.hmac_burst_wr/latest

Test location /workspace/coverage/default/33.hmac_datapath_stress.1097309750
Short name T462
Test name
Test status
Simulation time 5021362915 ps
CPU time 309.09 seconds
Started Jun 28 05:03:38 PM PDT 24
Finished Jun 28 05:08:48 PM PDT 24
Peak memory 682468 kb
Host smart-dbe6a18c-5354-4e8f-a091-a3bd371037b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1097309750 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_datapath_stress.1097309750
Directory /workspace/33.hmac_datapath_stress/latest

Test location /workspace/coverage/default/33.hmac_error.1157455970
Short name T318
Test name
Test status
Simulation time 26720421508 ps
CPU time 177.94 seconds
Started Jun 28 05:03:38 PM PDT 24
Finished Jun 28 05:06:36 PM PDT 24
Peak memory 200296 kb
Host smart-beaae109-80a4-4fbc-a24b-dcf5d8bdb00d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157455970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_error.1157455970
Directory /workspace/33.hmac_error/latest

Test location /workspace/coverage/default/33.hmac_long_msg.3963415911
Short name T776
Test name
Test status
Simulation time 8999982815 ps
CPU time 63.96 seconds
Started Jun 28 05:03:35 PM PDT 24
Finished Jun 28 05:04:40 PM PDT 24
Peak memory 200304 kb
Host smart-8d4ef664-95e8-464b-8158-0b9b05420288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963415911 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_long_msg.3963415911
Directory /workspace/33.hmac_long_msg/latest

Test location /workspace/coverage/default/33.hmac_smoke.2535108017
Short name T564
Test name
Test status
Simulation time 3525681703 ps
CPU time 18.64 seconds
Started Jun 28 05:03:34 PM PDT 24
Finished Jun 28 05:03:53 PM PDT 24
Peak memory 200304 kb
Host smart-5a4f8254-df4f-441f-825d-abc073bcfd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535108017 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_smoke.2535108017
Directory /workspace/33.hmac_smoke/latest

Test location /workspace/coverage/default/33.hmac_stress_all.3357144413
Short name T568
Test name
Test status
Simulation time 773543234174 ps
CPU time 4771.09 seconds
Started Jun 28 05:03:37 PM PDT 24
Finished Jun 28 06:23:09 PM PDT 24
Peak memory 805784 kb
Host smart-9c672807-d13f-43ca-98ef-94ce2ec0988d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357144413 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.hmac_stress_all.3357144413
Directory /workspace/33.hmac_stress_all/latest

Test location /workspace/coverage/default/33.hmac_test_hmac256_vectors.3970182284
Short name T484
Test name
Test status
Simulation time 4612431921 ps
CPU time 38.8 seconds
Started Jun 28 05:03:34 PM PDT 24
Finished Jun 28 05:04:14 PM PDT 24
Peak memory 200328 kb
Host smart-e084e777-609b-4500-a942-841c860269ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3970182284 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac256_vectors.3970182284
Directory /workspace/33.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_hmac384_vectors.4051764907
Short name T168
Test name
Test status
Simulation time 5302966166 ps
CPU time 82.44 seconds
Started Jun 28 05:03:35 PM PDT 24
Finished Jun 28 05:04:58 PM PDT 24
Peak memory 200328 kb
Host smart-db74b126-e9cd-45b8-b306-d1a9989dda19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4051764907 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac384_vectors.4051764907
Directory /workspace/33.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_hmac512_vectors.822370689
Short name T500
Test name
Test status
Simulation time 24986751022 ps
CPU time 76.61 seconds
Started Jun 28 05:03:35 PM PDT 24
Finished Jun 28 05:04:52 PM PDT 24
Peak memory 200556 kb
Host smart-0bcb11e3-e339-4f23-ae3a-9d984d7950c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=822370689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_hmac512_vectors.822370689
Directory /workspace/33.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha256_vectors.2755523872
Short name T282
Test name
Test status
Simulation time 167482904456 ps
CPU time 509.05 seconds
Started Jun 28 05:03:37 PM PDT 24
Finished Jun 28 05:12:07 PM PDT 24
Peak memory 200188 kb
Host smart-041dfa7e-28d2-4b8d-8ae2-cf51af6d198f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2755523872 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha256_vectors.2755523872
Directory /workspace/33.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha384_vectors.414328193
Short name T323
Test name
Test status
Simulation time 105361821080 ps
CPU time 1945.42 seconds
Started Jun 28 05:03:38 PM PDT 24
Finished Jun 28 05:36:04 PM PDT 24
Peak memory 215820 kb
Host smart-1cb719b7-efee-4ab9-b3f3-c207ae89511f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=414328193 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha384_vectors.414328193
Directory /workspace/33.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/33.hmac_test_sha512_vectors.1451754437
Short name T249
Test name
Test status
Simulation time 30897234348 ps
CPU time 1719.81 seconds
Started Jun 28 05:03:36 PM PDT 24
Finished Jun 28 05:32:16 PM PDT 24
Peak memory 216120 kb
Host smart-6fa47c4b-6872-4a39-9c32-f78ab315f90e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1451754437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_test_sha512_vectors.1451754437
Directory /workspace/33.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/33.hmac_wipe_secret.1302059486
Short name T304
Test name
Test status
Simulation time 636888575 ps
CPU time 6.84 seconds
Started Jun 28 05:03:35 PM PDT 24
Finished Jun 28 05:03:43 PM PDT 24
Peak memory 200060 kb
Host smart-9acf1432-79d2-4cb1-8d04-cb141163b7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302059486 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.hmac_wipe_secret.1302059486
Directory /workspace/33.hmac_wipe_secret/latest

Test location /workspace/coverage/default/34.hmac_alert_test.2214641396
Short name T683
Test name
Test status
Simulation time 12850999 ps
CPU time 0.6 seconds
Started Jun 28 05:03:53 PM PDT 24
Finished Jun 28 05:03:54 PM PDT 24
Peak memory 195852 kb
Host smart-f124bd13-c601-43d3-b566-e3ae43017db2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214641396 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_alert_test.2214641396
Directory /workspace/34.hmac_alert_test/latest

Test location /workspace/coverage/default/34.hmac_back_pressure.1857127515
Short name T663
Test name
Test status
Simulation time 2408995180 ps
CPU time 28.56 seconds
Started Jun 28 05:03:44 PM PDT 24
Finished Jun 28 05:04:13 PM PDT 24
Peak memory 200304 kb
Host smart-30c98408-76a7-4777-b29d-dbc781b3965c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857127515 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_back_pressure.1857127515
Directory /workspace/34.hmac_back_pressure/latest

Test location /workspace/coverage/default/34.hmac_burst_wr.2518355463
Short name T241
Test name
Test status
Simulation time 10145320017 ps
CPU time 44.94 seconds
Started Jun 28 05:03:44 PM PDT 24
Finished Jun 28 05:04:30 PM PDT 24
Peak memory 208792 kb
Host smart-7bf3430d-5684-46f5-bd10-eb03b029ab6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518355463 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_burst_wr.2518355463
Directory /workspace/34.hmac_burst_wr/latest

Test location /workspace/coverage/default/34.hmac_datapath_stress.705211674
Short name T180
Test name
Test status
Simulation time 5633435028 ps
CPU time 931.17 seconds
Started Jun 28 05:03:43 PM PDT 24
Finished Jun 28 05:19:15 PM PDT 24
Peak memory 762612 kb
Host smart-a7482c2a-8e51-4521-b8f8-ee14d8a8c84f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=705211674 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_datapath_stress.705211674
Directory /workspace/34.hmac_datapath_stress/latest

Test location /workspace/coverage/default/34.hmac_error.1396484721
Short name T363
Test name
Test status
Simulation time 7258761997 ps
CPU time 85.77 seconds
Started Jun 28 05:03:44 PM PDT 24
Finished Jun 28 05:05:10 PM PDT 24
Peak memory 200256 kb
Host smart-5af3830d-06e7-4b6b-a2ee-905a3facdb72
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396484721 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_error.1396484721
Directory /workspace/34.hmac_error/latest

Test location /workspace/coverage/default/34.hmac_long_msg.2251413770
Short name T428
Test name
Test status
Simulation time 13078399519 ps
CPU time 123.34 seconds
Started Jun 28 05:03:34 PM PDT 24
Finished Jun 28 05:05:39 PM PDT 24
Peak memory 200244 kb
Host smart-f535f46b-3da3-4ce4-8ee5-2f62583e73c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251413770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_long_msg.2251413770
Directory /workspace/34.hmac_long_msg/latest

Test location /workspace/coverage/default/34.hmac_smoke.22611449
Short name T275
Test name
Test status
Simulation time 436114546 ps
CPU time 6.2 seconds
Started Jun 28 05:03:35 PM PDT 24
Finished Jun 28 05:03:42 PM PDT 24
Peak memory 200352 kb
Host smart-c8c1bcde-82f4-4282-b842-89ae88882d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22611449 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_smoke.22611449
Directory /workspace/34.hmac_smoke/latest

Test location /workspace/coverage/default/34.hmac_stress_all.3249253461
Short name T456
Test name
Test status
Simulation time 65149315157 ps
CPU time 1997.55 seconds
Started Jun 28 05:03:43 PM PDT 24
Finished Jun 28 05:37:01 PM PDT 24
Peak memory 740628 kb
Host smart-35621f7f-e6bc-4d3c-a1c4-14ac279c75f7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249253461 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.hmac_stress_all.3249253461
Directory /workspace/34.hmac_stress_all/latest

Test location /workspace/coverage/default/34.hmac_test_hmac256_vectors.938776383
Short name T725
Test name
Test status
Simulation time 8148113795 ps
CPU time 70.16 seconds
Started Jun 28 05:03:42 PM PDT 24
Finished Jun 28 05:04:53 PM PDT 24
Peak memory 200324 kb
Host smart-29b2867f-f50c-460b-b1e9-028a7d05f65f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=938776383 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac256_vectors.938776383
Directory /workspace/34.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_hmac384_vectors.2030539037
Short name T728
Test name
Test status
Simulation time 32815981285 ps
CPU time 89.5 seconds
Started Jun 28 05:03:43 PM PDT 24
Finished Jun 28 05:05:13 PM PDT 24
Peak memory 200324 kb
Host smart-252502f4-07fe-4f9b-99d2-d9fa77397741
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2030539037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac384_vectors.2030539037
Directory /workspace/34.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_hmac512_vectors.1534137155
Short name T505
Test name
Test status
Simulation time 23296987620 ps
CPU time 57.68 seconds
Started Jun 28 05:03:48 PM PDT 24
Finished Jun 28 05:04:46 PM PDT 24
Peak memory 200300 kb
Host smart-dc11cbdc-5ca2-4bef-ac49-9d2fa0d0524b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1534137155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_hmac512_vectors.1534137155
Directory /workspace/34.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha256_vectors.2838606693
Short name T344
Test name
Test status
Simulation time 54087254375 ps
CPU time 507.79 seconds
Started Jun 28 05:03:48 PM PDT 24
Finished Jun 28 05:12:16 PM PDT 24
Peak memory 200268 kb
Host smart-c99201c7-0e16-41a7-84d5-2e504ca611a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2838606693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha256_vectors.2838606693
Directory /workspace/34.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha384_vectors.3005590867
Short name T266
Test name
Test status
Simulation time 120165659166 ps
CPU time 1604.61 seconds
Started Jun 28 05:03:45 PM PDT 24
Finished Jun 28 05:30:30 PM PDT 24
Peak memory 216200 kb
Host smart-c7c0dfce-02a9-4756-92a8-223e0a7181f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3005590867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha384_vectors.3005590867
Directory /workspace/34.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/34.hmac_test_sha512_vectors.4021285225
Short name T601
Test name
Test status
Simulation time 262701250581 ps
CPU time 1917.78 seconds
Started Jun 28 05:03:44 PM PDT 24
Finished Jun 28 05:35:42 PM PDT 24
Peak memory 215724 kb
Host smart-2315b2dc-b9a8-496c-baaf-44ad7863f56a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4021285225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_test_sha512_vectors.4021285225
Directory /workspace/34.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/34.hmac_wipe_secret.2962169614
Short name T636
Test name
Test status
Simulation time 1185552153 ps
CPU time 63.11 seconds
Started Jun 28 05:03:44 PM PDT 24
Finished Jun 28 05:04:47 PM PDT 24
Peak memory 200280 kb
Host smart-6aa14a5d-4ffc-40eb-9c1f-53c85d4b7b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962169614 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.hmac_wipe_secret.2962169614
Directory /workspace/34.hmac_wipe_secret/latest

Test location /workspace/coverage/default/35.hmac_alert_test.2310973956
Short name T167
Test name
Test status
Simulation time 35397699 ps
CPU time 0.6 seconds
Started Jun 28 05:03:55 PM PDT 24
Finished Jun 28 05:03:56 PM PDT 24
Peak memory 197168 kb
Host smart-5472ae52-4db0-4146-a5e9-dc734487b2ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310973956 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_alert_test.2310973956
Directory /workspace/35.hmac_alert_test/latest

Test location /workspace/coverage/default/35.hmac_back_pressure.1408221753
Short name T396
Test name
Test status
Simulation time 7554398640 ps
CPU time 41.37 seconds
Started Jun 28 05:03:54 PM PDT 24
Finished Jun 28 05:04:36 PM PDT 24
Peak memory 200344 kb
Host smart-af1242f2-7598-49ac-abd3-3404e9af67a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1408221753 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_back_pressure.1408221753
Directory /workspace/35.hmac_back_pressure/latest

Test location /workspace/coverage/default/35.hmac_burst_wr.4236260649
Short name T142
Test name
Test status
Simulation time 63600706173 ps
CPU time 80.08 seconds
Started Jun 28 05:03:59 PM PDT 24
Finished Jun 28 05:05:20 PM PDT 24
Peak memory 200312 kb
Host smart-082c63a9-5eb8-4e7a-8dae-b3f9e2ae6495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236260649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_burst_wr.4236260649
Directory /workspace/35.hmac_burst_wr/latest

Test location /workspace/coverage/default/35.hmac_datapath_stress.3969533442
Short name T635
Test name
Test status
Simulation time 10091240020 ps
CPU time 1620.67 seconds
Started Jun 28 05:03:57 PM PDT 24
Finished Jun 28 05:30:58 PM PDT 24
Peak memory 776512 kb
Host smart-51602a4d-161e-458f-a7e5-0d38b587e13f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969533442 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_datapath_stress.3969533442
Directory /workspace/35.hmac_datapath_stress/latest

Test location /workspace/coverage/default/35.hmac_error.1046338411
Short name T600
Test name
Test status
Simulation time 4106107586 ps
CPU time 40.71 seconds
Started Jun 28 05:03:55 PM PDT 24
Finished Jun 28 05:04:36 PM PDT 24
Peak memory 200252 kb
Host smart-3cd05b13-b644-4a68-b103-5870083225e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046338411 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_error.1046338411
Directory /workspace/35.hmac_error/latest

Test location /workspace/coverage/default/35.hmac_long_msg.1540899593
Short name T641
Test name
Test status
Simulation time 999995762 ps
CPU time 32.38 seconds
Started Jun 28 05:03:54 PM PDT 24
Finished Jun 28 05:04:27 PM PDT 24
Peak memory 200220 kb
Host smart-04e2a9ed-d076-4431-a479-cc779918af06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540899593 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_long_msg.1540899593
Directory /workspace/35.hmac_long_msg/latest

Test location /workspace/coverage/default/35.hmac_smoke.65756688
Short name T491
Test name
Test status
Simulation time 102249869 ps
CPU time 5.56 seconds
Started Jun 28 05:03:59 PM PDT 24
Finished Jun 28 05:04:05 PM PDT 24
Peak memory 200148 kb
Host smart-a0c3e76a-7bcc-4072-a518-6aaa83fa1d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65756688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_smoke.65756688
Directory /workspace/35.hmac_smoke/latest

Test location /workspace/coverage/default/35.hmac_test_hmac256_vectors.2571148824
Short name T625
Test name
Test status
Simulation time 1702153450 ps
CPU time 63.89 seconds
Started Jun 28 05:03:54 PM PDT 24
Finished Jun 28 05:04:58 PM PDT 24
Peak memory 200272 kb
Host smart-53370ef6-7e9a-40a0-b8e5-72f295360b44
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2571148824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac256_vectors.2571148824
Directory /workspace/35.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_hmac384_vectors.3281534151
Short name T292
Test name
Test status
Simulation time 2007110646 ps
CPU time 49 seconds
Started Jun 28 05:03:55 PM PDT 24
Finished Jun 28 05:04:44 PM PDT 24
Peak memory 200308 kb
Host smart-22dafeec-0cc1-41f2-bd09-8930874a8e1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3281534151 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac384_vectors.3281534151
Directory /workspace/35.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_hmac512_vectors.4024406569
Short name T657
Test name
Test status
Simulation time 2927092089 ps
CPU time 112.08 seconds
Started Jun 28 05:03:55 PM PDT 24
Finished Jun 28 05:05:48 PM PDT 24
Peak memory 200324 kb
Host smart-637c384c-45c3-4d04-a0b0-322720e075c9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4024406569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_hmac512_vectors.4024406569
Directory /workspace/35.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha256_vectors.2516139413
Short name T224
Test name
Test status
Simulation time 37672877658 ps
CPU time 528.61 seconds
Started Jun 28 05:03:54 PM PDT 24
Finished Jun 28 05:12:44 PM PDT 24
Peak memory 200252 kb
Host smart-a9fc6d17-5ff4-4cf4-89b1-9f4d7756279d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2516139413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha256_vectors.2516139413
Directory /workspace/35.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha384_vectors.4256042407
Short name T779
Test name
Test status
Simulation time 29963275847 ps
CPU time 1736.63 seconds
Started Jun 28 05:03:54 PM PDT 24
Finished Jun 28 05:32:51 PM PDT 24
Peak memory 216620 kb
Host smart-bb81445a-e3ba-4160-b8a4-871799fb62f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4256042407 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha384_vectors.4256042407
Directory /workspace/35.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/35.hmac_test_sha512_vectors.3770850745
Short name T239
Test name
Test status
Simulation time 546105042911 ps
CPU time 1880.79 seconds
Started Jun 28 05:03:54 PM PDT 24
Finished Jun 28 05:35:16 PM PDT 24
Peak memory 215804 kb
Host smart-76108505-73fe-4a22-aab6-c6d9558d6825
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3770850745 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_test_sha512_vectors.3770850745
Directory /workspace/35.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/35.hmac_wipe_secret.433093796
Short name T322
Test name
Test status
Simulation time 1632040013 ps
CPU time 31.46 seconds
Started Jun 28 05:03:57 PM PDT 24
Finished Jun 28 05:04:29 PM PDT 24
Peak memory 200276 kb
Host smart-6f001510-3d3e-4b45-8d53-bca5106de6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433093796 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.hmac_wipe_secret.433093796
Directory /workspace/35.hmac_wipe_secret/latest

Test location /workspace/coverage/default/36.hmac_alert_test.1955417981
Short name T792
Test name
Test status
Simulation time 18048077 ps
CPU time 0.57 seconds
Started Jun 28 05:04:09 PM PDT 24
Finished Jun 28 05:04:10 PM PDT 24
Peak memory 196240 kb
Host smart-30723b9e-0829-4da2-a789-3e414c436d8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955417981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_alert_test.1955417981
Directory /workspace/36.hmac_alert_test/latest

Test location /workspace/coverage/default/36.hmac_back_pressure.3286300833
Short name T571
Test name
Test status
Simulation time 636358149 ps
CPU time 16.93 seconds
Started Jun 28 05:03:55 PM PDT 24
Finished Jun 28 05:04:13 PM PDT 24
Peak memory 200296 kb
Host smart-c58f2ee9-e075-4d2d-af09-db512c917cbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286300833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_back_pressure.3286300833
Directory /workspace/36.hmac_back_pressure/latest

Test location /workspace/coverage/default/36.hmac_burst_wr.380907351
Short name T408
Test name
Test status
Simulation time 3609904574 ps
CPU time 50.1 seconds
Started Jun 28 05:04:00 PM PDT 24
Finished Jun 28 05:04:50 PM PDT 24
Peak memory 215928 kb
Host smart-49bbbdde-adea-4a9f-95c8-e9edc2221f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380907351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_burst_wr.380907351
Directory /workspace/36.hmac_burst_wr/latest

Test location /workspace/coverage/default/36.hmac_datapath_stress.486025144
Short name T200
Test name
Test status
Simulation time 81772028804 ps
CPU time 1104.32 seconds
Started Jun 28 05:03:58 PM PDT 24
Finished Jun 28 05:22:23 PM PDT 24
Peak memory 788352 kb
Host smart-21eaa1e1-ddd2-4a62-9a52-98a891d35ba1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=486025144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_datapath_stress.486025144
Directory /workspace/36.hmac_datapath_stress/latest

Test location /workspace/coverage/default/36.hmac_error.1631647983
Short name T294
Test name
Test status
Simulation time 2385507982 ps
CPU time 67.19 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:05:15 PM PDT 24
Peak memory 200284 kb
Host smart-73b6b0cd-5fb3-4c50-ae29-29eb862b352b
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631647983 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_error.1631647983
Directory /workspace/36.hmac_error/latest

Test location /workspace/coverage/default/36.hmac_long_msg.3188944394
Short name T230
Test name
Test status
Simulation time 631030067 ps
CPU time 35.02 seconds
Started Jun 28 05:03:55 PM PDT 24
Finished Jun 28 05:04:30 PM PDT 24
Peak memory 200224 kb
Host smart-49f7139b-507a-4ccd-b596-77b921e1bff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188944394 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_long_msg.3188944394
Directory /workspace/36.hmac_long_msg/latest

Test location /workspace/coverage/default/36.hmac_smoke.2923757379
Short name T762
Test name
Test status
Simulation time 132617826 ps
CPU time 6.65 seconds
Started Jun 28 05:03:56 PM PDT 24
Finished Jun 28 05:04:03 PM PDT 24
Peak memory 200316 kb
Host smart-b9b0e845-52fc-435f-b0a9-67babc0003e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923757379 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_smoke.2923757379
Directory /workspace/36.hmac_smoke/latest

Test location /workspace/coverage/default/36.hmac_stress_all.3839778627
Short name T751
Test name
Test status
Simulation time 92192161563 ps
CPU time 1740.02 seconds
Started Jun 28 05:04:10 PM PDT 24
Finished Jun 28 05:33:11 PM PDT 24
Peak memory 763292 kb
Host smart-cdb65d61-22f5-4a8d-85ab-b49da062ffef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839778627 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.hmac_stress_all.3839778627
Directory /workspace/36.hmac_stress_all/latest

Test location /workspace/coverage/default/36.hmac_test_hmac256_vectors.3517994930
Short name T426
Test name
Test status
Simulation time 3663434809 ps
CPU time 28.85 seconds
Started Jun 28 05:04:08 PM PDT 24
Finished Jun 28 05:04:37 PM PDT 24
Peak memory 200276 kb
Host smart-f11b5f61-08f0-4afd-a39a-65c030d21823
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3517994930 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac256_vectors.3517994930
Directory /workspace/36.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_hmac384_vectors.2074346894
Short name T791
Test name
Test status
Simulation time 11576128241 ps
CPU time 44.21 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:04:52 PM PDT 24
Peak memory 200296 kb
Host smart-50fb1b94-af18-4d88-bd8d-877d84ca57a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2074346894 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac384_vectors.2074346894
Directory /workspace/36.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_hmac512_vectors.3655668047
Short name T722
Test name
Test status
Simulation time 94478106321 ps
CPU time 106.74 seconds
Started Jun 28 05:04:06 PM PDT 24
Finished Jun 28 05:05:54 PM PDT 24
Peak memory 200364 kb
Host smart-915f10f6-9ffe-45e1-a1d3-c8601af2468a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3655668047 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_hmac512_vectors.3655668047
Directory /workspace/36.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha256_vectors.2163963472
Short name T101
Test name
Test status
Simulation time 190089355329 ps
CPU time 419.75 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:11:07 PM PDT 24
Peak memory 200260 kb
Host smart-6567c3f0-e802-4866-bf2c-ac66000c5470
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2163963472 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha256_vectors.2163963472
Directory /workspace/36.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha384_vectors.3004441732
Short name T542
Test name
Test status
Simulation time 135496799684 ps
CPU time 1744.35 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:33:12 PM PDT 24
Peak memory 216216 kb
Host smart-7dc23a2b-10af-491b-88a1-9379ce6e2c42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3004441732 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha384_vectors.3004441732
Directory /workspace/36.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/36.hmac_test_sha512_vectors.2336418177
Short name T258
Test name
Test status
Simulation time 911982521166 ps
CPU time 2248.23 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:41:36 PM PDT 24
Peak memory 215732 kb
Host smart-164b0526-187f-4425-93c5-64929775f818
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2336418177 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_test_sha512_vectors.2336418177
Directory /workspace/36.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/36.hmac_wipe_secret.3161875375
Short name T591
Test name
Test status
Simulation time 120787655 ps
CPU time 3.58 seconds
Started Jun 28 05:04:06 PM PDT 24
Finished Jun 28 05:04:10 PM PDT 24
Peak memory 200212 kb
Host smart-8ab60484-7274-4cdc-ba12-f147ae6a9c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161875375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.hmac_wipe_secret.3161875375
Directory /workspace/36.hmac_wipe_secret/latest

Test location /workspace/coverage/default/37.hmac_alert_test.2887804829
Short name T661
Test name
Test status
Simulation time 53638292 ps
CPU time 0.63 seconds
Started Jun 28 05:04:20 PM PDT 24
Finished Jun 28 05:04:21 PM PDT 24
Peak memory 196228 kb
Host smart-c8f16919-295b-4366-b65a-4d6402ebd8e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887804829 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_alert_test.2887804829
Directory /workspace/37.hmac_alert_test/latest

Test location /workspace/coverage/default/37.hmac_back_pressure.3094282689
Short name T278
Test name
Test status
Simulation time 104370319 ps
CPU time 6.45 seconds
Started Jun 28 05:04:09 PM PDT 24
Finished Jun 28 05:04:16 PM PDT 24
Peak memory 200056 kb
Host smart-08b4b372-35ea-44ed-b584-67ec248682ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3094282689 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_back_pressure.3094282689
Directory /workspace/37.hmac_back_pressure/latest

Test location /workspace/coverage/default/37.hmac_burst_wr.1905767996
Short name T586
Test name
Test status
Simulation time 7703537662 ps
CPU time 44.85 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:04:53 PM PDT 24
Peak memory 200340 kb
Host smart-a6b121dc-cfe7-48de-89f5-cafa1107e70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905767996 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_burst_wr.1905767996
Directory /workspace/37.hmac_burst_wr/latest

Test location /workspace/coverage/default/37.hmac_datapath_stress.2080555186
Short name T281
Test name
Test status
Simulation time 5819236143 ps
CPU time 1088.77 seconds
Started Jun 28 05:04:06 PM PDT 24
Finished Jun 28 05:22:15 PM PDT 24
Peak memory 773704 kb
Host smart-08a6829b-cc21-4034-8ba8-46a62601811f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080555186 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_datapath_stress.2080555186
Directory /workspace/37.hmac_datapath_stress/latest

Test location /workspace/coverage/default/37.hmac_error.2997589904
Short name T767
Test name
Test status
Simulation time 6853303719 ps
CPU time 148.68 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:06:36 PM PDT 24
Peak memory 200328 kb
Host smart-4b82327f-4f44-493c-be0d-b13057b66c46
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997589904 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_error.2997589904
Directory /workspace/37.hmac_error/latest

Test location /workspace/coverage/default/37.hmac_long_msg.3354997365
Short name T463
Test name
Test status
Simulation time 4161890221 ps
CPU time 7.39 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:04:15 PM PDT 24
Peak memory 200416 kb
Host smart-d3e724ff-db04-4bf8-bb25-3abc5796295e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354997365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_long_msg.3354997365
Directory /workspace/37.hmac_long_msg/latest

Test location /workspace/coverage/default/37.hmac_smoke.3492175418
Short name T444
Test name
Test status
Simulation time 288092581 ps
CPU time 3.23 seconds
Started Jun 28 05:04:08 PM PDT 24
Finished Jun 28 05:04:12 PM PDT 24
Peak memory 200316 kb
Host smart-54ceb69a-a657-4f01-81dc-e766c8275b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492175418 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_smoke.3492175418
Directory /workspace/37.hmac_smoke/latest

Test location /workspace/coverage/default/37.hmac_test_hmac256_vectors.2891017019
Short name T251
Test name
Test status
Simulation time 5976596815 ps
CPU time 73.66 seconds
Started Jun 28 05:04:10 PM PDT 24
Finished Jun 28 05:05:24 PM PDT 24
Peak memory 200332 kb
Host smart-ee71430c-2f5d-4ffc-8618-ac9baa5b39ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2891017019 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac256_vectors.2891017019
Directory /workspace/37.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_hmac384_vectors.3640333949
Short name T645
Test name
Test status
Simulation time 6468628378 ps
CPU time 78.43 seconds
Started Jun 28 05:04:22 PM PDT 24
Finished Jun 28 05:05:41 PM PDT 24
Peak memory 200288 kb
Host smart-088bfbff-d547-41e0-b1e6-5575e38537ad
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3640333949 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac384_vectors.3640333949
Directory /workspace/37.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_hmac512_vectors.2379388155
Short name T624
Test name
Test status
Simulation time 11181615803 ps
CPU time 58.55 seconds
Started Jun 28 05:04:21 PM PDT 24
Finished Jun 28 05:05:20 PM PDT 24
Peak memory 200328 kb
Host smart-d2e6e8b9-08f3-40af-b4d6-1163d5debe3e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2379388155 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_hmac512_vectors.2379388155
Directory /workspace/37.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha256_vectors.22096577
Short name T483
Test name
Test status
Simulation time 28208028014 ps
CPU time 408.82 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:10:56 PM PDT 24
Peak memory 200488 kb
Host smart-ffcaafa4-2d3c-4ce3-87b2-f67a2bc36f65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=22096577 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha256_vectors.22096577
Directory /workspace/37.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha384_vectors.3767852824
Short name T573
Test name
Test status
Simulation time 829307897089 ps
CPU time 2191.26 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:40:39 PM PDT 24
Peak memory 216268 kb
Host smart-21421d9f-1df1-4a95-88cc-8a2da061854d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3767852824 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha384_vectors.3767852824
Directory /workspace/37.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/37.hmac_test_sha512_vectors.1019448076
Short name T362
Test name
Test status
Simulation time 241620882922 ps
CPU time 1852.5 seconds
Started Jun 28 05:04:07 PM PDT 24
Finished Jun 28 05:35:01 PM PDT 24
Peak memory 216640 kb
Host smart-1a47532b-338e-4346-947a-87c7ed02282c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1019448076 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_test_sha512_vectors.1019448076
Directory /workspace/37.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/37.hmac_wipe_secret.2670895395
Short name T268
Test name
Test status
Simulation time 5588441335 ps
CPU time 40.93 seconds
Started Jun 28 05:04:08 PM PDT 24
Finished Jun 28 05:04:50 PM PDT 24
Peak memory 200380 kb
Host smart-970aaaf6-55da-4a8e-949d-f9121f042005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670895395 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.hmac_wipe_secret.2670895395
Directory /workspace/37.hmac_wipe_secret/latest

Test location /workspace/coverage/default/38.hmac_alert_test.4048839475
Short name T740
Test name
Test status
Simulation time 30590907 ps
CPU time 0.61 seconds
Started Jun 28 05:04:21 PM PDT 24
Finished Jun 28 05:04:22 PM PDT 24
Peak memory 196284 kb
Host smart-b00e30d0-bdfa-4300-a970-36793e30aa16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048839475 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_alert_test.4048839475
Directory /workspace/38.hmac_alert_test/latest

Test location /workspace/coverage/default/38.hmac_back_pressure.2010688150
Short name T701
Test name
Test status
Simulation time 969648041 ps
CPU time 51.92 seconds
Started Jun 28 05:04:19 PM PDT 24
Finished Jun 28 05:05:11 PM PDT 24
Peak memory 200260 kb
Host smart-a7577875-7643-4214-8f61-7b4da7c37320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2010688150 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_back_pressure.2010688150
Directory /workspace/38.hmac_back_pressure/latest

Test location /workspace/coverage/default/38.hmac_burst_wr.913492610
Short name T565
Test name
Test status
Simulation time 423328302 ps
CPU time 23.12 seconds
Started Jun 28 05:04:19 PM PDT 24
Finished Jun 28 05:04:43 PM PDT 24
Peak memory 200292 kb
Host smart-a09b6bf2-27b1-4cfc-8010-933f7a44bb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913492610 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_burst_wr.913492610
Directory /workspace/38.hmac_burst_wr/latest

Test location /workspace/coverage/default/38.hmac_datapath_stress.3466927806
Short name T507
Test name
Test status
Simulation time 13143575864 ps
CPU time 1054.28 seconds
Started Jun 28 05:04:19 PM PDT 24
Finished Jun 28 05:21:54 PM PDT 24
Peak memory 752596 kb
Host smart-05311d01-0ad8-4748-b0c9-00e4fc65b3fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466927806 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_datapath_stress.3466927806
Directory /workspace/38.hmac_datapath_stress/latest

Test location /workspace/coverage/default/38.hmac_error.3177852410
Short name T606
Test name
Test status
Simulation time 11628578116 ps
CPU time 206.57 seconds
Started Jun 28 05:04:20 PM PDT 24
Finished Jun 28 05:07:47 PM PDT 24
Peak memory 200288 kb
Host smart-ff9b1ecc-d55c-4a70-b75b-ef21e33d82d4
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177852410 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_error.3177852410
Directory /workspace/38.hmac_error/latest

Test location /workspace/coverage/default/38.hmac_long_msg.3908681670
Short name T40
Test name
Test status
Simulation time 3517162085 ps
CPU time 57.73 seconds
Started Jun 28 05:04:21 PM PDT 24
Finished Jun 28 05:05:19 PM PDT 24
Peak memory 200376 kb
Host smart-702d3e85-1cd1-4d1a-8b54-d6868dcf1d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908681670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_long_msg.3908681670
Directory /workspace/38.hmac_long_msg/latest

Test location /workspace/coverage/default/38.hmac_smoke.639127837
Short name T76
Test name
Test status
Simulation time 787899225 ps
CPU time 5 seconds
Started Jun 28 05:04:21 PM PDT 24
Finished Jun 28 05:04:27 PM PDT 24
Peak memory 200316 kb
Host smart-89d1efc1-569b-4745-90e0-4321a733aca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639127837 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_smoke.639127837
Directory /workspace/38.hmac_smoke/latest

Test location /workspace/coverage/default/38.hmac_stress_all.1757487454
Short name T627
Test name
Test status
Simulation time 9923752319 ps
CPU time 136.74 seconds
Started Jun 28 05:04:19 PM PDT 24
Finished Jun 28 05:06:36 PM PDT 24
Peak memory 216612 kb
Host smart-19c5ad9d-5dc1-4851-ac4d-e327e7bd82ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757487454 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.hmac_stress_all.1757487454
Directory /workspace/38.hmac_stress_all/latest

Test location /workspace/coverage/default/38.hmac_test_hmac256_vectors.3396422101
Short name T719
Test name
Test status
Simulation time 16452561586 ps
CPU time 76.15 seconds
Started Jun 28 05:04:21 PM PDT 24
Finished Jun 28 05:05:38 PM PDT 24
Peak memory 200324 kb
Host smart-f0a5ffbc-0a89-4258-a567-845986fa259f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3396422101 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac256_vectors.3396422101
Directory /workspace/38.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_hmac384_vectors.2086681742
Short name T233
Test name
Test status
Simulation time 20127880644 ps
CPU time 58.08 seconds
Started Jun 28 05:04:23 PM PDT 24
Finished Jun 28 05:05:21 PM PDT 24
Peak memory 200300 kb
Host smart-56a23113-495d-4f80-bc64-47e25bfc722f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2086681742 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac384_vectors.2086681742
Directory /workspace/38.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_hmac512_vectors.1756853760
Short name T419
Test name
Test status
Simulation time 9167545896 ps
CPU time 71.9 seconds
Started Jun 28 05:04:22 PM PDT 24
Finished Jun 28 05:05:34 PM PDT 24
Peak memory 200324 kb
Host smart-16df0503-8ea6-4e89-9dfe-a8204a8364d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1756853760 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_hmac512_vectors.1756853760
Directory /workspace/38.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha256_vectors.3649519110
Short name T709
Test name
Test status
Simulation time 28358564734 ps
CPU time 479.59 seconds
Started Jun 28 05:04:21 PM PDT 24
Finished Jun 28 05:12:21 PM PDT 24
Peak memory 200220 kb
Host smart-07e150b7-508a-4038-a379-c9f66cbdc2af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3649519110 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha256_vectors.3649519110
Directory /workspace/38.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha384_vectors.917773867
Short name T566
Test name
Test status
Simulation time 132982427477 ps
CPU time 1845.62 seconds
Started Jun 28 05:04:20 PM PDT 24
Finished Jun 28 05:35:06 PM PDT 24
Peak memory 216608 kb
Host smart-f7d9d64e-279e-4875-9a46-58e5428dd090
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=917773867 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha384_vectors.917773867
Directory /workspace/38.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/38.hmac_test_sha512_vectors.2964521008
Short name T227
Test name
Test status
Simulation time 32237161106 ps
CPU time 1890.31 seconds
Started Jun 28 05:04:20 PM PDT 24
Finished Jun 28 05:35:51 PM PDT 24
Peak memory 215660 kb
Host smart-a3f2bd52-e8df-4094-b9dc-e6f496130b1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2964521008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_test_sha512_vectors.2964521008
Directory /workspace/38.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/38.hmac_wipe_secret.361210816
Short name T300
Test name
Test status
Simulation time 40964440921 ps
CPU time 103.73 seconds
Started Jun 28 05:04:19 PM PDT 24
Finished Jun 28 05:06:03 PM PDT 24
Peak memory 200312 kb
Host smart-8ed172bc-dbbd-4b87-be5a-bdcdbf8a7b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361210816 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.hmac_wipe_secret.361210816
Directory /workspace/38.hmac_wipe_secret/latest

Test location /workspace/coverage/default/39.hmac_alert_test.3646200126
Short name T589
Test name
Test status
Simulation time 51809107 ps
CPU time 0.61 seconds
Started Jun 28 05:04:32 PM PDT 24
Finished Jun 28 05:04:34 PM PDT 24
Peak memory 196960 kb
Host smart-73f4ab84-bced-4b08-a82c-22f29ce79f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646200126 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_alert_test.3646200126
Directory /workspace/39.hmac_alert_test/latest

Test location /workspace/coverage/default/39.hmac_back_pressure.1048356699
Short name T650
Test name
Test status
Simulation time 2523763843 ps
CPU time 36.66 seconds
Started Jun 28 05:04:33 PM PDT 24
Finished Jun 28 05:05:11 PM PDT 24
Peak memory 200240 kb
Host smart-e6c1ae7d-19ac-4b81-a231-b646ebcfab11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1048356699 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_back_pressure.1048356699
Directory /workspace/39.hmac_back_pressure/latest

Test location /workspace/coverage/default/39.hmac_burst_wr.3561095317
Short name T718
Test name
Test status
Simulation time 1526855998 ps
CPU time 39.12 seconds
Started Jun 28 05:04:30 PM PDT 24
Finished Jun 28 05:05:10 PM PDT 24
Peak memory 200292 kb
Host smart-866e488f-a582-4c4d-bdae-986ee03f992e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561095317 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_burst_wr.3561095317
Directory /workspace/39.hmac_burst_wr/latest

Test location /workspace/coverage/default/39.hmac_error.254666428
Short name T350
Test name
Test status
Simulation time 2206343823 ps
CPU time 131.17 seconds
Started Jun 28 05:04:31 PM PDT 24
Finished Jun 28 05:06:43 PM PDT 24
Peak memory 200352 kb
Host smart-32d340cc-7b8c-43a5-87ed-e298321f28d2
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254666428 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_error.254666428
Directory /workspace/39.hmac_error/latest

Test location /workspace/coverage/default/39.hmac_long_msg.1246015518
Short name T295
Test name
Test status
Simulation time 3233510459 ps
CPU time 43.93 seconds
Started Jun 28 05:04:30 PM PDT 24
Finished Jun 28 05:05:15 PM PDT 24
Peak memory 200380 kb
Host smart-cbe30444-e69a-4d67-b17f-5dc1ea7d6f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246015518 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_long_msg.1246015518
Directory /workspace/39.hmac_long_msg/latest

Test location /workspace/coverage/default/39.hmac_smoke.2422434974
Short name T383
Test name
Test status
Simulation time 838426130 ps
CPU time 10.7 seconds
Started Jun 28 05:04:33 PM PDT 24
Finished Jun 28 05:04:44 PM PDT 24
Peak memory 200256 kb
Host smart-f2e5ad8a-815d-47ce-b8c7-8182f9011457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422434974 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_smoke.2422434974
Directory /workspace/39.hmac_smoke/latest

Test location /workspace/coverage/default/39.hmac_stress_all.261946753
Short name T677
Test name
Test status
Simulation time 14826695082 ps
CPU time 895.7 seconds
Started Jun 28 05:04:33 PM PDT 24
Finished Jun 28 05:19:31 PM PDT 24
Peak memory 732880 kb
Host smart-ad2c6f38-a825-4e07-865a-44b6bfce36a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261946753 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.hmac_stress_all.261946753
Directory /workspace/39.hmac_stress_all/latest

Test location /workspace/coverage/default/39.hmac_test_hmac256_vectors.765831413
Short name T757
Test name
Test status
Simulation time 47890217422 ps
CPU time 65.38 seconds
Started Jun 28 05:04:33 PM PDT 24
Finished Jun 28 05:05:40 PM PDT 24
Peak memory 200300 kb
Host smart-c5702bdf-f98e-4f54-aa74-b984b8546f1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=765831413 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac256_vectors.765831413
Directory /workspace/39.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_hmac384_vectors.3901443788
Short name T749
Test name
Test status
Simulation time 3035336503 ps
CPU time 53 seconds
Started Jun 28 05:04:31 PM PDT 24
Finished Jun 28 05:05:25 PM PDT 24
Peak memory 200328 kb
Host smart-21fd839b-53c9-4894-9c9b-fd46b8adbd98
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3901443788 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac384_vectors.3901443788
Directory /workspace/39.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_hmac512_vectors.717517354
Short name T41
Test name
Test status
Simulation time 13592751365 ps
CPU time 71.32 seconds
Started Jun 28 05:04:30 PM PDT 24
Finished Jun 28 05:05:42 PM PDT 24
Peak memory 200328 kb
Host smart-db348c8a-8c35-4e6b-8e21-f759191792c6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=717517354 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_hmac512_vectors.717517354
Directory /workspace/39.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha256_vectors.75818296
Short name T472
Test name
Test status
Simulation time 33071482245 ps
CPU time 503.43 seconds
Started Jun 28 05:04:30 PM PDT 24
Finished Jun 28 05:12:54 PM PDT 24
Peak memory 200296 kb
Host smart-39f50081-bee3-44dd-8db8-10ae84862acd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=75818296 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha256_vectors.75818296
Directory /workspace/39.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha384_vectors.570765214
Short name T781
Test name
Test status
Simulation time 130651243804 ps
CPU time 1716.27 seconds
Started Jun 28 05:04:31 PM PDT 24
Finished Jun 28 05:33:08 PM PDT 24
Peak memory 216680 kb
Host smart-63f3bd2c-5ee1-4428-a08c-8ed49ecc270b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=570765214 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha384_vectors.570765214
Directory /workspace/39.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/39.hmac_test_sha512_vectors.3143115415
Short name T558
Test name
Test status
Simulation time 105398003596 ps
CPU time 1852.09 seconds
Started Jun 28 05:04:31 PM PDT 24
Finished Jun 28 05:35:24 PM PDT 24
Peak memory 216676 kb
Host smart-71f37856-ee9e-484b-9fe3-f896899b384e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3143115415 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_test_sha512_vectors.3143115415
Directory /workspace/39.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/39.hmac_wipe_secret.139121864
Short name T132
Test name
Test status
Simulation time 6661418542 ps
CPU time 75.28 seconds
Started Jun 28 05:04:32 PM PDT 24
Finished Jun 28 05:05:48 PM PDT 24
Peak memory 200284 kb
Host smart-95c474ac-6ba6-4839-b5ab-55c5d89e01b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139121864 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.hmac_wipe_secret.139121864
Directory /workspace/39.hmac_wipe_secret/latest

Test location /workspace/coverage/default/4.hmac_alert_test.4040860448
Short name T685
Test name
Test status
Simulation time 11206434 ps
CPU time 0.58 seconds
Started Jun 28 05:00:18 PM PDT 24
Finished Jun 28 05:00:20 PM PDT 24
Peak memory 195876 kb
Host smart-a01ee4b4-cdfa-41d8-8fd5-5556adb8f5e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040860448 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_alert_test.4040860448
Directory /workspace/4.hmac_alert_test/latest

Test location /workspace/coverage/default/4.hmac_back_pressure.4282734387
Short name T547
Test name
Test status
Simulation time 9319720043 ps
CPU time 42.12 seconds
Started Jun 28 05:00:10 PM PDT 24
Finished Jun 28 05:00:53 PM PDT 24
Peak memory 200220 kb
Host smart-8458bb19-b788-490d-9f0c-380c0d8dedcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4282734387 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_back_pressure.4282734387
Directory /workspace/4.hmac_back_pressure/latest

Test location /workspace/coverage/default/4.hmac_burst_wr.2697195749
Short name T274
Test name
Test status
Simulation time 3142916795 ps
CPU time 49.98 seconds
Started Jun 28 05:00:17 PM PDT 24
Finished Jun 28 05:01:08 PM PDT 24
Peak memory 200352 kb
Host smart-812c26b5-82d8-4651-b223-5ab4b98bccff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697195749 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_burst_wr.2697195749
Directory /workspace/4.hmac_burst_wr/latest

Test location /workspace/coverage/default/4.hmac_datapath_stress.2744528213
Short name T3
Test name
Test status
Simulation time 2277763742 ps
CPU time 546.8 seconds
Started Jun 28 05:00:04 PM PDT 24
Finished Jun 28 05:09:12 PM PDT 24
Peak memory 693580 kb
Host smart-d18b1ce6-e273-4eed-8588-9c08b375607f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744528213 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_datapath_stress.2744528213
Directory /workspace/4.hmac_datapath_stress/latest

Test location /workspace/coverage/default/4.hmac_error.3741842982
Short name T489
Test name
Test status
Simulation time 33806691049 ps
CPU time 147.72 seconds
Started Jun 28 05:00:15 PM PDT 24
Finished Jun 28 05:02:44 PM PDT 24
Peak memory 200320 kb
Host smart-0c660c86-1321-4ab5-b0cd-5d21221d46ee
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741842982 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_error.3741842982
Directory /workspace/4.hmac_error/latest

Test location /workspace/coverage/default/4.hmac_long_msg.940211821
Short name T348
Test name
Test status
Simulation time 802305953 ps
CPU time 47.35 seconds
Started Jun 28 05:00:05 PM PDT 24
Finished Jun 28 05:00:53 PM PDT 24
Peak memory 200240 kb
Host smart-afc47926-55b1-4e21-a2d5-fa23173ec889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940211821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_long_msg.940211821
Directory /workspace/4.hmac_long_msg/latest

Test location /workspace/coverage/default/4.hmac_sec_cm.2900100613
Short name T51
Test name
Test status
Simulation time 88982056 ps
CPU time 0.99 seconds
Started Jun 28 05:00:18 PM PDT 24
Finished Jun 28 05:00:20 PM PDT 24
Peak memory 219760 kb
Host smart-3935ebec-d62e-4212-b386-b6f579d777b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900100613 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_sec_cm.2900100613
Directory /workspace/4.hmac_sec_cm/latest

Test location /workspace/coverage/default/4.hmac_smoke.1466722129
Short name T361
Test name
Test status
Simulation time 528367148 ps
CPU time 5.07 seconds
Started Jun 28 05:00:04 PM PDT 24
Finished Jun 28 05:00:10 PM PDT 24
Peak memory 200276 kb
Host smart-95b8d9c8-edf3-4141-8982-376de0b3dc77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466722129 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_smoke.1466722129
Directory /workspace/4.hmac_smoke/latest

Test location /workspace/coverage/default/4.hmac_stress_all.325167497
Short name T598
Test name
Test status
Simulation time 2646227592 ps
CPU time 36.24 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:00:54 PM PDT 24
Peak memory 200444 kb
Host smart-ec6f2c5b-d7f1-42c2-884e-d3c24dd674d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325167497 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.hmac_stress_all.325167497
Directory /workspace/4.hmac_stress_all/latest

Test location /workspace/coverage/default/4.hmac_test_hmac256_vectors.2004227283
Short name T219
Test name
Test status
Simulation time 1416213255 ps
CPU time 53.77 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:01:11 PM PDT 24
Peak memory 200268 kb
Host smart-fa8017fa-dff4-4166-b155-5ad5d6a60ffe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2004227283 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac256_vectors.2004227283
Directory /workspace/4.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac384_vectors.4139485008
Short name T632
Test name
Test status
Simulation time 12192499915 ps
CPU time 45.1 seconds
Started Jun 28 05:00:17 PM PDT 24
Finished Jun 28 05:01:03 PM PDT 24
Peak memory 200320 kb
Host smart-f16d71a3-ecea-4e86-af94-f81c2a101c09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4139485008 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac384_vectors.4139485008
Directory /workspace/4.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_hmac512_vectors.772706920
Short name T400
Test name
Test status
Simulation time 8665142081 ps
CPU time 101.38 seconds
Started Jun 28 05:00:17 PM PDT 24
Finished Jun 28 05:02:00 PM PDT 24
Peak memory 200344 kb
Host smart-59ecf3ea-95f2-420a-a752-328fb87154b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=772706920 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_hmac512_vectors.772706920
Directory /workspace/4.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha256_vectors.1467783906
Short name T745
Test name
Test status
Simulation time 35435637586 ps
CPU time 476.26 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:08:14 PM PDT 24
Peak memory 200256 kb
Host smart-47521c9f-c9b8-4f9b-a974-9ebc2552a54a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1467783906 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha256_vectors.1467783906
Directory /workspace/4.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha384_vectors.3320315430
Short name T435
Test name
Test status
Simulation time 113303079364 ps
CPU time 2017.57 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:33:54 PM PDT 24
Peak memory 216164 kb
Host smart-4f4dfbbf-4aad-4cd7-bb41-6721b0af8ca5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3320315430 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha384_vectors.3320315430
Directory /workspace/4.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/4.hmac_test_sha512_vectors.3570729843
Short name T642
Test name
Test status
Simulation time 70367083657 ps
CPU time 1953.06 seconds
Started Jun 28 05:00:15 PM PDT 24
Finished Jun 28 05:32:49 PM PDT 24
Peak memory 215776 kb
Host smart-cbc769a4-0a1a-4300-ba1a-9dc4b14ab1f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3570729843 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_test_sha512_vectors.3570729843
Directory /workspace/4.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/4.hmac_wipe_secret.83598617
Short name T97
Test name
Test status
Simulation time 25216576228 ps
CPU time 84.88 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:01:41 PM PDT 24
Peak memory 200336 kb
Host smart-a0826e53-6735-43e2-8f13-ac0607174786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83598617 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.hmac_wipe_secret.83598617
Directory /workspace/4.hmac_wipe_secret/latest

Test location /workspace/coverage/default/40.hmac_alert_test.1178943901
Short name T695
Test name
Test status
Simulation time 29680983 ps
CPU time 0.63 seconds
Started Jun 28 05:04:47 PM PDT 24
Finished Jun 28 05:04:48 PM PDT 24
Peak memory 195192 kb
Host smart-ffd088fc-ed4f-4352-b7d7-bd70276abc7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178943901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_alert_test.1178943901
Directory /workspace/40.hmac_alert_test/latest

Test location /workspace/coverage/default/40.hmac_back_pressure.1225473476
Short name T264
Test name
Test status
Simulation time 4028808968 ps
CPU time 55.93 seconds
Started Jun 28 05:04:31 PM PDT 24
Finished Jun 28 05:05:28 PM PDT 24
Peak memory 208532 kb
Host smart-f15b19ac-d84d-4074-b4e2-ef870f3c36be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225473476 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_back_pressure.1225473476
Directory /workspace/40.hmac_back_pressure/latest

Test location /workspace/coverage/default/40.hmac_datapath_stress.992359310
Short name T259
Test name
Test status
Simulation time 41300703 ps
CPU time 0.71 seconds
Started Jun 28 05:04:32 PM PDT 24
Finished Jun 28 05:04:33 PM PDT 24
Peak memory 198416 kb
Host smart-2eca5ac4-690a-4e8f-ab34-947aead428d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=992359310 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_datapath_stress.992359310
Directory /workspace/40.hmac_datapath_stress/latest

Test location /workspace/coverage/default/40.hmac_error.1846134707
Short name T454
Test name
Test status
Simulation time 16621836698 ps
CPU time 136.96 seconds
Started Jun 28 05:04:43 PM PDT 24
Finished Jun 28 05:07:00 PM PDT 24
Peak memory 200296 kb
Host smart-127d814e-282f-4578-b2fa-7a10a6737b3f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846134707 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_error.1846134707
Directory /workspace/40.hmac_error/latest

Test location /workspace/coverage/default/40.hmac_long_msg.788298033
Short name T717
Test name
Test status
Simulation time 1563861735 ps
CPU time 101.79 seconds
Started Jun 28 05:04:31 PM PDT 24
Finished Jun 28 05:06:14 PM PDT 24
Peak memory 200264 kb
Host smart-0e63ad38-3ea3-4f18-9ef3-54c44e0d3628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788298033 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_long_msg.788298033
Directory /workspace/40.hmac_long_msg/latest

Test location /workspace/coverage/default/40.hmac_smoke.1162196157
Short name T655
Test name
Test status
Simulation time 404311072 ps
CPU time 5.72 seconds
Started Jun 28 05:04:31 PM PDT 24
Finished Jun 28 05:04:37 PM PDT 24
Peak memory 200204 kb
Host smart-8828d4e4-79a3-41d9-9988-e3c3779504c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162196157 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_smoke.1162196157
Directory /workspace/40.hmac_smoke/latest

Test location /workspace/coverage/default/40.hmac_stress_all.3927245691
Short name T93
Test name
Test status
Simulation time 322936230864 ps
CPU time 5127.36 seconds
Started Jun 28 05:04:41 PM PDT 24
Finished Jun 28 06:30:09 PM PDT 24
Peak memory 764244 kb
Host smart-33b48de0-74ca-42e3-b476-a74e8c324097
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927245691 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.hmac_stress_all.3927245691
Directory /workspace/40.hmac_stress_all/latest

Test location /workspace/coverage/default/40.hmac_test_hmac256_vectors.3304194462
Short name T711
Test name
Test status
Simulation time 887976943 ps
CPU time 29.22 seconds
Started Jun 28 05:04:42 PM PDT 24
Finished Jun 28 05:05:12 PM PDT 24
Peak memory 200208 kb
Host smart-495b893f-b6c7-4849-bc81-3bbb75de3ea0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3304194462 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac256_vectors.3304194462
Directory /workspace/40.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_hmac384_vectors.2979911932
Short name T96
Test name
Test status
Simulation time 40307777531 ps
CPU time 84.29 seconds
Started Jun 28 05:04:41 PM PDT 24
Finished Jun 28 05:06:06 PM PDT 24
Peak memory 200364 kb
Host smart-8a8d7c06-a99c-41b3-ba9e-e7f77e69bc41
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2979911932 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac384_vectors.2979911932
Directory /workspace/40.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_hmac512_vectors.559358063
Short name T314
Test name
Test status
Simulation time 16536540907 ps
CPU time 71.13 seconds
Started Jun 28 05:04:48 PM PDT 24
Finished Jun 28 05:05:59 PM PDT 24
Peak memory 200296 kb
Host smart-dfcdad96-2697-43f0-a6e4-35711670ce52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=559358063 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_hmac512_vectors.559358063
Directory /workspace/40.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha256_vectors.2060272838
Short name T175
Test name
Test status
Simulation time 54592841663 ps
CPU time 511.02 seconds
Started Jun 28 05:04:43 PM PDT 24
Finished Jun 28 05:13:14 PM PDT 24
Peak memory 200256 kb
Host smart-ca6dd964-2e74-44ca-966d-e6804611d6e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2060272838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha256_vectors.2060272838
Directory /workspace/40.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha384_vectors.2162621572
Short name T341
Test name
Test status
Simulation time 31715324303 ps
CPU time 1919.73 seconds
Started Jun 28 05:04:43 PM PDT 24
Finished Jun 28 05:36:43 PM PDT 24
Peak memory 215716 kb
Host smart-de0dc699-cdb8-4ee3-bfe1-8bd02280f8fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2162621572 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha384_vectors.2162621572
Directory /workspace/40.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/40.hmac_test_sha512_vectors.3555332225
Short name T485
Test name
Test status
Simulation time 150356779461 ps
CPU time 1936.89 seconds
Started Jun 28 05:04:41 PM PDT 24
Finished Jun 28 05:36:58 PM PDT 24
Peak memory 216420 kb
Host smart-c7316e9a-afbb-4471-92d1-f97f381b8704
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3555332225 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_test_sha512_vectors.3555332225
Directory /workspace/40.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/40.hmac_wipe_secret.2634928351
Short name T736
Test name
Test status
Simulation time 3643934225 ps
CPU time 32.6 seconds
Started Jun 28 05:04:42 PM PDT 24
Finished Jun 28 05:05:16 PM PDT 24
Peak memory 200380 kb
Host smart-c1d07cf0-9de7-45d0-a13d-a80272bd078d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634928351 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.hmac_wipe_secret.2634928351
Directory /workspace/40.hmac_wipe_secret/latest

Test location /workspace/coverage/default/41.hmac_alert_test.1584757455
Short name T651
Test name
Test status
Simulation time 37233341 ps
CPU time 0.58 seconds
Started Jun 28 05:05:00 PM PDT 24
Finished Jun 28 05:05:01 PM PDT 24
Peak memory 195212 kb
Host smart-e4c8d954-8095-44e7-9766-9d6de8002863
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584757455 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_alert_test.1584757455
Directory /workspace/41.hmac_alert_test/latest

Test location /workspace/coverage/default/41.hmac_burst_wr.1218718483
Short name T33
Test name
Test status
Simulation time 4787612667 ps
CPU time 25.57 seconds
Started Jun 28 05:04:41 PM PDT 24
Finished Jun 28 05:05:07 PM PDT 24
Peak memory 200488 kb
Host smart-19b934eb-ab68-4f5e-a3ac-4f3a28a08c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218718483 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_burst_wr.1218718483
Directory /workspace/41.hmac_burst_wr/latest

Test location /workspace/coverage/default/41.hmac_datapath_stress.1610705654
Short name T622
Test name
Test status
Simulation time 1280867848 ps
CPU time 245.44 seconds
Started Jun 28 05:04:41 PM PDT 24
Finished Jun 28 05:08:47 PM PDT 24
Peak memory 479448 kb
Host smart-d5116be2-0a1f-48c8-bd58-a73058526897
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1610705654 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_datapath_stress.1610705654
Directory /workspace/41.hmac_datapath_stress/latest

Test location /workspace/coverage/default/41.hmac_error.229931858
Short name T138
Test name
Test status
Simulation time 2931685987 ps
CPU time 164.01 seconds
Started Jun 28 05:04:42 PM PDT 24
Finished Jun 28 05:07:27 PM PDT 24
Peak memory 200248 kb
Host smart-62288004-27f8-42eb-9256-8aab637b639f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229931858 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_error.229931858
Directory /workspace/41.hmac_error/latest

Test location /workspace/coverage/default/41.hmac_long_msg.214759034
Short name T458
Test name
Test status
Simulation time 817315911 ps
CPU time 3.69 seconds
Started Jun 28 05:04:46 PM PDT 24
Finished Jun 28 05:04:51 PM PDT 24
Peak memory 200164 kb
Host smart-660264e4-29d1-4e0f-b946-e3a811853763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214759034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_long_msg.214759034
Directory /workspace/41.hmac_long_msg/latest

Test location /workspace/coverage/default/41.hmac_smoke.1635540375
Short name T522
Test name
Test status
Simulation time 3144812788 ps
CPU time 18.21 seconds
Started Jun 28 05:04:42 PM PDT 24
Finished Jun 28 05:05:00 PM PDT 24
Peak memory 200380 kb
Host smart-b72b631f-8d7b-4b57-a67c-084c74fec9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635540375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_smoke.1635540375
Directory /workspace/41.hmac_smoke/latest

Test location /workspace/coverage/default/41.hmac_stress_all.2380530831
Short name T623
Test name
Test status
Simulation time 111445179278 ps
CPU time 4379.7 seconds
Started Jun 28 05:05:01 PM PDT 24
Finished Jun 28 06:18:03 PM PDT 24
Peak memory 773940 kb
Host smart-bede6a4f-9b8b-4169-bbc9-cc989fd21dc4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380530831 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.hmac_stress_all.2380530831
Directory /workspace/41.hmac_stress_all/latest

Test location /workspace/coverage/default/41.hmac_test_hmac256_vectors.1967234346
Short name T495
Test name
Test status
Simulation time 15154970575 ps
CPU time 32.49 seconds
Started Jun 28 05:04:40 PM PDT 24
Finished Jun 28 05:05:13 PM PDT 24
Peak memory 200364 kb
Host smart-0a1a6e34-9237-4b84-871b-89792f167db4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1967234346 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac256_vectors.1967234346
Directory /workspace/41.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_hmac384_vectors.3865124905
Short name T633
Test name
Test status
Simulation time 11931915924 ps
CPU time 88.59 seconds
Started Jun 28 05:05:01 PM PDT 24
Finished Jun 28 05:06:31 PM PDT 24
Peak memory 200324 kb
Host smart-946ca8a9-2831-4a93-887e-14053ad0b30e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3865124905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac384_vectors.3865124905
Directory /workspace/41.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_hmac512_vectors.1154111365
Short name T284
Test name
Test status
Simulation time 3831035978 ps
CPU time 58.46 seconds
Started Jun 28 05:05:01 PM PDT 24
Finished Jun 28 05:06:01 PM PDT 24
Peak memory 200332 kb
Host smart-bb0b8f16-1dd7-474a-b15f-3863a206e571
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1154111365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_hmac512_vectors.1154111365
Directory /workspace/41.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha256_vectors.2574601941
Short name T12
Test name
Test status
Simulation time 30470550016 ps
CPU time 462.58 seconds
Started Jun 28 05:04:43 PM PDT 24
Finished Jun 28 05:12:26 PM PDT 24
Peak memory 200296 kb
Host smart-036e5f02-ba4b-414e-a6c6-9998eb2770bc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2574601941 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha256_vectors.2574601941
Directory /workspace/41.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha384_vectors.3937824838
Short name T103
Test name
Test status
Simulation time 573520992239 ps
CPU time 1979.08 seconds
Started Jun 28 05:04:42 PM PDT 24
Finished Jun 28 05:37:42 PM PDT 24
Peak memory 216648 kb
Host smart-7541c3de-c422-4aaa-a6a6-59ae017a2c95
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3937824838 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha384_vectors.3937824838
Directory /workspace/41.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/41.hmac_test_sha512_vectors.153726189
Short name T263
Test name
Test status
Simulation time 28332590118 ps
CPU time 1556.29 seconds
Started Jun 28 05:04:42 PM PDT 24
Finished Jun 28 05:30:39 PM PDT 24
Peak memory 215764 kb
Host smart-ac430f2c-472e-417b-afdc-60c0b19f22f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=153726189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_test_sha512_vectors.153726189
Directory /workspace/41.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/41.hmac_wipe_secret.2986383001
Short name T678
Test name
Test status
Simulation time 8405360123 ps
CPU time 107.11 seconds
Started Jun 28 05:04:42 PM PDT 24
Finished Jun 28 05:06:30 PM PDT 24
Peak memory 200376 kb
Host smart-b000a34e-15d4-456f-b771-35674175eaf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986383001 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.hmac_wipe_secret.2986383001
Directory /workspace/41.hmac_wipe_secret/latest

Test location /workspace/coverage/default/42.hmac_alert_test.4194826295
Short name T206
Test name
Test status
Simulation time 11511792 ps
CPU time 0.6 seconds
Started Jun 28 05:05:01 PM PDT 24
Finished Jun 28 05:05:03 PM PDT 24
Peak memory 195848 kb
Host smart-6b4c499a-2e34-4c30-8d20-70496e2bec20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194826295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_alert_test.4194826295
Directory /workspace/42.hmac_alert_test/latest

Test location /workspace/coverage/default/42.hmac_back_pressure.1506676990
Short name T229
Test name
Test status
Simulation time 665184489 ps
CPU time 17.65 seconds
Started Jun 28 05:05:02 PM PDT 24
Finished Jun 28 05:05:21 PM PDT 24
Peak memory 200256 kb
Host smart-048aa534-9d5b-42da-beac-1adb3142c601
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1506676990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_back_pressure.1506676990
Directory /workspace/42.hmac_back_pressure/latest

Test location /workspace/coverage/default/42.hmac_burst_wr.3117497098
Short name T6
Test name
Test status
Simulation time 55649686 ps
CPU time 0.67 seconds
Started Jun 28 05:05:00 PM PDT 24
Finished Jun 28 05:05:02 PM PDT 24
Peak memory 196740 kb
Host smart-8a59bf02-58b6-4b2f-aae6-1811b9d7cf72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117497098 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_burst_wr.3117497098
Directory /workspace/42.hmac_burst_wr/latest

Test location /workspace/coverage/default/42.hmac_datapath_stress.1796297537
Short name T476
Test name
Test status
Simulation time 6568222219 ps
CPU time 472.7 seconds
Started Jun 28 05:05:02 PM PDT 24
Finished Jun 28 05:12:56 PM PDT 24
Peak memory 650652 kb
Host smart-495d5377-9f34-4ad1-85a2-e3ea35bed802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1796297537 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_datapath_stress.1796297537
Directory /workspace/42.hmac_datapath_stress/latest

Test location /workspace/coverage/default/42.hmac_error.2513453303
Short name T257
Test name
Test status
Simulation time 17837398086 ps
CPU time 99.83 seconds
Started Jun 28 05:05:02 PM PDT 24
Finished Jun 28 05:06:43 PM PDT 24
Peak memory 200220 kb
Host smart-23f4a03e-b5fe-4876-9e61-9c8183fcf7e0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513453303 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_error.2513453303
Directory /workspace/42.hmac_error/latest

Test location /workspace/coverage/default/42.hmac_long_msg.1108348618
Short name T144
Test name
Test status
Simulation time 12788817111 ps
CPU time 126.21 seconds
Started Jun 28 05:05:01 PM PDT 24
Finished Jun 28 05:07:08 PM PDT 24
Peak memory 216584 kb
Host smart-d4ba58a3-a223-47b7-ae74-2890dded2148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108348618 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_long_msg.1108348618
Directory /workspace/42.hmac_long_msg/latest

Test location /workspace/coverage/default/42.hmac_smoke.3103577833
Short name T189
Test name
Test status
Simulation time 931225547 ps
CPU time 11.56 seconds
Started Jun 28 05:05:02 PM PDT 24
Finished Jun 28 05:05:14 PM PDT 24
Peak memory 200284 kb
Host smart-186a038a-84fa-4540-a745-adde5635482c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103577833 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_smoke.3103577833
Directory /workspace/42.hmac_smoke/latest

Test location /workspace/coverage/default/42.hmac_test_hmac256_vectors.1540044821
Short name T715
Test name
Test status
Simulation time 16498935634 ps
CPU time 62.94 seconds
Started Jun 28 05:05:03 PM PDT 24
Finished Jun 28 05:06:07 PM PDT 24
Peak memory 200288 kb
Host smart-60975a02-b98b-401f-8516-da5fe1328296
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1540044821 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac256_vectors.1540044821
Directory /workspace/42.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_hmac384_vectors.639796244
Short name T668
Test name
Test status
Simulation time 16658262800 ps
CPU time 77.85 seconds
Started Jun 28 05:05:03 PM PDT 24
Finished Jun 28 05:06:21 PM PDT 24
Peak memory 200296 kb
Host smart-026e59ca-d751-454c-835d-90b2a745bd01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=639796244 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac384_vectors.639796244
Directory /workspace/42.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_hmac512_vectors.440351681
Short name T730
Test name
Test status
Simulation time 3798647307 ps
CPU time 56.75 seconds
Started Jun 28 05:05:01 PM PDT 24
Finished Jun 28 05:05:59 PM PDT 24
Peak memory 200408 kb
Host smart-fd441e8c-0ddb-454e-9260-815aa5d8f248
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=440351681 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_hmac512_vectors.440351681
Directory /workspace/42.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha256_vectors.3712298295
Short name T410
Test name
Test status
Simulation time 26414557128 ps
CPU time 394.9 seconds
Started Jun 28 05:05:00 PM PDT 24
Finished Jun 28 05:11:36 PM PDT 24
Peak memory 200220 kb
Host smart-7c0933ce-db66-4204-a3c8-36a75c11e5eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=3712298295 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha256_vectors.3712298295
Directory /workspace/42.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha384_vectors.74028790
Short name T411
Test name
Test status
Simulation time 119176139552 ps
CPU time 2020.87 seconds
Started Jun 28 05:05:00 PM PDT 24
Finished Jun 28 05:38:42 PM PDT 24
Peak memory 215836 kb
Host smart-40654dd3-3dda-47a9-ae00-40b5309c02c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=74028790 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha384_vectors.74028790
Directory /workspace/42.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/42.hmac_test_sha512_vectors.121208777
Short name T734
Test name
Test status
Simulation time 32170090079 ps
CPU time 1871.78 seconds
Started Jun 28 05:05:01 PM PDT 24
Finished Jun 28 05:36:14 PM PDT 24
Peak memory 215640 kb
Host smart-b0c3a8aa-ee16-4eac-a551-4ef500995a3c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=121208777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_test_sha512_vectors.121208777
Directory /workspace/42.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/42.hmac_wipe_secret.1499989046
Short name T787
Test name
Test status
Simulation time 1807493552 ps
CPU time 36.61 seconds
Started Jun 28 05:05:01 PM PDT 24
Finished Jun 28 05:05:39 PM PDT 24
Peak memory 200208 kb
Host smart-247a703f-53a7-4160-a827-3b0ea0fde023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499989046 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.hmac_wipe_secret.1499989046
Directory /workspace/42.hmac_wipe_secret/latest

Test location /workspace/coverage/default/43.hmac_alert_test.1823843274
Short name T533
Test name
Test status
Simulation time 29896511 ps
CPU time 0.57 seconds
Started Jun 28 05:05:13 PM PDT 24
Finished Jun 28 05:05:14 PM PDT 24
Peak memory 195332 kb
Host smart-449fd82c-10bf-47fb-8d96-4d930d2532f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823843274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_alert_test.1823843274
Directory /workspace/43.hmac_alert_test/latest

Test location /workspace/coverage/default/43.hmac_back_pressure.1332951608
Short name T107
Test name
Test status
Simulation time 3470612733 ps
CPU time 45.39 seconds
Started Jun 28 05:04:59 PM PDT 24
Finished Jun 28 05:05:45 PM PDT 24
Peak memory 200300 kb
Host smart-3e086801-6954-4e86-8725-9e967a35ae15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1332951608 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_back_pressure.1332951608
Directory /workspace/43.hmac_back_pressure/latest

Test location /workspace/coverage/default/43.hmac_burst_wr.1610727512
Short name T528
Test name
Test status
Simulation time 1024978640 ps
CPU time 27.33 seconds
Started Jun 28 05:05:13 PM PDT 24
Finished Jun 28 05:05:41 PM PDT 24
Peak memory 200304 kb
Host smart-802771d3-89d6-4326-a576-0e0aad996402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610727512 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_burst_wr.1610727512
Directory /workspace/43.hmac_burst_wr/latest

Test location /workspace/coverage/default/43.hmac_datapath_stress.3509135479
Short name T562
Test name
Test status
Simulation time 10422131619 ps
CPU time 704.08 seconds
Started Jun 28 05:05:13 PM PDT 24
Finished Jun 28 05:16:58 PM PDT 24
Peak memory 733112 kb
Host smart-f3fb4201-c365-4e87-9c6d-ff35f081fafe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3509135479 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_datapath_stress.3509135479
Directory /workspace/43.hmac_datapath_stress/latest

Test location /workspace/coverage/default/43.hmac_error.2360402034
Short name T369
Test name
Test status
Simulation time 26306388152 ps
CPU time 79.99 seconds
Started Jun 28 05:05:10 PM PDT 24
Finished Jun 28 05:06:30 PM PDT 24
Peak memory 200264 kb
Host smart-d6d86d6e-13d8-46b2-a5b5-5e0f08faa699
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360402034 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_error.2360402034
Directory /workspace/43.hmac_error/latest

Test location /workspace/coverage/default/43.hmac_long_msg.1103311850
Short name T592
Test name
Test status
Simulation time 271073859 ps
CPU time 2.58 seconds
Started Jun 28 05:05:02 PM PDT 24
Finished Jun 28 05:05:06 PM PDT 24
Peak memory 200252 kb
Host smart-00142b51-4907-411c-a6a7-11186b7f067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103311850 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_long_msg.1103311850
Directory /workspace/43.hmac_long_msg/latest

Test location /workspace/coverage/default/43.hmac_smoke.2451468964
Short name T560
Test name
Test status
Simulation time 1058806710 ps
CPU time 7.5 seconds
Started Jun 28 05:05:00 PM PDT 24
Finished Jun 28 05:05:09 PM PDT 24
Peak memory 200236 kb
Host smart-9d0c28db-dceb-4c50-b972-c1cacb0229cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451468964 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_smoke.2451468964
Directory /workspace/43.hmac_smoke/latest

Test location /workspace/coverage/default/43.hmac_test_hmac256_vectors.3963206169
Short name T477
Test name
Test status
Simulation time 5744364269 ps
CPU time 65.16 seconds
Started Jun 28 05:05:12 PM PDT 24
Finished Jun 28 05:06:18 PM PDT 24
Peak memory 200328 kb
Host smart-92af5454-8485-45ae-9711-0acb4ef764b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3963206169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac256_vectors.3963206169
Directory /workspace/43.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_hmac384_vectors.2270572321
Short name T616
Test name
Test status
Simulation time 27643099687 ps
CPU time 94 seconds
Started Jun 28 05:05:12 PM PDT 24
Finished Jun 28 05:06:46 PM PDT 24
Peak memory 200332 kb
Host smart-143ce6d6-7f3c-4877-b940-c21e20c34f96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2270572321 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac384_vectors.2270572321
Directory /workspace/43.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_hmac512_vectors.858951762
Short name T276
Test name
Test status
Simulation time 39237142355 ps
CPU time 100.72 seconds
Started Jun 28 05:05:14 PM PDT 24
Finished Jun 28 05:06:55 PM PDT 24
Peak memory 200324 kb
Host smart-9ed865b1-93e2-4292-b3b4-cb068e9214dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=858951762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_hmac512_vectors.858951762
Directory /workspace/43.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha256_vectors.1718601107
Short name T368
Test name
Test status
Simulation time 116814367611 ps
CPU time 514.6 seconds
Started Jun 28 05:05:15 PM PDT 24
Finished Jun 28 05:13:50 PM PDT 24
Peak memory 200260 kb
Host smart-f2e92c9d-92ee-4273-b893-6204182f030d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1718601107 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha256_vectors.1718601107
Directory /workspace/43.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha384_vectors.207811035
Short name T648
Test name
Test status
Simulation time 422882075065 ps
CPU time 2382.75 seconds
Started Jun 28 05:05:11 PM PDT 24
Finished Jun 28 05:44:55 PM PDT 24
Peak memory 216668 kb
Host smart-1f4a903e-dc16-415c-9318-058b74ed7387
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=207811035 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha384_vectors.207811035
Directory /workspace/43.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/43.hmac_test_sha512_vectors.3428938516
Short name T534
Test name
Test status
Simulation time 29201394667 ps
CPU time 1692.86 seconds
Started Jun 28 05:05:11 PM PDT 24
Finished Jun 28 05:33:25 PM PDT 24
Peak memory 215880 kb
Host smart-8c8de0dd-cb41-429d-838e-87e1910dc013
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3428938516 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_test_sha512_vectors.3428938516
Directory /workspace/43.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/43.hmac_wipe_secret.1219498581
Short name T596
Test name
Test status
Simulation time 9889281875 ps
CPU time 71.74 seconds
Started Jun 28 05:05:18 PM PDT 24
Finished Jun 28 05:06:30 PM PDT 24
Peak memory 200312 kb
Host smart-8f1aa962-8c2f-4311-a435-0ec3e40124b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219498581 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.hmac_wipe_secret.1219498581
Directory /workspace/43.hmac_wipe_secret/latest

Test location /workspace/coverage/default/44.hmac_alert_test.81196482
Short name T775
Test name
Test status
Simulation time 14148751 ps
CPU time 0.6 seconds
Started Jun 28 05:05:12 PM PDT 24
Finished Jun 28 05:05:14 PM PDT 24
Peak memory 196924 kb
Host smart-63d0be0d-781d-4158-bc77-1d94b641fdd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81196482 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_alert_test.81196482
Directory /workspace/44.hmac_alert_test/latest

Test location /workspace/coverage/default/44.hmac_back_pressure.398836191
Short name T59
Test name
Test status
Simulation time 22040374 ps
CPU time 1.29 seconds
Started Jun 28 05:05:14 PM PDT 24
Finished Jun 28 05:05:16 PM PDT 24
Peak memory 200112 kb
Host smart-d6ce3aac-f235-4fdd-a500-899a17394e55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398836191 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_back_pressure.398836191
Directory /workspace/44.hmac_back_pressure/latest

Test location /workspace/coverage/default/44.hmac_burst_wr.828842289
Short name T280
Test name
Test status
Simulation time 512177809 ps
CPU time 10.12 seconds
Started Jun 28 05:05:13 PM PDT 24
Finished Jun 28 05:05:24 PM PDT 24
Peak memory 200216 kb
Host smart-d75c7daf-ac99-405f-8f04-f070507de456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828842289 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_burst_wr.828842289
Directory /workspace/44.hmac_burst_wr/latest

Test location /workspace/coverage/default/44.hmac_datapath_stress.4121806078
Short name T738
Test name
Test status
Simulation time 1607358476 ps
CPU time 396.61 seconds
Started Jun 28 05:05:16 PM PDT 24
Finished Jun 28 05:11:53 PM PDT 24
Peak memory 652008 kb
Host smart-441a4f64-ee7b-4ab5-b558-b015c7127bfe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4121806078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_datapath_stress.4121806078
Directory /workspace/44.hmac_datapath_stress/latest

Test location /workspace/coverage/default/44.hmac_error.3558332109
Short name T643
Test name
Test status
Simulation time 30358883162 ps
CPU time 133.8 seconds
Started Jun 28 05:05:13 PM PDT 24
Finished Jun 28 05:07:28 PM PDT 24
Peak memory 200256 kb
Host smart-cfabe533-457a-44a0-8a42-4b5ff84996fa
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558332109 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_error.3558332109
Directory /workspace/44.hmac_error/latest

Test location /workspace/coverage/default/44.hmac_long_msg.4164526280
Short name T540
Test name
Test status
Simulation time 1691855756 ps
CPU time 54.23 seconds
Started Jun 28 05:05:16 PM PDT 24
Finished Jun 28 05:06:10 PM PDT 24
Peak memory 200328 kb
Host smart-05ed9ec0-ae4d-4b0d-b474-25058e290538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164526280 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_long_msg.4164526280
Directory /workspace/44.hmac_long_msg/latest

Test location /workspace/coverage/default/44.hmac_smoke.1435913031
Short name T306
Test name
Test status
Simulation time 4974753872 ps
CPU time 22.07 seconds
Started Jun 28 05:05:11 PM PDT 24
Finished Jun 28 05:05:34 PM PDT 24
Peak memory 200356 kb
Host smart-5e849e09-69a0-451b-8498-a9cd7e73a534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435913031 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_smoke.1435913031
Directory /workspace/44.hmac_smoke/latest

Test location /workspace/coverage/default/44.hmac_stress_all.1593766152
Short name T413
Test name
Test status
Simulation time 537344720044 ps
CPU time 10639.9 seconds
Started Jun 28 05:05:16 PM PDT 24
Finished Jun 28 08:02:38 PM PDT 24
Peak memory 743900 kb
Host smart-4ba94cb3-46e9-4dc9-99f5-bbcbd984e2df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593766152 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.hmac_stress_all.1593766152
Directory /workspace/44.hmac_stress_all/latest

Test location /workspace/coverage/default/44.hmac_test_hmac256_vectors.3248564144
Short name T608
Test name
Test status
Simulation time 2562259188 ps
CPU time 31.44 seconds
Started Jun 28 05:05:17 PM PDT 24
Finished Jun 28 05:05:49 PM PDT 24
Peak memory 200320 kb
Host smart-11f8a126-64b3-4d69-a59c-5fe976bea345
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3248564144 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac256_vectors.3248564144
Directory /workspace/44.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_hmac384_vectors.3040670696
Short name T785
Test name
Test status
Simulation time 1543411975 ps
CPU time 48.83 seconds
Started Jun 28 05:05:13 PM PDT 24
Finished Jun 28 05:06:02 PM PDT 24
Peak memory 200476 kb
Host smart-e4709569-8b60-4570-b16a-45e708451812
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3040670696 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac384_vectors.3040670696
Directory /workspace/44.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_hmac512_vectors.3647407332
Short name T470
Test name
Test status
Simulation time 19669342415 ps
CPU time 108.14 seconds
Started Jun 28 05:05:14 PM PDT 24
Finished Jun 28 05:07:02 PM PDT 24
Peak memory 200328 kb
Host smart-a0024460-e4f2-4bc6-8d58-a9159faf56ec
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3647407332 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_hmac512_vectors.3647407332
Directory /workspace/44.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha256_vectors.2722284042
Short name T288
Test name
Test status
Simulation time 235626680311 ps
CPU time 472.86 seconds
Started Jun 28 05:05:19 PM PDT 24
Finished Jun 28 05:13:12 PM PDT 24
Peak memory 200252 kb
Host smart-6e6239c5-44dd-4fae-8c29-2c83f75a4f75
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2722284042 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha256_vectors.2722284042
Directory /workspace/44.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha384_vectors.2453619025
Short name T720
Test name
Test status
Simulation time 389041397160 ps
CPU time 1711.32 seconds
Started Jun 28 05:05:11 PM PDT 24
Finished Jun 28 05:33:43 PM PDT 24
Peak memory 215988 kb
Host smart-d9e96d5b-b2b5-4ab9-bfe2-cfa982db6cee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2453619025 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha384_vectors.2453619025
Directory /workspace/44.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/44.hmac_test_sha512_vectors.3845560698
Short name T629
Test name
Test status
Simulation time 739170131746 ps
CPU time 2044.3 seconds
Started Jun 28 05:05:12 PM PDT 24
Finished Jun 28 05:39:18 PM PDT 24
Peak memory 216648 kb
Host smart-2cd6427e-7c9e-443b-aa4c-8845295bdce6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3845560698 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_test_sha512_vectors.3845560698
Directory /workspace/44.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/44.hmac_wipe_secret.1843692220
Short name T207
Test name
Test status
Simulation time 3164036117 ps
CPU time 57.22 seconds
Started Jun 28 05:05:14 PM PDT 24
Finished Jun 28 05:06:12 PM PDT 24
Peak memory 200380 kb
Host smart-06e618f3-f38f-4b5e-937a-6e415ccd1c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843692220 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.hmac_wipe_secret.1843692220
Directory /workspace/44.hmac_wipe_secret/latest

Test location /workspace/coverage/default/45.hmac_alert_test.492219925
Short name T184
Test name
Test status
Simulation time 36054174 ps
CPU time 0.58 seconds
Started Jun 28 05:05:21 PM PDT 24
Finished Jun 28 05:05:23 PM PDT 24
Peak memory 195224 kb
Host smart-f8f318c9-6d3f-4121-8b61-708ede42b015
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492219925 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_alert_test.492219925
Directory /workspace/45.hmac_alert_test/latest

Test location /workspace/coverage/default/45.hmac_back_pressure.4221800530
Short name T108
Test name
Test status
Simulation time 2276413070 ps
CPU time 25.91 seconds
Started Jun 28 05:05:10 PM PDT 24
Finished Jun 28 05:05:36 PM PDT 24
Peak memory 200352 kb
Host smart-df7ce2d4-a876-4bc9-b3ec-114ec45dac52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4221800530 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_back_pressure.4221800530
Directory /workspace/45.hmac_back_pressure/latest

Test location /workspace/coverage/default/45.hmac_burst_wr.454369315
Short name T702
Test name
Test status
Simulation time 9634595495 ps
CPU time 53.5 seconds
Started Jun 28 05:05:15 PM PDT 24
Finished Jun 28 05:06:09 PM PDT 24
Peak memory 200356 kb
Host smart-2d8cdd98-7c18-4dff-82d5-f6b273ae0d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454369315 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_burst_wr.454369315
Directory /workspace/45.hmac_burst_wr/latest

Test location /workspace/coverage/default/45.hmac_datapath_stress.2604445278
Short name T537
Test name
Test status
Simulation time 28031941515 ps
CPU time 875.87 seconds
Started Jun 28 05:05:13 PM PDT 24
Finished Jun 28 05:19:49 PM PDT 24
Peak memory 752364 kb
Host smart-4bcfada0-6c75-4e4d-8129-1283fc5d1aab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2604445278 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_datapath_stress.2604445278
Directory /workspace/45.hmac_datapath_stress/latest

Test location /workspace/coverage/default/45.hmac_error.245377178
Short name T43
Test name
Test status
Simulation time 1951480023 ps
CPU time 107.65 seconds
Started Jun 28 05:05:13 PM PDT 24
Finished Jun 28 05:07:02 PM PDT 24
Peak memory 200260 kb
Host smart-e2bc2c70-12ee-493b-af3b-cfaf4d6babcb
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245377178 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_error.245377178
Directory /workspace/45.hmac_error/latest

Test location /workspace/coverage/default/45.hmac_long_msg.3951643801
Short name T613
Test name
Test status
Simulation time 21134332723 ps
CPU time 108.38 seconds
Started Jun 28 05:05:12 PM PDT 24
Finished Jun 28 05:07:01 PM PDT 24
Peak memory 208760 kb
Host smart-e4f3c1e5-14bc-4e30-a682-dcf13116082d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951643801 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_long_msg.3951643801
Directory /workspace/45.hmac_long_msg/latest

Test location /workspace/coverage/default/45.hmac_smoke.132480371
Short name T177
Test name
Test status
Simulation time 300856509 ps
CPU time 4.14 seconds
Started Jun 28 05:05:14 PM PDT 24
Finished Jun 28 05:05:19 PM PDT 24
Peak memory 200252 kb
Host smart-d5d13a06-45e1-4a24-a7dd-ea91df5e76f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132480371 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_smoke.132480371
Directory /workspace/45.hmac_smoke/latest

Test location /workspace/coverage/default/45.hmac_stress_all.2063089144
Short name T85
Test name
Test status
Simulation time 672016841797 ps
CPU time 2202.07 seconds
Started Jun 28 05:05:21 PM PDT 24
Finished Jun 28 05:42:04 PM PDT 24
Peak memory 216316 kb
Host smart-15544df5-f3e3-44d8-9145-3bb0f4ea69fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063089144 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.hmac_stress_all.2063089144
Directory /workspace/45.hmac_stress_all/latest

Test location /workspace/coverage/default/45.hmac_test_hmac256_vectors.3781133546
Short name T735
Test name
Test status
Simulation time 29643782305 ps
CPU time 71.46 seconds
Started Jun 28 05:05:22 PM PDT 24
Finished Jun 28 05:06:34 PM PDT 24
Peak memory 200500 kb
Host smart-9b079436-fa8a-483c-bb11-72be91d47769
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3781133546 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac256_vectors.3781133546
Directory /workspace/45.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_hmac384_vectors.271305863
Short name T637
Test name
Test status
Simulation time 17110158441 ps
CPU time 39.61 seconds
Started Jun 28 05:05:22 PM PDT 24
Finished Jun 28 05:06:03 PM PDT 24
Peak memory 200000 kb
Host smart-57155a3c-ff37-4517-9b49-b2c57fd9afb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=271305863 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac384_vectors.271305863
Directory /workspace/45.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_hmac512_vectors.2500526905
Short name T431
Test name
Test status
Simulation time 7054551162 ps
CPU time 53.85 seconds
Started Jun 28 05:05:23 PM PDT 24
Finished Jun 28 05:06:17 PM PDT 24
Peak memory 200328 kb
Host smart-d4651fc4-3b59-4b0c-8f57-a9fd9ae4e010
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2500526905 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_hmac512_vectors.2500526905
Directory /workspace/45.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha256_vectors.4265876569
Short name T548
Test name
Test status
Simulation time 43267229268 ps
CPU time 571.55 seconds
Started Jun 28 05:05:13 PM PDT 24
Finished Jun 28 05:14:46 PM PDT 24
Peak memory 200260 kb
Host smart-d423d4a1-6c9a-4da3-938d-cdb6c577ceca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4265876569 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha256_vectors.4265876569
Directory /workspace/45.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha384_vectors.2539682910
Short name T468
Test name
Test status
Simulation time 405773513523 ps
CPU time 2112.14 seconds
Started Jun 28 05:05:15 PM PDT 24
Finished Jun 28 05:40:28 PM PDT 24
Peak memory 216292 kb
Host smart-5a553a62-822e-46da-8568-e0c17fbba2bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2539682910 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha384_vectors.2539682910
Directory /workspace/45.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/45.hmac_test_sha512_vectors.2465332451
Short name T303
Test name
Test status
Simulation time 288671500588 ps
CPU time 1695.39 seconds
Started Jun 28 05:05:13 PM PDT 24
Finished Jun 28 05:33:29 PM PDT 24
Peak memory 216208 kb
Host smart-5b45c78c-a979-43ce-b05d-2ba59124acba
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2465332451 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_test_sha512_vectors.2465332451
Directory /workspace/45.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/45.hmac_wipe_secret.2202856990
Short name T656
Test name
Test status
Simulation time 10255132161 ps
CPU time 53.54 seconds
Started Jun 28 05:05:12 PM PDT 24
Finished Jun 28 05:06:06 PM PDT 24
Peak memory 200312 kb
Host smart-94df2252-8bf9-4478-9f06-c366cbe0f1a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202856990 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.hmac_wipe_secret.2202856990
Directory /workspace/45.hmac_wipe_secret/latest

Test location /workspace/coverage/default/46.hmac_alert_test.3125688762
Short name T221
Test name
Test status
Simulation time 16495136 ps
CPU time 0.59 seconds
Started Jun 28 05:05:22 PM PDT 24
Finished Jun 28 05:05:24 PM PDT 24
Peak memory 195952 kb
Host smart-8de65b14-7f65-4257-bd84-3d3c568a6b92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125688762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_alert_test.3125688762
Directory /workspace/46.hmac_alert_test/latest

Test location /workspace/coverage/default/46.hmac_back_pressure.1785038862
Short name T549
Test name
Test status
Simulation time 148765355 ps
CPU time 6.29 seconds
Started Jun 28 05:05:21 PM PDT 24
Finished Jun 28 05:05:28 PM PDT 24
Peak memory 200112 kb
Host smart-06d1485f-290b-4303-8013-7526dbae8d8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785038862 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_back_pressure.1785038862
Directory /workspace/46.hmac_back_pressure/latest

Test location /workspace/coverage/default/46.hmac_burst_wr.1675126720
Short name T727
Test name
Test status
Simulation time 4174033205 ps
CPU time 63.92 seconds
Started Jun 28 05:05:22 PM PDT 24
Finished Jun 28 05:06:26 PM PDT 24
Peak memory 200328 kb
Host smart-a0f63299-9f6f-4698-ba06-6ae6ef230aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675126720 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_burst_wr.1675126720
Directory /workspace/46.hmac_burst_wr/latest

Test location /workspace/coverage/default/46.hmac_datapath_stress.1030893945
Short name T432
Test name
Test status
Simulation time 8240868857 ps
CPU time 1374.52 seconds
Started Jun 28 05:05:23 PM PDT 24
Finished Jun 28 05:28:18 PM PDT 24
Peak memory 754056 kb
Host smart-3f2232dd-1cef-4f40-91a0-cd12a01fa75c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1030893945 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_datapath_stress.1030893945
Directory /workspace/46.hmac_datapath_stress/latest

Test location /workspace/coverage/default/46.hmac_error.2504638408
Short name T555
Test name
Test status
Simulation time 720057812 ps
CPU time 42.23 seconds
Started Jun 28 05:05:21 PM PDT 24
Finished Jun 28 05:06:04 PM PDT 24
Peak memory 200172 kb
Host smart-41f5c7e4-8d17-44af-9932-bf05282db66f
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504638408 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_error.2504638408
Directory /workspace/46.hmac_error/latest

Test location /workspace/coverage/default/46.hmac_long_msg.3184691656
Short name T291
Test name
Test status
Simulation time 913558694 ps
CPU time 54.93 seconds
Started Jun 28 05:05:23 PM PDT 24
Finished Jun 28 05:06:18 PM PDT 24
Peak memory 200296 kb
Host smart-7834278a-2a18-4474-9b08-aec7d70090f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184691656 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_long_msg.3184691656
Directory /workspace/46.hmac_long_msg/latest

Test location /workspace/coverage/default/46.hmac_smoke.722526104
Short name T36
Test name
Test status
Simulation time 49003425 ps
CPU time 2.38 seconds
Started Jun 28 05:05:23 PM PDT 24
Finished Jun 28 05:05:26 PM PDT 24
Peak memory 200280 kb
Host smart-614d4074-2faf-4c24-8c82-f0d6b3b51495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722526104 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_smoke.722526104
Directory /workspace/46.hmac_smoke/latest

Test location /workspace/coverage/default/46.hmac_stress_all.2714652321
Short name T149
Test name
Test status
Simulation time 409471831904 ps
CPU time 5740 seconds
Started Jun 28 05:05:22 PM PDT 24
Finished Jun 28 06:41:03 PM PDT 24
Peak memory 793792 kb
Host smart-fabdff98-35da-425a-a495-68ff9e621097
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714652321 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.hmac_stress_all.2714652321
Directory /workspace/46.hmac_stress_all/latest

Test location /workspace/coverage/default/46.hmac_test_hmac256_vectors.3942888237
Short name T185
Test name
Test status
Simulation time 26935376604 ps
CPU time 73.71 seconds
Started Jun 28 05:05:21 PM PDT 24
Finished Jun 28 05:06:36 PM PDT 24
Peak memory 200464 kb
Host smart-12df3d7d-dab1-47ad-b364-c8b5afcf6ecf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3942888237 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac256_vectors.3942888237
Directory /workspace/46.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_hmac384_vectors.1600142121
Short name T179
Test name
Test status
Simulation time 1582555448 ps
CPU time 52.2 seconds
Started Jun 28 05:05:21 PM PDT 24
Finished Jun 28 05:06:14 PM PDT 24
Peak memory 200304 kb
Host smart-89465859-2496-4e25-a321-fc1ddba51c34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1600142121 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac384_vectors.1600142121
Directory /workspace/46.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_hmac512_vectors.803696169
Short name T203
Test name
Test status
Simulation time 7928419510 ps
CPU time 53.5 seconds
Started Jun 28 05:05:22 PM PDT 24
Finished Jun 28 05:06:16 PM PDT 24
Peak memory 200324 kb
Host smart-b96a5b34-a7f6-4220-be36-d56332ccbf45
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=803696169 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_hmac512_vectors.803696169
Directory /workspace/46.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha256_vectors.2721918161
Short name T297
Test name
Test status
Simulation time 154377841393 ps
CPU time 488.57 seconds
Started Jun 28 05:05:21 PM PDT 24
Finished Jun 28 05:13:30 PM PDT 24
Peak memory 200256 kb
Host smart-66378d43-2db2-476e-bc23-d136d76a676c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2721918161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha256_vectors.2721918161
Directory /workspace/46.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha384_vectors.805324167
Short name T261
Test name
Test status
Simulation time 224268173912 ps
CPU time 2010.61 seconds
Started Jun 28 05:05:24 PM PDT 24
Finished Jun 28 05:38:55 PM PDT 24
Peak memory 215748 kb
Host smart-10169b96-1d08-4144-a4d7-3e96856113bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=805324167 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha384_vectors.805324167
Directory /workspace/46.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/46.hmac_test_sha512_vectors.2664268404
Short name T514
Test name
Test status
Simulation time 137657266406 ps
CPU time 1906.97 seconds
Started Jun 28 05:05:25 PM PDT 24
Finished Jun 28 05:37:12 PM PDT 24
Peak memory 216608 kb
Host smart-d577a104-64bf-42c6-8548-7964ba4cc92b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2664268404 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_test_sha512_vectors.2664268404
Directory /workspace/46.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/46.hmac_wipe_secret.1034162020
Short name T471
Test name
Test status
Simulation time 4672241246 ps
CPU time 61.62 seconds
Started Jun 28 05:05:23 PM PDT 24
Finished Jun 28 05:06:25 PM PDT 24
Peak memory 200304 kb
Host smart-d3681d39-d394-4e6a-ac1b-adb8057d8f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034162020 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.hmac_wipe_secret.1034162020
Directory /workspace/46.hmac_wipe_secret/latest

Test location /workspace/coverage/default/47.hmac_alert_test.1497063687
Short name T669
Test name
Test status
Simulation time 13136063 ps
CPU time 0.59 seconds
Started Jun 28 05:05:32 PM PDT 24
Finished Jun 28 05:05:33 PM PDT 24
Peak memory 195440 kb
Host smart-3af10d2b-ad9a-4c3f-b251-1a790f9ae23f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497063687 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_alert_test.1497063687
Directory /workspace/47.hmac_alert_test/latest

Test location /workspace/coverage/default/47.hmac_back_pressure.3725258975
Short name T11
Test name
Test status
Simulation time 837332594 ps
CPU time 40.12 seconds
Started Jun 28 05:05:33 PM PDT 24
Finished Jun 28 05:06:14 PM PDT 24
Peak memory 200300 kb
Host smart-e24f9ead-3ce9-4eda-9300-78bd287a9043
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3725258975 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_back_pressure.3725258975
Directory /workspace/47.hmac_back_pressure/latest

Test location /workspace/coverage/default/47.hmac_burst_wr.4152735600
Short name T610
Test name
Test status
Simulation time 655289870 ps
CPU time 12.34 seconds
Started Jun 28 05:05:34 PM PDT 24
Finished Jun 28 05:05:46 PM PDT 24
Peak memory 200328 kb
Host smart-17f1eb28-e03b-4364-8469-ed7cb6f12808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152735600 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_burst_wr.4152735600
Directory /workspace/47.hmac_burst_wr/latest

Test location /workspace/coverage/default/47.hmac_datapath_stress.343698362
Short name T84
Test name
Test status
Simulation time 1825746208 ps
CPU time 382.78 seconds
Started Jun 28 05:05:32 PM PDT 24
Finished Jun 28 05:11:56 PM PDT 24
Peak memory 609048 kb
Host smart-5115944d-82bd-49b5-85f6-0bb2dbbbd0e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=343698362 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_datapath_stress.343698362
Directory /workspace/47.hmac_datapath_stress/latest

Test location /workspace/coverage/default/47.hmac_error.23635199
Short name T611
Test name
Test status
Simulation time 5660415285 ps
CPU time 26.36 seconds
Started Jun 28 05:05:33 PM PDT 24
Finished Jun 28 05:06:00 PM PDT 24
Peak memory 200164 kb
Host smart-d2576a96-71fd-4378-8114-021688e95ae0
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23635199 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_error.23635199
Directory /workspace/47.hmac_error/latest

Test location /workspace/coverage/default/47.hmac_long_msg.3196968775
Short name T415
Test name
Test status
Simulation time 6324597881 ps
CPU time 58.13 seconds
Started Jun 28 05:05:32 PM PDT 24
Finished Jun 28 05:06:31 PM PDT 24
Peak memory 200312 kb
Host smart-305ba962-0ee8-4ccc-83a6-c1b1855776dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196968775 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_long_msg.3196968775
Directory /workspace/47.hmac_long_msg/latest

Test location /workspace/coverage/default/47.hmac_smoke.2483949802
Short name T339
Test name
Test status
Simulation time 208617516 ps
CPU time 5.35 seconds
Started Jun 28 05:05:21 PM PDT 24
Finished Jun 28 05:05:27 PM PDT 24
Peak memory 200316 kb
Host smart-d71a4f55-7614-4889-ab89-f74d7a9e497f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483949802 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_smoke.2483949802
Directory /workspace/47.hmac_smoke/latest

Test location /workspace/coverage/default/47.hmac_stress_all.2242144787
Short name T106
Test name
Test status
Simulation time 322927070040 ps
CPU time 6717.61 seconds
Started Jun 28 05:05:32 PM PDT 24
Finished Jun 28 06:57:31 PM PDT 24
Peak memory 826196 kb
Host smart-31725a7b-aaf7-4a3a-9af2-2257aecf6f69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242144787 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.hmac_stress_all.2242144787
Directory /workspace/47.hmac_stress_all/latest

Test location /workspace/coverage/default/47.hmac_test_hmac256_vectors.2533151200
Short name T178
Test name
Test status
Simulation time 3388136973 ps
CPU time 30.01 seconds
Started Jun 28 05:05:33 PM PDT 24
Finished Jun 28 05:06:04 PM PDT 24
Peak memory 200328 kb
Host smart-9445cd2a-dd34-4674-a403-a97fdeee83e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2533151200 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac256_vectors.2533151200
Directory /workspace/47.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_hmac384_vectors.1936687800
Short name T232
Test name
Test status
Simulation time 10091952698 ps
CPU time 87.88 seconds
Started Jun 28 05:05:31 PM PDT 24
Finished Jun 28 05:07:00 PM PDT 24
Peak memory 200364 kb
Host smart-14199dea-30e1-4c9a-ba9c-64e61121219e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1936687800 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac384_vectors.1936687800
Directory /workspace/47.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_hmac512_vectors.3513418970
Short name T165
Test name
Test status
Simulation time 7572811110 ps
CPU time 116.08 seconds
Started Jun 28 05:05:32 PM PDT 24
Finished Jun 28 05:07:29 PM PDT 24
Peak memory 200260 kb
Host smart-1d30b542-ec00-4de0-80a8-24cb1339bc93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3513418970 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_hmac512_vectors.3513418970
Directory /workspace/47.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha256_vectors.2600937993
Short name T316
Test name
Test status
Simulation time 81231089040 ps
CPU time 536.89 seconds
Started Jun 28 05:05:33 PM PDT 24
Finished Jun 28 05:14:30 PM PDT 24
Peak memory 200260 kb
Host smart-4ca07af7-52ff-41b2-a9a9-708c3ba9c2d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2600937993 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha256_vectors.2600937993
Directory /workspace/47.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha384_vectors.492222770
Short name T225
Test name
Test status
Simulation time 208869620577 ps
CPU time 1889.99 seconds
Started Jun 28 05:05:33 PM PDT 24
Finished Jun 28 05:37:03 PM PDT 24
Peak memory 216200 kb
Host smart-01caa78c-f35e-41a8-80e2-02b6999e6d34
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=492222770 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha384_vectors.492222770
Directory /workspace/47.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/47.hmac_test_sha512_vectors.3014808898
Short name T703
Test name
Test status
Simulation time 575796231988 ps
CPU time 1971.74 seconds
Started Jun 28 05:05:31 PM PDT 24
Finished Jun 28 05:38:24 PM PDT 24
Peak memory 216164 kb
Host smart-b7b85c68-cd15-42ea-a993-c11a89a11de7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3014808898 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_test_sha512_vectors.3014808898
Directory /workspace/47.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/47.hmac_wipe_secret.1949048453
Short name T22
Test name
Test status
Simulation time 3004717216 ps
CPU time 53.99 seconds
Started Jun 28 05:05:33 PM PDT 24
Finished Jun 28 05:06:27 PM PDT 24
Peak memory 200320 kb
Host smart-057ad8a1-9ca5-46e9-b3bc-d54364adea9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949048453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.hmac_wipe_secret.1949048453
Directory /workspace/47.hmac_wipe_secret/latest

Test location /workspace/coverage/default/48.hmac_alert_test.3796815375
Short name T170
Test name
Test status
Simulation time 12820679 ps
CPU time 0.59 seconds
Started Jun 28 05:05:44 PM PDT 24
Finished Jun 28 05:05:46 PM PDT 24
Peak memory 196212 kb
Host smart-24978dc5-6a04-481b-a146-9dde4ff2d1e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796815375 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_alert_test.3796815375
Directory /workspace/48.hmac_alert_test/latest

Test location /workspace/coverage/default/48.hmac_back_pressure.1783149583
Short name T25
Test name
Test status
Simulation time 186367607 ps
CPU time 8.85 seconds
Started Jun 28 05:05:31 PM PDT 24
Finished Jun 28 05:05:41 PM PDT 24
Peak memory 200104 kb
Host smart-c37b4eb9-cabb-4ce4-9b0b-22a83e4ee6de
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1783149583 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_back_pressure.1783149583
Directory /workspace/48.hmac_back_pressure/latest

Test location /workspace/coverage/default/48.hmac_burst_wr.4291672365
Short name T724
Test name
Test status
Simulation time 209742400 ps
CPU time 3.2 seconds
Started Jun 28 05:05:32 PM PDT 24
Finished Jun 28 05:05:36 PM PDT 24
Peak memory 200248 kb
Host smart-5c4fe84e-bd79-461e-a8aa-0a6c20d1c579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291672365 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_burst_wr.4291672365
Directory /workspace/48.hmac_burst_wr/latest

Test location /workspace/coverage/default/48.hmac_datapath_stress.3062818643
Short name T201
Test name
Test status
Simulation time 3214186468 ps
CPU time 815.86 seconds
Started Jun 28 05:05:32 PM PDT 24
Finished Jun 28 05:19:08 PM PDT 24
Peak memory 732540 kb
Host smart-9f330955-6afc-4b34-934d-d109e5aa064a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3062818643 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_datapath_stress.3062818643
Directory /workspace/48.hmac_datapath_stress/latest

Test location /workspace/coverage/default/48.hmac_error.24880746
Short name T139
Test name
Test status
Simulation time 12143231678 ps
CPU time 73.12 seconds
Started Jun 28 05:05:44 PM PDT 24
Finished Jun 28 05:06:58 PM PDT 24
Peak memory 200476 kb
Host smart-3219a178-480e-4baf-ab42-a5b25e2d7fe5
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24880746 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_error.24880746
Directory /workspace/48.hmac_error/latest

Test location /workspace/coverage/default/48.hmac_long_msg.2729427252
Short name T577
Test name
Test status
Simulation time 3242283343 ps
CPU time 47.82 seconds
Started Jun 28 05:05:33 PM PDT 24
Finished Jun 28 05:06:22 PM PDT 24
Peak memory 200380 kb
Host smart-411e040c-d4eb-45fc-9fa8-b3f008eb15c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729427252 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_long_msg.2729427252
Directory /workspace/48.hmac_long_msg/latest

Test location /workspace/coverage/default/48.hmac_smoke.3772994453
Short name T519
Test name
Test status
Simulation time 90005070 ps
CPU time 1.39 seconds
Started Jun 28 05:05:32 PM PDT 24
Finished Jun 28 05:05:34 PM PDT 24
Peak memory 199928 kb
Host smart-11af5bd9-645d-4e9a-9037-197313dd070e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772994453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_smoke.3772994453
Directory /workspace/48.hmac_smoke/latest

Test location /workspace/coverage/default/48.hmac_stress_all.657914413
Short name T88
Test name
Test status
Simulation time 4194804835 ps
CPU time 64.02 seconds
Started Jun 28 05:05:45 PM PDT 24
Finished Jun 28 05:06:50 PM PDT 24
Peak memory 216688 kb
Host smart-95e5fb10-d894-4f26-8228-1210e5b85b4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657914413 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.hmac_stress_all.657914413
Directory /workspace/48.hmac_stress_all/latest

Test location /workspace/coverage/default/48.hmac_test_hmac256_vectors.179395886
Short name T746
Test name
Test status
Simulation time 5713059037 ps
CPU time 64.1 seconds
Started Jun 28 05:05:45 PM PDT 24
Finished Jun 28 05:06:50 PM PDT 24
Peak memory 200296 kb
Host smart-7e375390-7ade-42f8-9dde-f343fa2bbf7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=179395886 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac256_vectors.179395886
Directory /workspace/48.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_hmac384_vectors.591165642
Short name T743
Test name
Test status
Simulation time 2916746527 ps
CPU time 45.05 seconds
Started Jun 28 05:05:44 PM PDT 24
Finished Jun 28 05:06:30 PM PDT 24
Peak memory 200296 kb
Host smart-fcdd9793-50de-460b-a132-6ef7e5d35c5b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=591165642 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac384_vectors.591165642
Directory /workspace/48.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_hmac512_vectors.1913944549
Short name T287
Test name
Test status
Simulation time 10216262279 ps
CPU time 96.72 seconds
Started Jun 28 05:05:44 PM PDT 24
Finished Jun 28 05:07:21 PM PDT 24
Peak memory 200328 kb
Host smart-0d20dceb-5a0f-4eb5-bdd6-5a3a27defd38
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1913944549 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_hmac512_vectors.1913944549
Directory /workspace/48.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha256_vectors.1163953670
Short name T490
Test name
Test status
Simulation time 24105363359 ps
CPU time 444.39 seconds
Started Jun 28 05:05:43 PM PDT 24
Finished Jun 28 05:13:08 PM PDT 24
Peak memory 200396 kb
Host smart-972030a1-68a9-4ccd-8833-8cd7e4a8a5cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1163953670 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha256_vectors.1163953670
Directory /workspace/48.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha384_vectors.1843480217
Short name T494
Test name
Test status
Simulation time 133311824144 ps
CPU time 1842.99 seconds
Started Jun 28 05:05:44 PM PDT 24
Finished Jun 28 05:36:28 PM PDT 24
Peak memory 216324 kb
Host smart-ed61a773-90c3-4db9-a406-2bfe888f98f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1843480217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha384_vectors.1843480217
Directory /workspace/48.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/48.hmac_test_sha512_vectors.109877421
Short name T260
Test name
Test status
Simulation time 32399749701 ps
CPU time 1765.2 seconds
Started Jun 28 05:05:44 PM PDT 24
Finished Jun 28 05:35:10 PM PDT 24
Peak memory 215780 kb
Host smart-afa6a1bb-7b90-437d-bdf5-58e9f8905d31
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=109877421 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_test_sha512_vectors.109877421
Directory /workspace/48.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/48.hmac_wipe_secret.2052405885
Short name T486
Test name
Test status
Simulation time 3706105575 ps
CPU time 35.12 seconds
Started Jun 28 05:05:44 PM PDT 24
Finished Jun 28 05:06:20 PM PDT 24
Peak memory 200192 kb
Host smart-0cba37d8-a1a7-4f88-affa-d1cd24d5eb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052405885 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.hmac_wipe_secret.2052405885
Directory /workspace/48.hmac_wipe_secret/latest

Test location /workspace/coverage/default/49.hmac_alert_test.2752883259
Short name T473
Test name
Test status
Simulation time 28177702 ps
CPU time 0.59 seconds
Started Jun 28 05:05:55 PM PDT 24
Finished Jun 28 05:05:56 PM PDT 24
Peak memory 195980 kb
Host smart-c08a2a27-8cc3-409c-9e3a-245095a00a7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752883259 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_alert_test.2752883259
Directory /workspace/49.hmac_alert_test/latest

Test location /workspace/coverage/default/49.hmac_back_pressure.1139423527
Short name T694
Test name
Test status
Simulation time 4972346288 ps
CPU time 31.43 seconds
Started Jun 28 05:05:44 PM PDT 24
Finished Jun 28 05:06:17 PM PDT 24
Peak memory 216660 kb
Host smart-921baa27-611b-416b-b448-6633c4038027
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1139423527 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_back_pressure.1139423527
Directory /workspace/49.hmac_back_pressure/latest

Test location /workspace/coverage/default/49.hmac_burst_wr.2657240584
Short name T417
Test name
Test status
Simulation time 2211930478 ps
CPU time 70.63 seconds
Started Jun 28 05:05:43 PM PDT 24
Finished Jun 28 05:06:54 PM PDT 24
Peak memory 200372 kb
Host smart-53916b10-c7d7-4551-a44c-00ded0a5f306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657240584 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_burst_wr.2657240584
Directory /workspace/49.hmac_burst_wr/latest

Test location /workspace/coverage/default/49.hmac_datapath_stress.3197701859
Short name T710
Test name
Test status
Simulation time 3472742937 ps
CPU time 214.78 seconds
Started Jun 28 05:05:45 PM PDT 24
Finished Jun 28 05:09:20 PM PDT 24
Peak memory 599412 kb
Host smart-e8bc4731-f038-4c46-9182-10a41df6d18f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3197701859 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_datapath_stress.3197701859
Directory /workspace/49.hmac_datapath_stress/latest

Test location /workspace/coverage/default/49.hmac_error.970104960
Short name T448
Test name
Test status
Simulation time 20678416381 ps
CPU time 72.75 seconds
Started Jun 28 05:05:44 PM PDT 24
Finished Jun 28 05:06:57 PM PDT 24
Peak memory 200324 kb
Host smart-86b2d802-c002-4d92-ba32-5d091d4f050d
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970104960 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_error.970104960
Directory /workspace/49.hmac_error/latest

Test location /workspace/coverage/default/49.hmac_long_msg.3122499148
Short name T569
Test name
Test status
Simulation time 10540965043 ps
CPU time 107.83 seconds
Started Jun 28 05:05:43 PM PDT 24
Finished Jun 28 05:07:31 PM PDT 24
Peak memory 200336 kb
Host smart-5da36e3f-0074-454d-8c5e-f7bb157f7eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122499148 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_long_msg.3122499148
Directory /workspace/49.hmac_long_msg/latest

Test location /workspace/coverage/default/49.hmac_smoke.4208227056
Short name T212
Test name
Test status
Simulation time 455486739 ps
CPU time 7.51 seconds
Started Jun 28 05:05:43 PM PDT 24
Finished Jun 28 05:05:51 PM PDT 24
Peak memory 200280 kb
Host smart-d70b0542-ee3b-4ab8-a33c-4a68f5f35bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208227056 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_smoke.4208227056
Directory /workspace/49.hmac_smoke/latest

Test location /workspace/coverage/default/49.hmac_test_hmac256_vectors.3905874059
Short name T313
Test name
Test status
Simulation time 6154699342 ps
CPU time 63.64 seconds
Started Jun 28 05:05:55 PM PDT 24
Finished Jun 28 05:06:59 PM PDT 24
Peak memory 200268 kb
Host smart-b947ee69-4e52-4014-b46d-4e9bda9dab7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3905874059 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac256_vectors.3905874059
Directory /workspace/49.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_hmac384_vectors.4135731759
Short name T597
Test name
Test status
Simulation time 11272900178 ps
CPU time 93.58 seconds
Started Jun 28 05:05:54 PM PDT 24
Finished Jun 28 05:07:28 PM PDT 24
Peak memory 200236 kb
Host smart-c330bb25-c4b6-4ab7-8418-24d3c64cc0af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4135731759 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac384_vectors.4135731759
Directory /workspace/49.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_hmac512_vectors.1323567102
Short name T82
Test name
Test status
Simulation time 45740433011 ps
CPU time 127.68 seconds
Started Jun 28 05:05:57 PM PDT 24
Finished Jun 28 05:08:05 PM PDT 24
Peak memory 200300 kb
Host smart-057b1539-30d3-46e2-a5fb-3992a4db8cd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1323567102 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_hmac512_vectors.1323567102
Directory /workspace/49.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha256_vectors.2334605374
Short name T681
Test name
Test status
Simulation time 29775489475 ps
CPU time 528.03 seconds
Started Jun 28 05:05:55 PM PDT 24
Finished Jun 28 05:14:43 PM PDT 24
Peak memory 200288 kb
Host smart-8fe946e7-0f36-4bc6-855a-9ba4b8433b05
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2334605374 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha256_vectors.2334605374
Directory /workspace/49.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha384_vectors.2145715345
Short name T301
Test name
Test status
Simulation time 227296083997 ps
CPU time 2087.53 seconds
Started Jun 28 05:05:54 PM PDT 24
Finished Jun 28 05:40:42 PM PDT 24
Peak memory 216220 kb
Host smart-582ef119-224a-4749-84f3-945bcaafce0b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2145715345 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha384_vectors.2145715345
Directory /workspace/49.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/49.hmac_test_sha512_vectors.2319664075
Short name T538
Test name
Test status
Simulation time 313730795256 ps
CPU time 2051.48 seconds
Started Jun 28 05:05:55 PM PDT 24
Finished Jun 28 05:40:07 PM PDT 24
Peak memory 215900 kb
Host smart-46b949a5-976f-4d81-84ca-9f9608732261
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2319664075 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_test_sha512_vectors.2319664075
Directory /workspace/49.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/49.hmac_wipe_secret.3436586453
Short name T367
Test name
Test status
Simulation time 975839740 ps
CPU time 17.59 seconds
Started Jun 28 05:05:44 PM PDT 24
Finished Jun 28 05:06:02 PM PDT 24
Peak memory 200200 kb
Host smart-0e279953-629a-4861-b208-4580fd7e0f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436586453 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.hmac_wipe_secret.3436586453
Directory /workspace/49.hmac_wipe_secret/latest

Test location /workspace/coverage/default/5.hmac_alert_test.661333037
Short name T19
Test name
Test status
Simulation time 14127916 ps
CPU time 0.58 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:00:35 PM PDT 24
Peak memory 195128 kb
Host smart-229e5cec-3e3f-4c91-bc6e-cd99295ecce7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661333037 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_alert_test.661333037
Directory /workspace/5.hmac_alert_test/latest

Test location /workspace/coverage/default/5.hmac_back_pressure.2992805539
Short name T761
Test name
Test status
Simulation time 1705881371 ps
CPU time 40.95 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:00:58 PM PDT 24
Peak memory 200216 kb
Host smart-ff92bb32-f58d-4269-a09f-3dc45dbb21ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2992805539 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_back_pressure.2992805539
Directory /workspace/5.hmac_back_pressure/latest

Test location /workspace/coverage/default/5.hmac_burst_wr.3632654639
Short name T579
Test name
Test status
Simulation time 2950851530 ps
CPU time 39.37 seconds
Started Jun 28 05:00:15 PM PDT 24
Finished Jun 28 05:00:56 PM PDT 24
Peak memory 200284 kb
Host smart-07be41e1-39fe-42ba-80f2-e2d89d1c5bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632654639 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_burst_wr.3632654639
Directory /workspace/5.hmac_burst_wr/latest

Test location /workspace/coverage/default/5.hmac_datapath_stress.1363377266
Short name T699
Test name
Test status
Simulation time 3093899165 ps
CPU time 124.37 seconds
Started Jun 28 05:00:17 PM PDT 24
Finished Jun 28 05:02:22 PM PDT 24
Peak memory 602608 kb
Host smart-1f7ee346-7ff2-405c-acc0-8a51a1a74d7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1363377266 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_datapath_stress.1363377266
Directory /workspace/5.hmac_datapath_stress/latest

Test location /workspace/coverage/default/5.hmac_error.278952161
Short name T56
Test name
Test status
Simulation time 6661157398 ps
CPU time 24.85 seconds
Started Jun 28 05:00:15 PM PDT 24
Finished Jun 28 05:00:40 PM PDT 24
Peak memory 200308 kb
Host smart-17d463d2-07c1-40bd-bb57-d1d9bd213fcc
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278952161 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_error.278952161
Directory /workspace/5.hmac_error/latest

Test location /workspace/coverage/default/5.hmac_long_msg.3824536777
Short name T552
Test name
Test status
Simulation time 763960141 ps
CPU time 42.89 seconds
Started Jun 28 05:00:17 PM PDT 24
Finished Jun 28 05:01:01 PM PDT 24
Peak memory 200220 kb
Host smart-fd75622b-8df5-463f-a91d-6d171262afd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824536777 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_long_msg.3824536777
Directory /workspace/5.hmac_long_msg/latest

Test location /workspace/coverage/default/5.hmac_smoke.853656013
Short name T172
Test name
Test status
Simulation time 238334463 ps
CPU time 3.56 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:00:21 PM PDT 24
Peak memory 200292 kb
Host smart-5cbf1dc9-16f5-423f-99ca-0a8f48d1bdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853656013 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_smoke.853656013
Directory /workspace/5.hmac_smoke/latest

Test location /workspace/coverage/default/5.hmac_stress_all.1618605033
Short name T585
Test name
Test status
Simulation time 56981590855 ps
CPU time 3130.14 seconds
Started Jun 28 05:00:17 PM PDT 24
Finished Jun 28 05:52:29 PM PDT 24
Peak memory 735820 kb
Host smart-d53f054e-5256-4110-8102-4035ee49fd43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618605033 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.hmac_stress_all.1618605033
Directory /workspace/5.hmac_stress_all/latest

Test location /workspace/coverage/default/5.hmac_test_hmac256_vectors.4093293481
Short name T409
Test name
Test status
Simulation time 1425003169 ps
CPU time 56.07 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:01:13 PM PDT 24
Peak memory 200236 kb
Host smart-d2ef66d5-a14b-4c17-9698-ec8cbbd1287f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4093293481 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac256_vectors.4093293481
Directory /workspace/5.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_hmac384_vectors.1741339936
Short name T649
Test name
Test status
Simulation time 5259278398 ps
CPU time 80.81 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:01:37 PM PDT 24
Peak memory 200328 kb
Host smart-df8c0048-90b0-4a5e-854f-e505c994c56c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1741339936 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac384_vectors.1741339936
Directory /workspace/5.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_hmac512_vectors.3929457831
Short name T440
Test name
Test status
Simulation time 17321152161 ps
CPU time 53.95 seconds
Started Jun 28 05:00:15 PM PDT 24
Finished Jun 28 05:01:10 PM PDT 24
Peak memory 200364 kb
Host smart-f6a1b0d8-de6f-4d69-b766-cc9369cfbbb5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3929457831 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_hmac512_vectors.3929457831
Directory /workspace/5.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha256_vectors.4024343082
Short name T208
Test name
Test status
Simulation time 37942874268 ps
CPU time 446.64 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:07:44 PM PDT 24
Peak memory 200164 kb
Host smart-bb220406-4ea0-469c-ae66-3a2e2b9d016a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=4024343082 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha256_vectors.4024343082
Directory /workspace/5.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha384_vectors.1262576994
Short name T442
Test name
Test status
Simulation time 132075079944 ps
CPU time 1853.77 seconds
Started Jun 28 05:00:17 PM PDT 24
Finished Jun 28 05:31:12 PM PDT 24
Peak memory 215664 kb
Host smart-46e37b9d-ecc2-46fc-ae7a-5f497c2ae943
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1262576994 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha384_vectors.1262576994
Directory /workspace/5.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/5.hmac_test_sha512_vectors.3060508347
Short name T752
Test name
Test status
Simulation time 126154332094 ps
CPU time 1817.78 seconds
Started Jun 28 05:00:16 PM PDT 24
Finished Jun 28 05:30:35 PM PDT 24
Peak memory 216652 kb
Host smart-44be9269-a1c3-40d9-9351-5134d7efb35a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3060508347 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_test_sha512_vectors.3060508347
Directory /workspace/5.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/5.hmac_wipe_secret.468152497
Short name T517
Test name
Test status
Simulation time 1544171669 ps
CPU time 34.6 seconds
Started Jun 28 05:00:18 PM PDT 24
Finished Jun 28 05:00:54 PM PDT 24
Peak memory 200272 kb
Host smart-b17919f8-875e-4668-9662-3761b4005468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468152497 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.hmac_wipe_secret.468152497
Directory /workspace/5.hmac_wipe_secret/latest

Test location /workspace/coverage/default/6.hmac_alert_test.1972977869
Short name T351
Test name
Test status
Simulation time 13142087 ps
CPU time 0.62 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:00:35 PM PDT 24
Peak memory 196928 kb
Host smart-15adaf6e-3218-4601-9044-62037f912a75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972977869 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_alert_test.1972977869
Directory /workspace/6.hmac_alert_test/latest

Test location /workspace/coverage/default/6.hmac_back_pressure.2446926215
Short name T530
Test name
Test status
Simulation time 335598365 ps
CPU time 15.61 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:00:48 PM PDT 24
Peak memory 200268 kb
Host smart-606070eb-c00d-4a8b-9eac-cbad045f1cf3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2446926215 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_back_pressure.2446926215
Directory /workspace/6.hmac_back_pressure/latest

Test location /workspace/coverage/default/6.hmac_burst_wr.1865705040
Short name T524
Test name
Test status
Simulation time 900887739 ps
CPU time 48.68 seconds
Started Jun 28 05:00:30 PM PDT 24
Finished Jun 28 05:01:20 PM PDT 24
Peak memory 200264 kb
Host smart-3b595a68-c76f-40ea-ab37-ad290e3449bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865705040 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_burst_wr.1865705040
Directory /workspace/6.hmac_burst_wr/latest

Test location /workspace/coverage/default/6.hmac_datapath_stress.3067564308
Short name T401
Test name
Test status
Simulation time 9588292841 ps
CPU time 447.49 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:08:03 PM PDT 24
Peak memory 678432 kb
Host smart-b1dd48ad-b51f-4182-978e-ec4c344d5efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3067564308 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_datapath_stress.3067564308
Directory /workspace/6.hmac_datapath_stress/latest

Test location /workspace/coverage/default/6.hmac_error.605061517
Short name T575
Test name
Test status
Simulation time 2203371373 ps
CPU time 24.12 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:00:57 PM PDT 24
Peak memory 200224 kb
Host smart-6cfc5c63-dde0-4544-8ce3-8e3f0a9a0fc6
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605061517 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_error.605061517
Directory /workspace/6.hmac_error/latest

Test location /workspace/coverage/default/6.hmac_long_msg.3264153901
Short name T283
Test name
Test status
Simulation time 28186723354 ps
CPU time 109.82 seconds
Started Jun 28 05:00:35 PM PDT 24
Finished Jun 28 05:02:26 PM PDT 24
Peak memory 200316 kb
Host smart-5d89b448-b48f-4115-b2cd-188fdb7a0dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264153901 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_long_msg.3264153901
Directory /workspace/6.hmac_long_msg/latest

Test location /workspace/coverage/default/6.hmac_smoke.174745038
Short name T774
Test name
Test status
Simulation time 1228071029 ps
CPU time 2.5 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:00:35 PM PDT 24
Peak memory 200316 kb
Host smart-1c6b4cb3-4c3a-4e89-9706-c623ee6644b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174745038 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_smoke.174745038
Directory /workspace/6.hmac_smoke/latest

Test location /workspace/coverage/default/6.hmac_stress_all.2625967841
Short name T574
Test name
Test status
Simulation time 36229083802 ps
CPU time 1565.03 seconds
Started Jun 28 05:00:34 PM PDT 24
Finished Jun 28 05:26:41 PM PDT 24
Peak memory 752008 kb
Host smart-648ca18e-821f-433d-81e3-3280eeb1d3e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625967841 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.hmac_stress_all.2625967841
Directory /workspace/6.hmac_stress_all/latest

Test location /workspace/coverage/default/6.hmac_test_hmac256_vectors.3028306241
Short name T512
Test name
Test status
Simulation time 3521305108 ps
CPU time 30.45 seconds
Started Jun 28 05:00:30 PM PDT 24
Finished Jun 28 05:01:02 PM PDT 24
Peak memory 200360 kb
Host smart-b1630465-323f-4fbb-8611-ade604f3fa2e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3028306241 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac256_vectors.3028306241
Directory /workspace/6.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_hmac384_vectors.1265749386
Short name T436
Test name
Test status
Simulation time 2000962099 ps
CPU time 76.51 seconds
Started Jun 28 05:00:32 PM PDT 24
Finished Jun 28 05:01:51 PM PDT 24
Peak memory 200300 kb
Host smart-ed1cf280-9467-4ce2-abd1-34bc3ea25f7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1265749386 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac384_vectors.1265749386
Directory /workspace/6.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_hmac512_vectors.1776081543
Short name T359
Test name
Test status
Simulation time 3142534240 ps
CPU time 102.68 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:02:15 PM PDT 24
Peak memory 200268 kb
Host smart-9a81098f-fda1-440a-a4ae-1b1e6c607a2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1776081543 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_hmac512_vectors.1776081543
Directory /workspace/6.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha256_vectors.2021309694
Short name T590
Test name
Test status
Simulation time 39320762843 ps
CPU time 513.55 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:09:08 PM PDT 24
Peak memory 200256 kb
Host smart-d0eda46f-7b1c-434d-9916-d721b1739e9e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=2021309694 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha256_vectors.2021309694
Directory /workspace/6.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha384_vectors.3853322069
Short name T336
Test name
Test status
Simulation time 31639239099 ps
CPU time 1792.2 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:30:27 PM PDT 24
Peak memory 216280 kb
Host smart-83153dba-72dd-4523-b641-5ccc4c66c8e3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3853322069 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha384_vectors.3853322069
Directory /workspace/6.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/6.hmac_test_sha512_vectors.2673234262
Short name T713
Test name
Test status
Simulation time 58966655098 ps
CPU time 1697.37 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:28:52 PM PDT 24
Peak memory 216548 kb
Host smart-e0f08e67-ff66-4f8b-b835-5660699e624d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2673234262 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_test_sha512_vectors.2673234262
Directory /workspace/6.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/6.hmac_wipe_secret.774960195
Short name T329
Test name
Test status
Simulation time 16264185940 ps
CPU time 54.55 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:01:27 PM PDT 24
Peak memory 200544 kb
Host smart-4ea1507d-8135-4940-a9f5-55d487c4d86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774960195 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.hmac_wipe_secret.774960195
Directory /workspace/6.hmac_wipe_secret/latest

Test location /workspace/coverage/default/7.hmac_alert_test.2517833233
Short name T748
Test name
Test status
Simulation time 14138264 ps
CPU time 0.59 seconds
Started Jun 28 05:00:30 PM PDT 24
Finished Jun 28 05:00:31 PM PDT 24
Peak memory 196016 kb
Host smart-6506f0dd-82a4-426b-a1e0-2f0deeb0ffb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517833233 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_alert_test.2517833233
Directory /workspace/7.hmac_alert_test/latest

Test location /workspace/coverage/default/7.hmac_back_pressure.1966486078
Short name T109
Test name
Test status
Simulation time 752413980 ps
CPU time 36.13 seconds
Started Jun 28 05:00:34 PM PDT 24
Finished Jun 28 05:01:12 PM PDT 24
Peak memory 199464 kb
Host smart-b066ac6e-053a-496e-9b7c-cc8bb9ecced4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1966486078 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_back_pressure.1966486078
Directory /workspace/7.hmac_back_pressure/latest

Test location /workspace/coverage/default/7.hmac_burst_wr.2394839243
Short name T763
Test name
Test status
Simulation time 22147102986 ps
CPU time 33.45 seconds
Started Jun 28 05:00:30 PM PDT 24
Finished Jun 28 05:01:04 PM PDT 24
Peak memory 200376 kb
Host smart-8b9b2ea4-4a13-43f3-935f-07c511070d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394839243 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_burst_wr.2394839243
Directory /workspace/7.hmac_burst_wr/latest

Test location /workspace/coverage/default/7.hmac_datapath_stress.3772766798
Short name T504
Test name
Test status
Simulation time 541266846 ps
CPU time 165.22 seconds
Started Jun 28 05:00:30 PM PDT 24
Finished Jun 28 05:03:17 PM PDT 24
Peak memory 454436 kb
Host smart-fe382334-8695-43f2-832d-257801bf670a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772766798 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_datapath_stress.3772766798
Directory /workspace/7.hmac_datapath_stress/latest

Test location /workspace/coverage/default/7.hmac_error.2756622560
Short name T299
Test name
Test status
Simulation time 4845297522 ps
CPU time 132.76 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:02:48 PM PDT 24
Peak memory 200284 kb
Host smart-d82f92fa-3631-4d90-b935-1631db3bfc91
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756622560 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_error.2756622560
Directory /workspace/7.hmac_error/latest

Test location /workspace/coverage/default/7.hmac_long_msg.2563693437
Short name T630
Test name
Test status
Simulation time 1207331798 ps
CPU time 38.24 seconds
Started Jun 28 05:00:34 PM PDT 24
Finished Jun 28 05:01:14 PM PDT 24
Peak memory 200280 kb
Host smart-c1542b5c-e81b-4a2b-a44e-7bd747d0f5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563693437 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_long_msg.2563693437
Directory /workspace/7.hmac_long_msg/latest

Test location /workspace/coverage/default/7.hmac_smoke.3642791036
Short name T391
Test name
Test status
Simulation time 74297474 ps
CPU time 3.56 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:00:37 PM PDT 24
Peak memory 200232 kb
Host smart-5b0c2bb7-f5f0-4400-b53a-0959fb4d3dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642791036 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_smoke.3642791036
Directory /workspace/7.hmac_smoke/latest

Test location /workspace/coverage/default/7.hmac_stress_all.1836346315
Short name T784
Test name
Test status
Simulation time 10054115653 ps
CPU time 262.48 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:04:55 PM PDT 24
Peak memory 216856 kb
Host smart-b9c5ed06-7025-485a-91e6-ed69c51cab01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836346315 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.hmac_stress_all.1836346315
Directory /workspace/7.hmac_stress_all/latest

Test location /workspace/coverage/default/7.hmac_test_hmac256_vectors.2629818499
Short name T768
Test name
Test status
Simulation time 5460552830 ps
CPU time 53.84 seconds
Started Jun 28 05:00:32 PM PDT 24
Finished Jun 28 05:01:28 PM PDT 24
Peak memory 200328 kb
Host smart-27ed48a5-0cf9-422b-99d3-496d10b09822
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2629818499 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac256_vectors.2629818499
Directory /workspace/7.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_hmac384_vectors.3774925388
Short name T526
Test name
Test status
Simulation time 13822813244 ps
CPU time 54.06 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:01:29 PM PDT 24
Peak memory 200300 kb
Host smart-3ff913cd-cbdf-455a-b6a0-cf755e24f3d0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3774925388 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac384_vectors.3774925388
Directory /workspace/7.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_hmac512_vectors.102745693
Short name T342
Test name
Test status
Simulation time 10230091365 ps
CPU time 98.52 seconds
Started Jun 28 05:00:30 PM PDT 24
Finished Jun 28 05:02:09 PM PDT 24
Peak memory 200260 kb
Host smart-0dcbbb5e-889f-407c-bebd-d90291788cc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=102745693 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_hmac512_vectors.102745693
Directory /workspace/7.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha256_vectors.118642044
Short name T162
Test name
Test status
Simulation time 39868895300 ps
CPU time 501.61 seconds
Started Jun 28 05:00:32 PM PDT 24
Finished Jun 28 05:08:55 PM PDT 24
Peak memory 200256 kb
Host smart-908fc38b-115d-4f48-98c7-f1fe571cd74e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=118642044 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha256_vectors.118642044
Directory /workspace/7.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha384_vectors.1759567598
Short name T378
Test name
Test status
Simulation time 39855925090 ps
CPU time 1788.89 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:30:24 PM PDT 24
Peak memory 216676 kb
Host smart-bf005f47-6200-480d-b515-f712d4b1a295
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1759567598 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha384_vectors.1759567598
Directory /workspace/7.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/7.hmac_test_sha512_vectors.4051702649
Short name T187
Test name
Test status
Simulation time 650491977602 ps
CPU time 2000.36 seconds
Started Jun 28 05:00:34 PM PDT 24
Finished Jun 28 05:33:56 PM PDT 24
Peak memory 216376 kb
Host smart-6dbdd11c-6a08-407f-b998-a04a77603628
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4051702649 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_test_sha512_vectors.4051702649
Directory /workspace/7.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/7.hmac_wipe_secret.2478879135
Short name T460
Test name
Test status
Simulation time 9032584140 ps
CPU time 47.82 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:01:21 PM PDT 24
Peak memory 200336 kb
Host smart-2123aa71-1146-4e68-bf80-7164217220b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478879135 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.hmac_wipe_secret.2478879135
Directory /workspace/7.hmac_wipe_secret/latest

Test location /workspace/coverage/default/8.hmac_alert_test.2852732973
Short name T666
Test name
Test status
Simulation time 28657481 ps
CPU time 0.6 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:00:33 PM PDT 24
Peak memory 196988 kb
Host smart-8d509f7c-2661-4e05-a4f2-93d9195b915e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852732973 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_alert_test.2852732973
Directory /workspace/8.hmac_alert_test/latest

Test location /workspace/coverage/default/8.hmac_back_pressure.28988688
Short name T638
Test name
Test status
Simulation time 679690362 ps
CPU time 34.21 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:01:07 PM PDT 24
Peak memory 200264 kb
Host smart-4a0d7aa1-be29-44da-8a2b-798d4230b20d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=28988688 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_back_pressure.28988688
Directory /workspace/8.hmac_back_pressure/latest

Test location /workspace/coverage/default/8.hmac_burst_wr.2527396115
Short name T450
Test name
Test status
Simulation time 728560643 ps
CPU time 4.06 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:00:36 PM PDT 24
Peak memory 200148 kb
Host smart-e3ca81bd-07fb-4849-9987-806b4fc7a977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527396115 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_burst_wr.2527396115
Directory /workspace/8.hmac_burst_wr/latest

Test location /workspace/coverage/default/8.hmac_datapath_stress.2942247728
Short name T599
Test name
Test status
Simulation time 15905744726 ps
CPU time 1088.33 seconds
Started Jun 28 05:00:32 PM PDT 24
Finished Jun 28 05:18:42 PM PDT 24
Peak memory 731992 kb
Host smart-8f64d862-4b6d-4803-9c0c-376f9f987ad5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2942247728 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_datapath_stress.2942247728
Directory /workspace/8.hmac_datapath_stress/latest

Test location /workspace/coverage/default/8.hmac_error.1363253784
Short name T245
Test name
Test status
Simulation time 39751051804 ps
CPU time 179.51 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:03:32 PM PDT 24
Peak memory 200332 kb
Host smart-3e61c84d-c900-44f8-a2c2-c8315341a420
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363253784 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_error.1363253784
Directory /workspace/8.hmac_error/latest

Test location /workspace/coverage/default/8.hmac_long_msg.1881401825
Short name T553
Test name
Test status
Simulation time 302105856 ps
CPU time 18.73 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:00:52 PM PDT 24
Peak memory 200252 kb
Host smart-145b7cf7-4c02-4e21-aba1-41b83b774bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881401825 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_long_msg.1881401825
Directory /workspace/8.hmac_long_msg/latest

Test location /workspace/coverage/default/8.hmac_smoke.4144792977
Short name T405
Test name
Test status
Simulation time 642960846 ps
CPU time 9.49 seconds
Started Jun 28 05:00:32 PM PDT 24
Finished Jun 28 05:00:43 PM PDT 24
Peak memory 200280 kb
Host smart-57124139-fec6-4589-ba2f-746ab9525476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144792977 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_smoke.4144792977
Directory /workspace/8.hmac_smoke/latest

Test location /workspace/coverage/default/8.hmac_stress_all.1654250180
Short name T527
Test name
Test status
Simulation time 33547188993 ps
CPU time 551.64 seconds
Started Jun 28 05:00:32 PM PDT 24
Finished Jun 28 05:09:46 PM PDT 24
Peak memory 216716 kb
Host smart-eff3c6c9-3132-4aaf-9405-7abcbbc5426f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654250180 -assert nopos
tproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.hmac_stress_all.1654250180
Directory /workspace/8.hmac_stress_all/latest

Test location /workspace/coverage/default/8.hmac_test_hmac256_vectors.3676795986
Short name T340
Test name
Test status
Simulation time 6419726273 ps
CPU time 57.18 seconds
Started Jun 28 05:00:32 PM PDT 24
Finished Jun 28 05:01:31 PM PDT 24
Peak memory 200328 kb
Host smart-f8782d0b-a212-4913-91b2-2f0f7d317ff4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3676795986 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac256_vectors.3676795986
Directory /workspace/8.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_hmac384_vectors.1245553334
Short name T453
Test name
Test status
Simulation time 29430855593 ps
CPU time 85.65 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:02:00 PM PDT 24
Peak memory 200288 kb
Host smart-d6434499-def1-4cb9-aaf5-a3a9ff7b4ec6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1245553334 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac384_vectors.1245553334
Directory /workspace/8.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_hmac512_vectors.2550659762
Short name T198
Test name
Test status
Simulation time 77276145634 ps
CPU time 62.08 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:01:37 PM PDT 24
Peak memory 200380 kb
Host smart-b059e722-ad16-42b2-a203-0e1f67a16124
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2550659762 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_hmac512_vectors.2550659762
Directory /workspace/8.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha256_vectors.1035280635
Short name T256
Test name
Test status
Simulation time 73660823634 ps
CPU time 491.41 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:08:46 PM PDT 24
Peak memory 200256 kb
Host smart-28262f6a-f10f-476f-9b74-faadd62a2e09
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=1035280635 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha256_vectors.1035280635
Directory /workspace/8.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha384_vectors.2217884680
Short name T509
Test name
Test status
Simulation time 177947738983 ps
CPU time 2150.69 seconds
Started Jun 28 05:00:29 PM PDT 24
Finished Jun 28 05:36:20 PM PDT 24
Peak memory 216168 kb
Host smart-9b736c5e-ffc2-470b-b006-b430016c1b01
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2217884680 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha384_vectors.2217884680
Directory /workspace/8.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/8.hmac_test_sha512_vectors.4253154320
Short name T211
Test name
Test status
Simulation time 383722440445 ps
CPU time 1840.32 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:31:13 PM PDT 24
Peak memory 215804 kb
Host smart-3e6df758-2f43-4ee9-85da-79690b6f2951
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4253154320 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_test_sha512_vectors.4253154320
Directory /workspace/8.hmac_test_sha512_vectors/latest

Test location /workspace/coverage/default/8.hmac_wipe_secret.1773994217
Short name T427
Test name
Test status
Simulation time 1791409815 ps
CPU time 34.43 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:01:09 PM PDT 24
Peak memory 200268 kb
Host smart-a8426140-6995-4967-acac-23127b0dc37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773994217 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.hmac_wipe_secret.1773994217
Directory /workspace/8.hmac_wipe_secret/latest

Test location /workspace/coverage/default/9.hmac_alert_test.2577649311
Short name T160
Test name
Test status
Simulation time 13830947 ps
CPU time 0.57 seconds
Started Jun 28 05:00:47 PM PDT 24
Finished Jun 28 05:00:49 PM PDT 24
Peak memory 195196 kb
Host smart-2f96cada-fc30-4aa3-bed8-3a4c5bee3189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577649311 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_alert_test.2577649311
Directory /workspace/9.hmac_alert_test/latest

Test location /workspace/coverage/default/9.hmac_back_pressure.1887808601
Short name T372
Test name
Test status
Simulation time 656305001 ps
CPU time 7.95 seconds
Started Jun 28 05:00:33 PM PDT 24
Finished Jun 28 05:00:43 PM PDT 24
Peak memory 200204 kb
Host smart-6c83339d-f66a-454f-8efe-f97307c2c2a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1887808601 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_back_pressure.1887808601
Directory /workspace/9.hmac_back_pressure/latest

Test location /workspace/coverage/default/9.hmac_burst_wr.1146178208
Short name T315
Test name
Test status
Simulation time 1408646837 ps
CPU time 21.39 seconds
Started Jun 28 05:00:32 PM PDT 24
Finished Jun 28 05:00:55 PM PDT 24
Peak memory 200188 kb
Host smart-301d6a47-c010-4068-abb5-7daac791e8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146178208 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_burst_wr.1146178208
Directory /workspace/9.hmac_burst_wr/latest

Test location /workspace/coverage/default/9.hmac_datapath_stress.3174675783
Short name T712
Test name
Test status
Simulation time 1450230942 ps
CPU time 126.37 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:02:40 PM PDT 24
Peak memory 389112 kb
Host smart-f419e69b-762a-459f-8fe9-dc4be91a321f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3174675783 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_datapath_stress.3174675783
Directory /workspace/9.hmac_datapath_stress/latest

Test location /workspace/coverage/default/9.hmac_error.2731552181
Short name T634
Test name
Test status
Simulation time 7045978130 ps
CPU time 121.5 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:02:34 PM PDT 24
Peak memory 200236 kb
Host smart-e9511571-beaf-4f33-93cd-204e70bfbd78
User root
Command /workspace/default/simv +test_timeout_ns=300_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731552181 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_error.2731552181
Directory /workspace/9.hmac_error/latest

Test location /workspace/coverage/default/9.hmac_long_msg.582762189
Short name T704
Test name
Test status
Simulation time 203535308 ps
CPU time 11.96 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:00:44 PM PDT 24
Peak memory 200188 kb
Host smart-f8da6318-78db-41ac-9a4e-1fc5348c8b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582762189 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_long_msg.582762189
Directory /workspace/9.hmac_long_msg/latest

Test location /workspace/coverage/default/9.hmac_smoke.3079023474
Short name T289
Test name
Test status
Simulation time 2344772284 ps
CPU time 15.52 seconds
Started Jun 28 05:00:30 PM PDT 24
Finished Jun 28 05:00:46 PM PDT 24
Peak memory 200312 kb
Host smart-b3427990-35f6-4f79-bee9-a596b423a107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079023474 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_smoke.3079023474
Directory /workspace/9.hmac_smoke/latest

Test location /workspace/coverage/default/9.hmac_stress_all.126512252
Short name T105
Test name
Test status
Simulation time 3458111897 ps
CPU time 49.75 seconds
Started Jun 28 05:00:45 PM PDT 24
Finished Jun 28 05:01:35 PM PDT 24
Peak memory 200332 kb
Host smart-fb6b51b3-ee54-4c43-946c-6e07cb9b3289
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126512252 -assert nopost
proc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.hmac_stress_all.126512252
Directory /workspace/9.hmac_stress_all/latest

Test location /workspace/coverage/default/9.hmac_test_hmac256_vectors.4010234981
Short name T104
Test name
Test status
Simulation time 13643470993 ps
CPU time 59.9 seconds
Started Jun 28 05:00:49 PM PDT 24
Finished Jun 28 05:01:49 PM PDT 24
Peak memory 200168 kb
Host smart-55ab15e4-20a8-4aa4-a004-19c46203fba6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_256 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4010234981 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac256_vectors.4010234981
Directory /workspace/9.hmac_test_hmac256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_hmac384_vectors.2273640576
Short name T247
Test name
Test status
Simulation time 9039532776 ps
CPU time 82.85 seconds
Started Jun 28 05:00:44 PM PDT 24
Finished Jun 28 05:02:08 PM PDT 24
Peak memory 200256 kb
Host smart-2a80b972-f0bb-4f21-9288-b61882e245b4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2273640576 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac384_vectors.2273640576
Directory /workspace/9.hmac_test_hmac384_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_hmac512_vectors.3596709718
Short name T469
Test name
Test status
Simulation time 2666112262 ps
CPU time 95.9 seconds
Started Jun 28 05:00:53 PM PDT 24
Finished Jun 28 05:02:29 PM PDT 24
Peak memory 200044 kb
Host smart-12b82226-c955-4ec2-8af6-a27ac5437d69
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=2_000_000_000 +sha2_digest_size=SHA2_512 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3596709718 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_hmac512_vectors.3596709718
Directory /workspace/9.hmac_test_hmac512_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha256_vectors.421967092
Short name T412
Test name
Test status
Simulation time 7897021719 ps
CPU time 435.84 seconds
Started Jun 28 05:00:46 PM PDT 24
Finished Jun 28 05:08:03 PM PDT 24
Peak memory 200260 kb
Host smart-1da6ab57-02a1-40e8-9207-c36e1eb227e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=800_000_000 +sha2_digest_size=SHA2_256 +cd
c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se
ed=421967092 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha256_vectors.421967092
Directory /workspace/9.hmac_test_sha256_vectors/latest

Test location /workspace/coverage/default/9.hmac_test_sha384_vectors.4087359274
Short name T317
Test name
Test status
Simulation time 61966733882 ps
CPU time 1737.82 seconds
Started Jun 28 05:00:48 PM PDT 24
Finished Jun 28 05:29:47 PM PDT 24
Peak memory 215692 kb
Host smart-a6a4d097-f378-4bb2-a278-de54fae3608d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1_000_000_000 +sha2_digest_size=SHA2_384 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4087359274 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_test_sha384_vectors.4087359274
Directory /workspace/9.hmac_test_sha384_vectors/latest

Test location /workspace/coverage/default/9.hmac_wipe_secret.1696121179
Short name T667
Test name
Test status
Simulation time 2955597642 ps
CPU time 62.69 seconds
Started Jun 28 05:00:31 PM PDT 24
Finished Jun 28 05:01:35 PM PDT 24
Peak memory 200376 kb
Host smart-1807605d-66ef-401f-964d-01f6dc01f6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696121179 -assert nopostproc +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.hmac_wipe_secret.1696121179
Directory /workspace/9.hmac_wipe_secret/latest
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