Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 129568853 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 136249217 1 T1 3738 T2 3380 T3 750967



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 107331403 1 T1 3201 T2 3003 T3 594511
values[0x0] 74650409 1 T1 1621 T2 1947 T3 415756
values[0x1] 83836258 1 T1 1886 T2 2414 T3 463993



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 97137985 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 168680085 1 T1 4529 T2 4456 T3 930404



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 783837 1 T1 22 T3 5791 T4 24
valid_sources[0x01] 785077 1 T1 30 T3 5758 T4 27
valid_sources[0x02] 846612 1 T1 24 T3 5908 T4 30
valid_sources[0x03] 864506 1 T1 23 T3 5872 T4 15
valid_sources[0x04] 1145506 1 T1 11 T3 5846 T4 19
valid_sources[0x05] 778074 1 T1 20 T3 5766 T4 17
valid_sources[0x06] 790935 1 T1 23 T3 5685 T4 21
valid_sources[0x07] 785288 1 T1 17 T3 5764 T4 27
valid_sources[0x08] 784266 1 T1 35 T3 5716 T4 28
valid_sources[0x09] 824099 1 T1 26 T3 5712 T4 15
valid_sources[0x0a] 784260 1 T1 25 T3 5927 T4 28
valid_sources[0x0b] 802973 1 T1 14 T3 5737 T4 33
valid_sources[0x0c] 788130 1 T1 30 T3 5739 T4 22
valid_sources[0x0d] 2554250 1 T1 34 T3 5699 T4 27
valid_sources[0x0e] 829391 1 T1 25 T3 5884 T4 19
valid_sources[0x0f] 2422291 1 T1 32 T3 5735 T4 19
valid_sources[0x10] 810465 1 T1 36 T3 5710 T4 30
valid_sources[0x11] 823198 1 T1 27 T3 5720 T4 26
valid_sources[0x12] 828095 1 T1 24 T3 5717 T4 35
valid_sources[0x13] 789864 1 T1 33 T2 1 T3 5680
valid_sources[0x14] 788496 1 T1 18 T3 5688 T4 27
valid_sources[0x15] 813985 1 T1 27 T3 5756 T4 38
valid_sources[0x16] 2377661 1 T1 22 T3 5911 T4 25
valid_sources[0x17] 923975 1 T1 25 T3 5746 T4 23
valid_sources[0x18] 786503 1 T1 19 T3 5816 T4 32
valid_sources[0x19] 788189 1 T1 21 T3 5755 T4 21
valid_sources[0x1a] 785261 1 T1 27 T3 5606 T4 29
valid_sources[0x1b] 810908 1 T1 19 T3 5705 T4 17
valid_sources[0x1c] 787987 1 T1 35 T3 5771 T4 18
valid_sources[0x1d] 787222 1 T1 37 T3 5702 T4 33
valid_sources[0x1e] 1168189 1 T1 19 T3 5651 T4 32
valid_sources[0x1f] 785619 1 T1 37 T3 5780 T4 20
valid_sources[0x20] 818375 1 T1 30 T3 5560 T4 26
valid_sources[0x21] 2335333 1 T1 18 T3 5774 T4 26
valid_sources[0x22] 790210 1 T1 24 T3 5693 T4 24
valid_sources[0x23] 4648779 1 T1 30 T3 5806 T4 29
valid_sources[0x24] 786746 1 T1 37 T3 5833 T4 21
valid_sources[0x25] 786064 1 T1 21 T3 5631 T4 13
valid_sources[0x26] 824506 1 T1 21 T3 5812 T4 15
valid_sources[0x27] 785188 1 T1 23 T3 5696 T4 33
valid_sources[0x28] 785969 1 T1 26 T3 5740 T4 14
valid_sources[0x29] 781853 1 T1 39 T3 5839 T4 30
valid_sources[0x2a] 784030 1 T1 27 T3 5834 T4 24
valid_sources[0x2b] 788357 1 T1 19 T3 5750 T4 22
valid_sources[0x2c] 866409 1 T1 31 T3 5649 T4 28
valid_sources[0x2d] 812080 1 T1 27 T3 5781 T4 40
valid_sources[0x2e] 781447 1 T1 23 T3 5849 T4 33
valid_sources[0x2f] 797952 1 T1 26 T3 5704 T4 23
valid_sources[0x30] 788180 1 T1 26 T3 5936 T4 24
valid_sources[0x31] 1031479 1 T1 21 T3 5785 T4 32
valid_sources[0x32] 829353 1 T1 18 T3 5735 T4 32
valid_sources[0x33] 1405132 1 T1 33 T3 5881 T4 20
valid_sources[0x34] 783291 1 T1 23 T3 5697 T4 23
valid_sources[0x35] 788593 1 T1 22 T3 5781 T4 24
valid_sources[0x36] 853044 1 T1 17 T3 5751 T4 28
valid_sources[0x37] 805239 1 T1 23 T3 5681 T4 24
valid_sources[0x38] 786292 1 T1 24 T3 5661 T4 8
valid_sources[0x39] 785707 1 T1 20 T3 5630 T4 20
valid_sources[0x3a] 869794 1 T1 28 T3 5609 T4 30
valid_sources[0x3b] 942604 1 T1 21 T3 5675 T4 18
valid_sources[0x3c] 871594 1 T1 25 T3 5949 T4 31
valid_sources[0x3d] 787869 1 T1 24 T3 5828 T4 21
valid_sources[0x3e] 789190 1 T1 22 T3 5764 T4 25
valid_sources[0x3f] 855053 1 T1 32 T3 5845 T4 38
valid_sources[0x40] 786085 1 T1 37 T3 5758 T4 20
valid_sources[0x41] 801152 1 T1 26 T3 5863 T4 24
valid_sources[0x42] 1541290 1 T1 21 T3 5791 T4 27
valid_sources[0x43] 914037 1 T1 18 T3 5869 T4 25
valid_sources[0x44] 857900 1 T1 26 T3 5827 T4 22
valid_sources[0x45] 790727 1 T1 47 T3 5772 T4 15
valid_sources[0x46] 790023 1 T1 26 T3 5788 T4 24
valid_sources[0x47] 1185720 1 T1 23 T3 5817 T4 28
valid_sources[0x48] 786505 1 T1 19 T3 5802 T4 17
valid_sources[0x49] 815415 1 T1 18 T3 5580 T4 16
valid_sources[0x4a] 1165545 1 T1 23 T3 5722 T4 33
valid_sources[0x4b] 839832 1 T1 20 T3 5594 T4 16
valid_sources[0x4c] 785696 1 T1 18 T3 5787 T4 23
valid_sources[0x4d] 782864 1 T1 25 T3 5791 T4 23
valid_sources[0x4e] 2721621 1 T1 32 T3 5892 T4 21
valid_sources[0x4f] 2517463 1 T1 25 T3 5732 T4 12
valid_sources[0x50] 872651 1 T1 21 T3 5807 T4 15
valid_sources[0x51] 779795 1 T1 29 T3 5857 T4 18
valid_sources[0x52] 3396734 1 T1 20 T3 5822 T4 34
valid_sources[0x53] 792063 1 T1 25 T2 7363 T3 5756
valid_sources[0x54] 816121 1 T1 27 T3 5728 T4 25
valid_sources[0x55] 899090 1 T1 33 T3 5790 T4 35
valid_sources[0x56] 798159 1 T1 36 T3 5827 T4 18
valid_sources[0x57] 800398 1 T1 27 T3 5758 T4 34
valid_sources[0x58] 2187496 1 T1 42 T3 5726 T4 24
valid_sources[0x59] 795633 1 T1 19 T3 5712 T4 34
valid_sources[0x5a] 2218691 1 T1 27 T3 5861 T4 33
valid_sources[0x5b] 2308508 1 T1 23 T3 5709 T4 21
valid_sources[0x5c] 809569 1 T1 33 T3 5795 T4 24
valid_sources[0x5d] 785810 1 T1 19 T3 5813 T4 22
valid_sources[0x5e] 840391 1 T1 30 T3 5725 T4 26
valid_sources[0x5f] 784478 1 T1 24 T3 5662 T4 20
valid_sources[0x60] 865875 1 T1 31 T3 5717 T4 26
valid_sources[0x61] 783673 1 T1 32 T3 5831 T4 33
valid_sources[0x62] 844144 1 T1 25 T3 5815 T4 30
valid_sources[0x63] 785691 1 T1 31 T3 5842 T4 25
valid_sources[0x64] 785612 1 T1 29 T3 5697 T4 35
valid_sources[0x65] 2421857 1 T1 34 T3 5822 T4 19
valid_sources[0x66] 822690 1 T1 22 T3 5792 T4 35
valid_sources[0x67] 2362814 1 T1 21 T3 5874 T4 19
valid_sources[0x68] 836115 1 T1 30 T3 5716 T4 33
valid_sources[0x69] 785115 1 T1 26 T3 5766 T4 22
valid_sources[0x6a] 786649 1 T1 31 T3 5643 T4 22
valid_sources[0x6b] 808018 1 T1 19 T3 5639 T4 28
valid_sources[0x6c] 784959 1 T1 18 T3 5792 T4 17
valid_sources[0x6d] 791018 1 T1 25 T3 5685 T4 21
valid_sources[0x6e] 789548 1 T1 29 T3 5692 T4 29
valid_sources[0x6f] 795608 1 T1 22 T3 5812 T4 23
valid_sources[0x70] 2990194 1 T1 20 T3 5727 T4 27
valid_sources[0x71] 789433 1 T1 29 T3 5837 T4 23
valid_sources[0x72] 936487 1 T1 31 T3 5591 T4 24
valid_sources[0x73] 858123 1 T1 30 T3 5772 T4 22
valid_sources[0x74] 839867 1 T1 27 T3 5735 T4 34
valid_sources[0x75] 786717 1 T1 12 T3 5737 T4 31
valid_sources[0x76] 817849 1 T1 36 T3 5691 T4 21
valid_sources[0x77] 1475728 1 T1 25 T3 5751 T4 15
valid_sources[0x78] 782936 1 T1 15 T3 5761 T4 21
valid_sources[0x79] 800135 1 T1 18 T3 5707 T4 20
valid_sources[0x7a] 802930 1 T1 31 T3 5675 T4 29
valid_sources[0x7b] 787430 1 T1 30 T3 5646 T4 21
valid_sources[0x7c] 787744 1 T1 28 T3 5823 T4 27
valid_sources[0x7d] 2420654 1 T1 24 T3 5795 T4 21
valid_sources[0x7e] 786757 1 T1 21 T3 5727 T4 18
valid_sources[0x7f] 786275 1 T1 33 T3 5781 T4 25
valid_sources[0x80] 843534 1 T1 12 T3 5776 T4 15



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 53327308 1 T1 1452 T2 1471 T3 297063
values[0x0] all_enables biggest_size 43999591 1 T1 1148 T2 1038 T3 242121
values[0x1] all_enables biggest_size 38922318 1 T1 1138 T2 871 T3 211783

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%