Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

130241790

1

T1

2970

T2

3984

T3

723293

full_word

136292902

1

T1

3738

T2

3380

T3

750967

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	266534282	1			T1	6708		T2	7364		T3	147426
auto[TlIntgErrCmd]	137	1			T40	6		T57	6		T59	6
auto[TlIntgErrData]	139	1			T40	12		T57	10		T59	6
auto[TlIntgErrBoth]	134	1			T40	12		T57	4		T59	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

107554464

1

T1

3201

T2

3003

T3

594511

auto[1]

158980228

1

T1

3507

T2

4361

T3

879749

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrBoth]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	54209844	1			T1	1749		T2	1532		T3	297448
auto[TlIntgErrNone]	partial	auto[1]	76031554	1			T1	1221		T2	2452		T3	425845
auto[TlIntgErrNone]	full_word	auto[0]	53344432	1			T1	1452		T2	1471		T3	297063
auto[TlIntgErrNone]	full_word	auto[1]	82948452	1			T1	2286		T2	1909		T3	453904
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T40	2		T57	3		T59	2
auto[TlIntgErrCmd]	partial	auto[1]	70	1			T40	4		T57	2		T59	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T57	1		T59	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T137	1		T138	1		-	-
auto[TlIntgErrData]	partial	auto[0]	61	1			T40	5		T57	5		T59	2
auto[TlIntgErrData]	partial	auto[1]	72	1			T40	7		T57	4		T59	4
auto[TlIntgErrData]	full_word	auto[0]	4	1			T57	1		T139	1		T140	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T140	2		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	58	1			T40	4		T57	2		T59	2
auto[TlIntgErrBoth]	partial	auto[1]	72	1			T40	8		T57	2		T59	5
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T59	1		T141	2		T142	1