SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.hmac_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
98.42 | 100.00 | 93.75 | 100.00 | 100.00 | 96.77 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 2 | 2 | 100.00 | 2 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 2 | 2 | 100.00 | 2 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 1456552293 | 381869 | 0 | 0 |
intr_enable_rd_A | 1456552293 | 2102 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1456552293 | 381869 | 0 | 0 |
T39 | 489653 | 146518 | 0 | 0 |
T40 | 22105 | 11 | 0 | 0 |
T41 | 3158 | 9 | 0 | 0 |
T57 | 8721 | 8 | 0 | 0 |
T58 | 5108 | 720 | 0 | 0 |
T59 | 8394 | 6 | 0 | 0 |
T60 | 2858 | 491 | 0 | 0 |
T66 | 4576 | 116 | 0 | 0 |
T71 | 2091 | 279 | 0 | 0 |
T72 | 2492 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1456552293 | 2102 | 0 | 0 |
T64 | 684273 | 16 | 0 | 0 |
T73 | 0 | 19 | 0 | 0 |
T74 | 0 | 45 | 0 | 0 |
T75 | 0 | 42 | 0 | 0 |
T76 | 0 | 29 | 0 | 0 |
T77 | 0 | 4 | 0 | 0 |
T78 | 0 | 6 | 0 | 0 |
T79 | 0 | 15 | 0 | 0 |
T80 | 0 | 7 | 0 | 0 |
T81 | 0 | 14 | 0 | 0 |
T82 | 167018 | 0 | 0 | 0 |
T83 | 256336 | 0 | 0 | 0 |
T84 | 766038 | 0 | 0 | 0 |
T85 | 661437 | 0 | 0 | 0 |
T86 | 347498 | 0 | 0 | 0 |
T87 | 162094 | 0 | 0 | 0 |
T88 | 60766 | 0 | 0 | 0 |
T89 | 159920 | 0 | 0 | 0 |
T90 | 62762 | 0 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |