Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	116193962	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122332371

1

T1

5

T2

724378

T3

19124

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	96464278	1			T1	1		T2	568637		T3	20149
values[0x0]	66908511	1			T1	8		T2	408883		T3	10269
values[0x1]	75153544	1			T1	10		T2	458038		T3	12014

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	87081325	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151445008

1

T1

9

T2

900900

T3

24569

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	747146	1			T4	262		T7	8056		T10	5570
valid_sources[0x01]	730981	1			T4	261		T7	7951		T10	5207
valid_sources[0x02]	683744	1			T4	248		T7	7961		T10	5556
valid_sources[0x03]	705751	1			T4	287		T7	8166		T10	5544
valid_sources[0x04]	737339	1			T4	247		T7	7994		T10	5162
valid_sources[0x05]	683396	1			T4	248		T7	7886		T10	5218
valid_sources[0x06]	688664	1			T4	285		T7	7978		T10	5646
valid_sources[0x07]	2070532	1			T4	257		T7	8070		T10	5720
valid_sources[0x08]	782587	1			T4	242		T7	7977		T10	5519
valid_sources[0x09]	679189	1			T4	311		T7	7963		T10	5273
valid_sources[0x0a]	675610	1			T4	269		T7	7967		T10	5459
valid_sources[0x0b]	745470	1			T4	282		T7	7896		T10	5454
valid_sources[0x0c]	677259	1			T4	222		T7	7892		T10	5567
valid_sources[0x0d]	705412	1			T4	241		T7	8078		T10	5289
valid_sources[0x0e]	684219	1			T4	264		T7	7997		T10	5274
valid_sources[0x0f]	678722	1			T4	265		T7	8041		T10	5221
valid_sources[0x10]	691220	1			T4	286		T7	7972		T21	1
valid_sources[0x11]	685389	1			T4	255		T7	7983		T10	5333
valid_sources[0x12]	682201	1			T4	288		T7	8055		T10	5574
valid_sources[0x13]	2196888	1			T4	253		T7	8001		T10	5545
valid_sources[0x14]	1100670	1			T4	260		T7	7942		T10	5455
valid_sources[0x15]	739711	1			T4	258		T7	7895		T10	5178
valid_sources[0x16]	677845	1			T4	257		T7	7965		T10	5556
valid_sources[0x17]	755610	1			T4	261		T7	8038		T10	5513
valid_sources[0x18]	679469	1			T4	270		T7	7892		T10	5658
valid_sources[0x19]	718846	1			T4	256		T7	7895		T10	5552
valid_sources[0x1a]	678680	1			T4	294		T7	7870		T10	5704
valid_sources[0x1b]	691444	1			T4	276		T7	7850		T10	5567
valid_sources[0x1c]	784711	1			T4	242		T7	7810		T10	5565
valid_sources[0x1d]	684038	1			T4	273		T7	8030		T10	5555
valid_sources[0x1e]	713684	1			T4	264		T7	8039		T10	5376
valid_sources[0x1f]	747491	1			T4	241		T7	8074		T10	5284
valid_sources[0x20]	2217784	1			T4	298		T7	7845		T10	5353
valid_sources[0x21]	770124	1			T4	277		T7	8134		T10	5384
valid_sources[0x22]	680420	1			T4	228		T7	8055		T10	5398
valid_sources[0x23]	678262	1			T4	239		T7	8056		T21	1
valid_sources[0x24]	679146	1			T4	273		T7	8065		T10	5181
valid_sources[0x25]	686274	1			T4	258		T7	8131		T10	5557
valid_sources[0x26]	681314	1			T4	234		T7	7910		T10	5454
valid_sources[0x27]	681714	1			T4	245		T7	7987		T10	5495
valid_sources[0x28]	679123	1			T4	272		T7	8118		T10	5442
valid_sources[0x29]	682533	1			T4	276		T7	7977		T10	5209
valid_sources[0x2a]	698662	1			T4	274		T7	8011		T21	1
valid_sources[0x2b]	678778	1			T4	267		T7	8071		T10	5463
valid_sources[0x2c]	2076112	1			T4	274		T7	7995		T10	5399
valid_sources[0x2d]	716054	1			T4	256		T7	8046		T10	5361
valid_sources[0x2e]	678047	1			T4	279		T7	8011		T10	5212
valid_sources[0x2f]	727788	1			T1	7		T4	249		T7	7927
valid_sources[0x30]	682436	1			T4	246		T7	7834		T21	1
valid_sources[0x31]	677656	1			T4	291		T7	7891		T10	5588
valid_sources[0x32]	841068	1			T4	237		T7	7971		T10	5109
valid_sources[0x33]	719309	1			T4	258		T7	7833		T10	5319
valid_sources[0x34]	678228	1			T4	264		T7	8069		T10	5445
valid_sources[0x35]	679477	1			T4	257		T7	7928		T10	5615
valid_sources[0x36]	682787	1			T4	258		T7	8099		T10	5546
valid_sources[0x37]	717393	1			T4	262		T7	8151		T10	5441
valid_sources[0x38]	706974	1			T4	253		T7	7909		T10	5588
valid_sources[0x39]	676467	1			T4	272		T7	7828		T10	5544
valid_sources[0x3a]	1168100	1			T4	265		T7	7987		T10	5484
valid_sources[0x3b]	690352	1			T4	285		T7	7981		T10	5550
valid_sources[0x3c]	728552	1			T4	280		T7	7909		T10	5127
valid_sources[0x3d]	2134164	1			T4	290		T7	8022		T10	5428
valid_sources[0x3e]	687115	1			T4	255		T7	8056		T10	5334
valid_sources[0x3f]	676364	1			T4	261		T7	8008		T10	5296
valid_sources[0x40]	709442	1			T4	273		T7	7985		T10	5197
valid_sources[0x41]	762882	1			T4	251		T7	7970		T10	5571
valid_sources[0x42]	919216	1			T4	275		T7	8135		T10	5203
valid_sources[0x43]	710503	1			T4	270		T7	8092		T10	5640
valid_sources[0x44]	903359	1			T4	293		T7	8150		T10	5364
valid_sources[0x45]	738399	1			T4	266		T7	7870		T10	5314
valid_sources[0x46]	706397	1			T4	275		T7	7941		T10	5412
valid_sources[0x47]	675197	1			T4	271		T7	7951		T10	5391
valid_sources[0x48]	680203	1			T4	265		T7	7874		T10	5273
valid_sources[0x49]	694073	1			T4	258		T7	7992		T10	5591
valid_sources[0x4a]	733847	1			T4	233		T7	8262		T10	5415
valid_sources[0x4b]	759017	1			T4	274		T7	7920		T10	5425
valid_sources[0x4c]	763075	1			T4	252		T7	8069		T10	5531
valid_sources[0x4d]	715283	1			T4	269		T7	8039		T10	5307
valid_sources[0x4e]	682300	1			T4	273		T7	8128		T10	5665
valid_sources[0x4f]	2148965	1			T4	251		T7	8261		T10	5178
valid_sources[0x50]	5100394	1			T4	247		T7	8100		T10	5432
valid_sources[0x51]	3778586	1			T4	269		T7	7953		T10	5527
valid_sources[0x52]	681576	1			T4	262		T7	7874		T10	5344
valid_sources[0x53]	676755	1			T4	258		T7	7982		T10	5494
valid_sources[0x54]	679613	1			T4	249		T7	7887		T10	5513
valid_sources[0x55]	680779	1			T4	250		T7	7992		T10	5163
valid_sources[0x56]	802038	1			T4	272		T7	7877		T10	5500
valid_sources[0x57]	677978	1			T4	257		T7	8050		T10	5296
valid_sources[0x58]	676595	1			T4	257		T7	7970		T10	5701
valid_sources[0x59]	674808	1			T4	246		T7	7987		T10	5274
valid_sources[0x5a]	714001	1			T4	310		T7	7931		T10	5739
valid_sources[0x5b]	680132	1			T4	230		T7	7906		T10	5490
valid_sources[0x5c]	684035	1			T4	301		T7	8024		T10	5300
valid_sources[0x5d]	783747	1			T4	249		T7	8017		T10	5447
valid_sources[0x5e]	679894	1			T4	262		T7	7860		T21	1
valid_sources[0x5f]	2334710	1			T4	305		T7	8040		T10	5215
valid_sources[0x60]	685669	1			T4	261		T7	8096		T10	5700
valid_sources[0x61]	678850	1			T4	246		T20	1		T7	7969
valid_sources[0x62]	1084380	1			T4	263		T7	7897		T10	5428
valid_sources[0x63]	789198	1			T4	279		T7	8058		T10	5277
valid_sources[0x64]	677134	1			T4	258		T7	8011		T10	5525
valid_sources[0x65]	2370616	1			T4	267		T7	8006		T10	5295
valid_sources[0x66]	792724	1			T4	254		T7	7841		T10	5610
valid_sources[0x67]	680445	1			T4	237		T7	7963		T10	5373
valid_sources[0x68]	675494	1			T19	7		T4	265		T7	8109
valid_sources[0x69]	726907	1			T4	262		T7	8021		T10	5375
valid_sources[0x6a]	699923	1			T4	296		T7	7909		T10	5413
valid_sources[0x6b]	681569	1			T4	255		T7	7846		T10	5337
valid_sources[0x6c]	674763	1			T4	264		T7	8108		T10	5296
valid_sources[0x6d]	2157834	1			T4	288		T7	8021		T10	5264
valid_sources[0x6e]	1295389	1			T4	261		T7	7932		T10	5543
valid_sources[0x6f]	680871	1			T4	253		T7	7965		T10	5507
valid_sources[0x70]	679128	1			T4	261		T7	7911		T10	5090
valid_sources[0x71]	682797	1			T4	265		T7	7984		T10	5377
valid_sources[0x72]	2132377	1			T4	304		T7	7925		T10	5294
valid_sources[0x73]	676458	1			T4	302		T7	7991		T10	5639
valid_sources[0x74]	680787	1			T4	266		T7	7952		T10	5246
valid_sources[0x75]	679792	1			T4	287		T7	8109		T10	5279
valid_sources[0x76]	678207	1			T4	264		T7	7906		T10	5598
valid_sources[0x77]	727317	1			T4	297		T7	7881		T10	5652
valid_sources[0x78]	710589	1			T4	256		T7	8198		T10	5535
valid_sources[0x79]	785710	1			T4	250		T7	7931		T10	5270
valid_sources[0x7a]	675706	1			T4	258		T7	7736		T10	5445
valid_sources[0x7b]	734629	1			T4	274		T7	8022		T10	5106
valid_sources[0x7c]	687549	1			T4	241		T7	8027		T10	5377
valid_sources[0x7d]	704797	1			T4	264		T7	8109		T10	5447
valid_sources[0x7e]	676442	1			T4	297		T7	7997		T21	1
valid_sources[0x7f]	677553	1			T4	240		T7	7978		T10	5237
valid_sources[0x80]	2249612	1			T4	276		T7	7905		T10	5349

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

47937769

1

T2

284266

T3

10054

T4

13766

values[0x0]

all_enables

biggest_size

39472457

1

T1

5

T2

235527

T3

4970

values[0x1]

all_enables

biggest_size

34922145

1

T2

204585

T3

4100

T4

8364