Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

117272267

1

T1

14

T2

711180

T3

23308

full_word

122402563

1

T1

5

T2

724378

T3

19124

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	239674430	1			T1	19		T2	143555		T3	42432
auto[TlIntgErrCmd]	135	1			T34	10		T42	8		T43	9
auto[TlIntgErrData]	133	1			T34	5		T42	6		T43	10
auto[TlIntgErrBoth]	132	1			T34	5		T42	6		T43	11

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96829170

1

T1

1

T2

568637

T3

20149

auto[1]

142845660

1

T1

18

T2

866921

T3

22283

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	48863566	1			T1	1		T2	284371		T3	10095
auto[TlIntgErrNone]	partial	auto[1]	68408335	1			T1	13		T2	426809		T3	13213
auto[TlIntgErrNone]	full_word	auto[0]	47965419	1			T2	284266		T3	10054		T4	13766
auto[TlIntgErrNone]	full_word	auto[1]	74437110	1			T1	5		T2	440112		T3	9070
auto[TlIntgErrCmd]	partial	auto[0]	52	1			T34	2		T42	3		T43	3
auto[TlIntgErrCmd]	partial	auto[1]	71	1			T34	5		T42	5		T43	6
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T79	1		T141	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T34	3		T54	2		T79	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T34	2		T42	4		T43	5
auto[TlIntgErrData]	partial	auto[1]	61	1			T34	1		T42	2		T43	4
auto[TlIntgErrData]	full_word	auto[0]	5	1			T34	2		T137	1		T142	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T43	1		T54	2		T53	1
auto[TlIntgErrBoth]	partial	auto[0]	60	1			T34	3		T42	1		T43	8
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T34	2		T42	4		T43	2
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T42	1		T43	1		T79	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T53	1		T79	1		T137	2