Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.42	100.00	93.75	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1351828161	617552	0	0
intr_enable_rd_A	1351828161	3321	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1351828161	617552	0	0
T18	314276	118241	0	0
T23	38161	0	0	0
T34	0	6	0	0
T35	0	28	0	0
T40	0	8	0	0
T41	0	730	0	0
T42	0	8	0	0
T43	0	6	0	0
T44	0	431	0	0
T53	0	10	0	0
T54	0	12	0	0
T55	1160	0	0	0
T56	99876	0	0	0
T57	247260	0	0	0
T58	969090	0	0	0
T59	895	0	0	0
T60	400675	0	0	0
T61	161614	0	0	0
T62	1035	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1351828161	3321	0	0
T34	0	168	0	0
T35	0	26	0	0
T54	0	269	0	0
T63	348832	53	0	0
T64	0	3	0	0
T65	0	71	0	0
T66	0	43	0	0
T67	0	25	0	0
T68	0	5	0	0
T69	0	9	0	0
T70	64893	0	0	0
T71	551595	0	0	0
T72	199535	0	0	0
T73	93212	0	0	0
T74	1134	0	0	0
T75	33879	0	0	0
T76	827388	0	0	0
T77	176087	0	0	0
T78	199309	0	0	0