Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

47951500

1

T1

60322

T2

36124

T3

1127

full_word

42154824

1

T1

48047

T2

29605

T3

1176

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	90105874	1			T1	108369		T2	65729		T3	2303
auto[TlIntgErrCmd]	167	1			T56	9		T57	7		T58	6
auto[TlIntgErrData]	152	1			T56	8		T57	8		T58	7
auto[TlIntgErrBoth]	131	1			T56	13		T57	5		T58	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

42175619

1

T1

54631

T2

32938

T3

1162

auto[1]

47930705

1

T1

53738

T2

32791

T3

1141

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	21900148	1			T1	27342		T2	16457		T3	588
auto[TlIntgErrNone]	partial	auto[1]	26050953	1			T1	32980		T2	19667		T3	539
auto[TlIntgErrNone]	full_word	auto[0]	20275274	1			T1	27289		T2	16481		T3	574
auto[TlIntgErrNone]	full_word	auto[1]	21879499	1			T1	20758		T2	13124		T3	602
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T56	1		T57	1		T58	2
auto[TlIntgErrCmd]	partial	auto[1]	85	1			T56	6		T57	5		T58	3
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T129	1		T130	1		T131	1
auto[TlIntgErrCmd]	full_word	auto[1]	16	1			T56	2		T57	1		T58	1
auto[TlIntgErrData]	partial	auto[0]	72	1			T56	4		T57	4		T58	3
auto[TlIntgErrData]	partial	auto[1]	64	1			T56	2		T57	4		T58	4
auto[TlIntgErrData]	full_word	auto[0]	8	1			T130	1		T132	1		T133	2
auto[TlIntgErrData]	full_word	auto[1]	8	1			T56	2		T126	1		T132	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T56	4		T57	4		T58	2
auto[TlIntgErrBoth]	partial	auto[1]	74	1			T56	8		T57	1		T58	5
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T134	1		T130	1		T59	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T56	1		T59	1		T132	1