Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.44	100.00	93.85	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	441523390	2136344	0	0
intr_enable_rd_A	441523390	3133	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441523390	2136344	0	0
T9	110677	374707	0	0
T10	0	103343	0	0
T11	0	281280	0	0
T16	0	136308	0	0
T22	0	136223	0	0
T23	0	280715	0	0
T24	0	39764	0	0
T60	0	24919	0	0
T61	0	217203	0	0
T62	0	58481	0	0
T63	33571	0	0	0
T64	380154	0	0	0
T65	377235	0	0	0
T66	187042	0	0	0
T67	223877	0	0	0
T68	378569	0	0	0
T69	186195	0	0	0
T70	29696	0	0	0
T71	998	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	441523390	3133	0	0
T10	0	226	0	0
T16	0	97	0	0
T19	58522	0	0	0
T20	195912	0	0	0
T40	1115	0	0	0
T72	804950	28	0	0
T73	0	17	0	0
T74	0	55	0	0
T75	0	35	0	0
T76	0	44	0	0
T77	0	61	0	0
T78	0	61	0	0
T79	0	29	0	0
T80	557969	0	0	0
T81	12495	0	0	0
T82	34681	0	0	0
T83	56035	0	0	0
T84	430694	0	0	0
T85	102140	0	0	0