Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_hmac_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 41126579 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 39738120 1 T1 5356 T2 48 T3 5614



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 38197456 1 T1 3644 T2 35 T3 5636
values[0x0] 20007141 1 T1 2601 T2 17 T3 2543
values[0x1] 22660102 1 T1 2635 T2 17 T3 2939



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 31613586 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 49251113 1 T1 6061 T2 51 T3 6958



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 251088 1 T3 50 T5 103 T4 1507
valid_sources[0x01] 246285 1 T3 54 T5 121 T4 663
valid_sources[0x02] 244671 1 T3 49 T5 103 T4 939
valid_sources[0x03] 248723 1 T3 44 T5 124 T4 1048
valid_sources[0x04] 245355 1 T3 45 T5 91 T4 783
valid_sources[0x05] 246519 1 T3 41 T5 137 T4 1025
valid_sources[0x06] 247284 1 T3 34 T5 110 T4 1179
valid_sources[0x07] 470579 1 T3 36 T5 117 T4 1577
valid_sources[0x08] 266642 1 T2 1 T3 48 T5 143
valid_sources[0x09] 243657 1 T3 48 T5 143 T4 418
valid_sources[0x0a] 849327 1 T3 30 T5 106 T4 522
valid_sources[0x0b] 246187 1 T3 37 T5 139 T4 1320
valid_sources[0x0c] 324449 1 T2 2 T3 52 T5 114
valid_sources[0x0d] 308977 1 T3 50 T5 116 T4 1525
valid_sources[0x0e] 303032 1 T3 33 T5 123 T4 1174
valid_sources[0x0f] 294145 1 T3 51 T5 131 T4 881
valid_sources[0x10] 247810 1 T3 24 T5 114 T4 951
valid_sources[0x11] 249687 1 T3 46 T5 142 T4 983
valid_sources[0x12] 386164 1 T3 34 T5 91 T4 1162
valid_sources[0x13] 243879 1 T3 65 T5 139 T4 402
valid_sources[0x14] 246627 1 T3 50 T5 114 T4 739
valid_sources[0x15] 244637 1 T3 65 T5 93 T4 795
valid_sources[0x16] 273721 1 T3 35 T5 160 T4 284
valid_sources[0x17] 248068 1 T2 1 T3 50 T5 127
valid_sources[0x18] 247110 1 T2 5 T3 31 T5 167
valid_sources[0x19] 272201 1 T3 44 T5 129 T4 521
valid_sources[0x1a] 301249 1 T3 50 T5 130 T4 734
valid_sources[0x1b] 244272 1 T3 43 T5 128 T4 267
valid_sources[0x1c] 253051 1 T3 51 T5 124 T4 557
valid_sources[0x1d] 244629 1 T3 53 T5 130 T4 938
valid_sources[0x1e] 253073 1 T3 19 T5 125 T4 498
valid_sources[0x1f] 246599 1 T3 57 T5 93 T4 974
valid_sources[0x20] 479501 1 T3 17 T5 162 T4 741
valid_sources[0x21] 2231018 1 T3 36 T5 137 T4 1051
valid_sources[0x22] 321462 1 T3 31 T5 101 T4 548
valid_sources[0x23] 247903 1 T3 22 T5 125 T4 457
valid_sources[0x24] 308620 1 T3 33 T5 146 T4 1606
valid_sources[0x25] 336441 1 T3 39 T5 128 T4 981
valid_sources[0x26] 932207 1 T3 40 T5 125 T4 878
valid_sources[0x27] 245955 1 T3 70 T5 136 T4 1162
valid_sources[0x28] 244775 1 T3 51 T5 99 T4 1491
valid_sources[0x29] 248486 1 T3 58 T5 111 T4 972
valid_sources[0x2a] 286002 1 T2 4 T3 38 T5 83
valid_sources[0x2b] 243478 1 T3 53 T5 122 T4 806
valid_sources[0x2c] 244194 1 T3 40 T5 120 T4 1285
valid_sources[0x2d] 243974 1 T3 41 T5 123 T4 494
valid_sources[0x2e] 245914 1 T3 37 T5 138 T4 395
valid_sources[0x2f] 248227 1 T3 18 T5 130 T4 810
valid_sources[0x30] 247726 1 T3 41 T5 119 T4 932
valid_sources[0x31] 244996 1 T3 42 T5 132 T4 614
valid_sources[0x32] 247828 1 T3 38 T5 107 T4 847
valid_sources[0x33] 303314 1 T3 32 T5 122 T4 731
valid_sources[0x34] 292625 1 T3 53 T5 143 T4 873
valid_sources[0x35] 245078 1 T3 69 T5 131 T4 1524
valid_sources[0x36] 249993 1 T3 75 T5 84 T4 1523
valid_sources[0x37] 332934 1 T3 50 T5 143 T4 963
valid_sources[0x38] 245965 1 T3 52 T5 118 T4 640
valid_sources[0x39] 246599 1 T3 37 T5 148 T4 418
valid_sources[0x3a] 246740 1 T3 40 T5 118 T4 684
valid_sources[0x3b] 248242 1 T3 52 T5 82 T4 1256
valid_sources[0x3c] 245414 1 T2 2 T3 33 T5 109
valid_sources[0x3d] 258477 1 T3 77 T5 82 T4 1275
valid_sources[0x3e] 386181 1 T3 49 T5 157 T4 873
valid_sources[0x3f] 244599 1 T3 48 T5 139 T4 836
valid_sources[0x40] 250872 1 T3 40 T5 125 T4 1123
valid_sources[0x41] 799146 1 T3 37 T5 141 T4 679
valid_sources[0x42] 245237 1 T3 31 T5 118 T4 920
valid_sources[0x43] 354961 1 T3 44 T5 115 T4 889
valid_sources[0x44] 242043 1 T3 40 T5 128 T4 832
valid_sources[0x45] 245569 1 T3 32 T5 96 T4 216
valid_sources[0x46] 248655 1 T3 54 T5 123 T4 221
valid_sources[0x47] 245623 1 T3 33 T5 103 T4 383
valid_sources[0x48] 423288 1 T3 34 T5 184 T4 637
valid_sources[0x49] 376949 1 T3 63 T5 149 T4 1274
valid_sources[0x4a] 247174 1 T3 38 T5 112 T4 846
valid_sources[0x4b] 246429 1 T3 29 T5 142 T4 1386
valid_sources[0x4c] 582823 1 T3 41 T5 153 T4 1090
valid_sources[0x4d] 250192 1 T3 47 T5 116 T4 1501
valid_sources[0x4e] 243091 1 T3 43 T5 116 T4 911
valid_sources[0x4f] 266001 1 T3 36 T5 117 T4 1879
valid_sources[0x50] 245819 1 T3 28 T5 118 T4 1450
valid_sources[0x51] 243058 1 T3 30 T5 149 T4 906
valid_sources[0x52] 249081 1 T3 44 T5 145 T4 1374
valid_sources[0x53] 246720 1 T3 70 T5 131 T4 1147
valid_sources[0x54] 243138 1 T3 62 T5 117 T4 899
valid_sources[0x55] 244997 1 T3 30 T5 136 T4 1172
valid_sources[0x56] 243260 1 T3 59 T5 128 T4 1210
valid_sources[0x57] 350462 1 T3 35 T5 110 T4 173
valid_sources[0x58] 753884 1 T3 64 T5 100 T4 1119
valid_sources[0x59] 247469 1 T3 68 T5 101 T4 789
valid_sources[0x5a] 881480 1 T3 30 T5 155 T4 1117
valid_sources[0x5b] 245425 1 T3 51 T5 99 T4 485
valid_sources[0x5c] 276546 1 T3 54 T5 119 T4 1177
valid_sources[0x5d] 246533 1 T3 47 T5 90 T4 1083
valid_sources[0x5e] 266133 1 T3 22 T5 158 T4 1072
valid_sources[0x5f] 250384 1 T3 41 T5 64 T4 1074
valid_sources[0x60] 246032 1 T3 34 T5 118 T4 1546
valid_sources[0x61] 254870 1 T3 55 T5 139 T4 1162
valid_sources[0x62] 250878 1 T3 64 T5 158 T4 791
valid_sources[0x63] 246228 1 T3 39 T5 127 T4 2406
valid_sources[0x64] 245835 1 T3 46 T5 90 T4 524
valid_sources[0x65] 243655 1 T3 29 T5 97 T4 279
valid_sources[0x66] 279475 1 T3 36 T5 124 T4 1960
valid_sources[0x67] 249526 1 T3 41 T5 121 T4 754
valid_sources[0x68] 248059 1 T3 48 T5 128 T4 461
valid_sources[0x69] 250446 1 T3 40 T5 120 T4 1698
valid_sources[0x6a] 258906 1 T3 45 T5 104 T4 1533
valid_sources[0x6b] 241961 1 T3 40 T5 117 T4 1238
valid_sources[0x6c] 245333 1 T3 33 T5 193 T4 735
valid_sources[0x6d] 240581 1 T3 47 T5 112 T4 360
valid_sources[0x6e] 246691 1 T3 23 T5 106 T4 1152
valid_sources[0x6f] 244543 1 T3 40 T5 105 T4 828
valid_sources[0x70] 720576 1 T2 8 T3 39 T5 106
valid_sources[0x71] 248987 1 T3 60 T5 136 T4 681
valid_sources[0x72] 246558 1 T3 46 T5 114 T4 756
valid_sources[0x73] 353064 1 T3 27 T5 136 T4 1006
valid_sources[0x74] 245541 1 T3 48 T5 116 T4 1030
valid_sources[0x75] 2148313 1 T3 42 T5 143 T4 572
valid_sources[0x76] 244803 1 T3 46 T5 161 T4 1146
valid_sources[0x77] 247913 1 T3 54 T5 146 T4 283
valid_sources[0x78] 248895 1 T3 41 T5 156 T4 617
valid_sources[0x79] 245491 1 T3 72 T5 115 T4 1317
valid_sources[0x7a] 244390 1 T2 1 T3 47 T5 142
valid_sources[0x7b] 245803 1 T3 36 T5 128 T4 548
valid_sources[0x7c] 266204 1 T3 35 T5 118 T4 874
valid_sources[0x7d] 246552 1 T3 30 T5 149 T4 779
valid_sources[0x7e] 245455 1 T3 36 T5 97 T4 1046
valid_sources[0x7f] 288014 1 T3 29 T5 158 T4 871
valid_sources[0x80] 247076 1 T3 53 T5 106 T4 703



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 18861262 1 T1 1763 T2 14 T3 2722
values[0x0] all_enables biggest_size 11212674 1 T1 1883 T2 17 T3 1493
values[0x1] all_enables biggest_size 9664184 1 T1 1710 T2 17 T3 1399

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%