SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[hmac_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 64238081 | 1 | T1 | 5512 | T2 | 69 | T3 | 9128 | ||||
auto[1] | 20748435 | 1 | T1 | 3368 | T3 | 1990 | T5 | 6071 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 84986247 | 1 | T1 | 8880 | T2 | 69 | T3 | 11118 | ||||
values[1] | 30 | 1 | T55 | 2 | T56 | 2 | T105 | 2 | ||||
values[2] | 5 | 1 | T57 | 2 | T105 | 1 | T106 | 1 | ||||
values[3] | 138 | 1 | T55 | 9 | T56 | 5 | T57 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 84986270 | 1 | T1 | 8880 | T2 | 69 | T3 | 11118 | ||||
values[1] | 25 | 1 | T105 | 1 | T107 | 1 | T108 | 2 | ||||
values[2] | 9 | 1 | T107 | 3 | T109 | 1 | T110 | 1 | ||||
values[3] | 116 | 1 | T55 | 7 | T56 | 7 | T57 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 84986136 | 1 | T1 | 8880 | T2 | 69 | T3 | 11118 | ||||
auto[TlIntgErrCmd] | 134 | 1 | T55 | 10 | T56 | 3 | T57 | 4 | ||||
auto[TlIntgErrData] | 111 | 1 | T55 | 4 | T56 | 9 | T57 | 4 | ||||
auto[TlIntgErrBoth] | 135 | 1 | T55 | 6 | T56 | 8 | T57 | 2 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |