Unified Coverage Report :: Module :: hmac_csr_assert_fpv

Module : hmac_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_hmac_csr_assert_0/hmac_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.hmac_csr_assert	100.00						100.00

---

Module Instance : tb.dut.hmac_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.44	100.00	93.85	100.00	100.00	96.77	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : hmac_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	409002510	2235577	0	0
intr_enable_rd_A	409002510	4815	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409002510	2235577	0	0
T10	671581	0	0	0
T12	128483	173204	0	0
T13	0	115383	0	0
T14	0	354698	0	0
T16	0	37589	0	0
T19	0	100978	0	0
T20	0	23272	0	0
T24	0	203055	0	0
T30	0	200863	0	0
T31	305497	0	0	0
T49	5387	0	0	0
T54	306268	0	0	0
T55	0	8	0	0
T58	0	216516	0	0
T59	23660	0	0	0
T60	28375	0	0	0
T61	155234	0	0	0
T62	298792	0	0	0
T63	94130	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	409002510	4815	0	0
T11	724012	28	0	0
T15	907899	0	0	0
T19	0	47	0	0
T20	0	17	0	0
T21	246303	0	0	0
T23	19679	0	0	0
T25	238945	0	0	0
T42	128049	0	0	0
T47	321491	0	0	0
T48	384408	0	0	0
T57	0	75	0	0
T64	0	57	0	0
T65	0	15	0	0
T66	0	18	0	0
T67	0	19	0	0
T68	0	44	0	0
T69	0	25	0	0
T70	326615	0	0	0
T71	372727	0	0	0