Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[hmac_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

45602498

1

T1

4148

T2

38239

T3

351021

full_word

40195982

1

T1

3594

T2

30712

T3

351852

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	85798150	1			T1	7742		T2	68951		T3	702873
auto[TlIntgErrCmd]	104	1			T68	8		T69	2		T70	5
auto[TlIntgErrData]	109	1			T68	9		T69	4		T70	2
auto[TlIntgErrBoth]	117	1			T68	13		T69	4		T70	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

39956124

1

T1

3856

T2

34530

T3

331533

auto[1]

45842356

1

T1

3886

T2

34421

T3

371340

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	20742499	1			T1	1942		T2	17268		T3	175291
auto[TlIntgErrNone]	partial	auto[1]	24859695	1			T1	2206		T2	20971		T3	175730
auto[TlIntgErrNone]	full_word	auto[0]	19213488	1			T1	1914		T2	17262		T3	156242
auto[TlIntgErrNone]	full_word	auto[1]	20982468	1			T1	1680		T2	13450		T3	195610
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T68	4		T70	2		T129	1
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T68	4		T69	2		T70	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T131	1		T133	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T129	1		T134	1		T72	1
auto[TlIntgErrData]	partial	auto[0]	47	1			T68	5		T69	2		T70	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T68	4		T69	2		T70	1
auto[TlIntgErrData]	full_word	auto[0]	7	1			T134	1		T135	1		T132	1
auto[TlIntgErrData]	full_word	auto[1]	3	1			T129	1		T135	1		T136	1
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T68	5		T69	1		T70	1
auto[TlIntgErrBoth]	partial	auto[1]	68	1			T68	7		T69	2		T70	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T68	1		T69	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T135	1		T131	1		T137	1